Modul 3 PLD, VHDL, PLD, VHDL, Latches Latches, , FlipFlip--Flops...
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Digital Design 2010 DE2 1 1 Modul 3 Modul 3 PLD, VHDL, PLD, VHDL, Latches Latches, , Flip Flip-Flops & Flops & Counters Counters 2
Transcript of Modul 3 PLD, VHDL, PLD, VHDL, Latches Latches, , FlipFlip--Flops...
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Modul 3Modul 3
PLD, VHDL, PLD, VHDL, LatchesLatches, , FlipFlip--Flops & Flops & CountersCounters
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Cou te sCou te s
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PLAPLAPALPALPLDPLDCPLDCPLDFPGAFPGA
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FPGAFPGAASICASIC
PLA contains a 2 level structure of AND and OR gates with userprogrammable connections (sum of the product basically min terms)programmable connections (sum of the product, basically min terms).
PLA structure was enhanced to PAL programmable logic arrays and todaysuch devices are called PLD programmable Logic Devices.
However, PAL lack scalability as the 2 level cannot be scaled to larger sizes,so instead of PLD, CPLD Complex PLD are introduced which basicallycontains large number of PLDs and interconnection structure that is alsoprogrammable so providing a rich design capability.
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programmable so providing a rich design capability.
The later version of CPLD which contains large number of individual blocksis called FPGA.
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Sum of the product: AND gates providethe product and OR gates as sum.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
The only limitation here is size of thedevice as the number of input and outputpins and the number of product termsavailable.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
To make it more flexible and enhancing the capability of these circuits an inputdriver with true and negated option.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
In PAL, only AND gates are programmable where as OR gates are fixed, so there is a limit on producing product terms in sum.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
In this case both are programmable, so product terms are re-usable.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
This is just the extension of PLA, it contains a flip-flop as a storageelement and typically the output of the flip-flop is fed back to the logic tosupport finite state machine design.
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One time: One time: Antifuse (Metal crystalline alloy is created for conduction.
Reprogrammable: Floating Gate.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Floating Gate
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Initially, floating gate has no charge so it has no effect on circuitoperation and all transistors are effectively connected, to programthe logic high voltage is applied to the link where no connection isrequired.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Through avalanche injection a negative charge is placed to the floating gateso once you apply a normal 1 logic transistor does not turned on and typicallyit is believed that the charge remains there for 10 years. Ultraviolet light wasused to erase the device, because it becomes conductive under ultravioletlight.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Modern devices are manufactured in a different way using a tunneling effect, the advantage is that one can electronically erase the device.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
PLD and CPLD has coarse grain architecture meaning fewer interconnections, where as FPGA has fine grain architecture having a rich inter connection topology. Generic (GAL) Gate Array logic is also a PAL as shown in figure.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Output which contains a flip-flop is called registered output where as the other is obviously called un-registered output.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
Contains 6 logic block with each containing 6 macro-cell, interconnection issupported at different levels some may be connected some may be not.
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The basic logic blocks are much simpler than the CPLD, but it is fine grain interconnection topology.
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Embedded Systems: A Contemporary Design Tool by James K. Peckol
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Output which contains a flip-flop is called registered output .
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tPD : Propogation delaytCO : Propagation delay from the rising edge of the clocktCF : PD from the rising edge of the clock to the macrocell’s outputtSU : Setup time during which signal must be stabletH : Signal at D input must be hold for that period of time
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It should be remembered that timing parameters in PLDs have longer setup times because ofAND & OR gates, so for critical timing requirements it should be kept in mind forimplementation.
Which gate is faster ?
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HDL and HDL and VerilogVerilog are hardware description languages.are hardware description languages.
HDL has its root in PASCAL & ADA HDL has its root in PASCAL & ADA
WhWh V ilV il h it t i Ch it t i C
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Where as Where as VerilogVerilog has its root in C. has its root in C.
Documentation and Modelling Language
Developed and designed with principles of structured programming in mind (ideas from PASCAL and Ada).
Design is decomposed.Each design element has both well defined interface and precise functional specifications.Concurrency, timing and clocking can be modelled.
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Logical operations and timing behaviour can be simulated.
VHDL is basically, VHSIC Hardware Description Language, Very High Speed Integrated Circuits HDL.
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Entity is declaration of modules input and output. It is like a wrapper hiding h d il f h i i id
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the details of what is inside.
Where as architecture is more detailed description of the modules internal behavior or structure. This allows a hierarchical design.
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Inside the text file entity and architecture is defined separately.
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Before we start going into any language we must understand the overall language in this VHDL d i flcase VHDL design flow.
It is divided into 2 parts, front end and back end.
Typically, large logic designs has the capacity to be divided into blocks of different functionality so one can have a hierarchical structure.
Verification or testing has 2 dimensions, functional verification which is concerned with logical behaviour of the circuit where as timing is concerned with more on gate delays etc, so in this case one test the actual delay verses the estimated delay However in the front end
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so in this case one test the actual delay verses the estimated delay. However, in the front end it is still limited verification.
In the back end the design is converted into set of primitives which can be assembled into the target technology (PLD/CPLD etc). Fitting is mapping to the technology. Final step is the timing verification due to many things including length of wires etc.
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For ReferenceFor Reference
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For ReferenceFor Reference
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A collection of 2 or more D type flip flops with acommon clock is called a register, registers are usedto store collection of related bits. Constraint is that allthe bits gets updated with the same clock.
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If EN_L is asserted then at the rising edge of clock the flip flops are loadedwith the data inputs, otherwise they retain their present values.
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The reason of having latching the address is that typically address busand data bus are multiplexed in 3 state logic to save pins. ROMCS_L isROM chip select effective low.
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In this case the higher order bits (12 bits) are used for chip select, where as the20 lower order bits are used for address location of the selected device.
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It may produce quick chip select for devices, higher order address bits are directlygiven to latching decoder and the address valid is also applied directly to latchingdecoder.
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Most commonly used counter is n bit binary counter. This is a ripple binarycounter as carry is propagated to the next counter, one bit at a time.
T is the toggle flip flop which changes (toggles) its state at each clock pulse.
Ri l t l d i i if it i l i l t th
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Ripple counters are slow and one can imagine if it is a large ripple counter themost significant output may not be valid because of the propagation delay.
The counter shown is with a Serial Enable, it is called serial counter because thecombinational enable signal propagate serial from LSB to MSB. It can haveproblem if the clock period is two short, it will not have enough time that LSBchange is propagated to MSB
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The counter with Parallel Enable, which eliminates the problem and this is thefastest binary counter structure
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If you look at the 4 output signals it can be realised easily that each output isdivided by 2 at each step, so the counter can be used as divide by 2, 4, 8 and 16counter.
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