1 ECE 545—Digital System Design with VHDL Lecture 1 Digital Logic Review.
George Mason University ECE 545 – Introduction to VHDL ECE 545 Lecture 5 Finite State Machines.
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Transcript of George Mason University ECE 545 – Introduction to VHDL ECE 545 Lecture 5 Finite State Machines.
ECE 545 – Introduction to VHDL 3
Arrays of std_logic_vectors
. . . . . . . . . .
32
32
32
32
32
32
1
M
L(0)
L(1)
L(2)
L(3)
L(M-1)
L(M)
REP_BLOCK
REP_BLOCK
REP_BLOCK
REP_BLOCK
2
3
. . .
ECE 545 – Introduction to VHDL 4
Arrays of std_logic_vectors
TYPE sig_array IS ARRAY(0 TO M) OF STD_LOGIC_VECTOR(31 DOWNTO 0);…SIGNAL L: sig_array;…BEGIN
L(0) <= A;CASCADE: for I in 1 to M generate
C: REP_BLOCK port map(REP_IN => L(I-1), REP_OUT=>L(I)); END GENERATE;
Z <= L(M);END Structural;
ECE 545 – Introduction to VHDL 5
Finite State Machine Resources
• Volnei A. Pedroni, Circuit Design with VHDL
Chapter 8, State Machines
• Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right
Chapter 6, Finite State Machines
Chapter 10, Getting the Most from Your State
Machine
ECE 545 – Introduction to VHDL 6
Structure of a Typical Digital System
Execution Unit
(Datapath)
Control Unit
(Control)
Data Inputs
Data Outputs
Control Inputs
Control Outputs
Control Signals
ECE 545 – Introduction to VHDL 7
Execution Unit (Datapath)
• Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task
• Examples of Resources• Adders, Multipliers, Registers, Memories, etc.
ECE 545 – Introduction to VHDL 8
Control Unit (Control)
• Controls Data Movements in an Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources
• Follows Some ‘Program’ or Schedule
• Often Implemented as Finite State Machine
or collection of Finite State Machines
ECE 545 – Introduction to VHDL 10
Finite State Machines (FSMs)
• Any Circuit with Memory Is a Finite State Machine• Even computers can be viewed as huge FSMs
• Design of FSMs Involves• Defining states• Defining transitions between states• Optimization / minimization
• Above Approach Is Practical for Small FSMs Only
ECE 545 – Introduction to VHDL 11
Moore FSM
• Output Is a Function of a Present State Only
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clockreset
ECE 545 – Introduction to VHDL 12
Mealy FSM• Output Is a Function of a Present State and
Inputs
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clockreset
ECE 545 – Introduction to VHDL 13
Moore Machine
state 1 /output 1
state 2 /output 2
transitioncondition 1
transitioncondition 2
ECE 545 – Introduction to VHDL 14
Mealy Machine
state 1 state 2
transition condition 1 /output 1
transition condition 2 /output 2
ECE 545 – Introduction to VHDL 15
Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be Functionally Equivalent• Equivalent Mealy FSM can be derived from
Moore FSM and vice versa
• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States• Smaller circuit area
ECE 545 – Introduction to VHDL 16
Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as Inputs Change• Mealy FSM responds one clock cycle sooner
than equivalent Moore FSM
• Moore FSM Has No Combinational Path Between Inputs and Outputs• Moore FSM is more likely to have a shorter
critical path
ECE 545 – Introduction to VHDL 17
Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
ECE 545 – Introduction to VHDL 18
Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
ECE 545 – Introduction to VHDL 19
Moore & Mealy FSMs – Example 1
clock
input
Moore
Mealy
0 1 0 0 0
S0 S1 S2 S0 S0
S0 S1 S0 S0 S0
ECE 545 – Introduction to VHDL 21
FSMs in VHDL
• Finite State Machines Can Be Easily Described With Processes
• Synthesis Tools Understand FSM Description If Certain Rules Are Followed• State transitions should be described in a
process sensitive to clock and asynchronous reset signals only
• Outputs described as concurrent statements outside the process
ECE 545 – Introduction to VHDL 22
Moore FSM
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
clockreset
process(clock, reset)
concurrent statements
ECE 545 – Introduction to VHDL 23
Mealy FSM
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clockreset
process(clock, reset)
concurrent statements
ECE 545 – Introduction to VHDL 24
Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
ECE 545 – Introduction to VHDL 25
Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)BEGIN
IF(reset = ‘1’) THENMoore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS
WHEN S0 => IF input = ‘1’ THEN
Moore_state <= S1; ELSE Moore_state <= S0; END IF;
ECE 545 – Introduction to VHDL 26
Moore FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Moore_state <= S2; ELSE Moore_state <= S1; END IF;
WHEN S2 => IF input = ‘0’ THEN
Moore_state <= S0; ELSE
Moore_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
ECE 545 – Introduction to VHDL 27
Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
ECE 545 – Introduction to VHDL 28
Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)BEGIN
IF(reset = ‘1’) THENMealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS
WHEN S0 => IF input = ‘1’ THEN
Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
ECE 545 – Introduction to VHDL 29
Mealy FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0; ELSE Mealy_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
ECE 545 – Introduction to VHDL 30
Moore FSM – Example 2: State diagram
C z 1 =
resetn
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
ECE 545 – Introduction to VHDL 31
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM – Example 2: State table
ECE 545 – Introduction to VHDL 32
Moore FSM
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y
Next State
Output: z
clockresetn
process(clock, reset)
concurrent statements
ECE 545 – Introduction to VHDL 33
USE ieee.std_logic_1164.all ;
ENTITY simple ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END simple ;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
Moore FSM – Example 2: VHDL code (1)
ECE 545 – Introduction to VHDL 34
CASE y ISWHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;WHEN B =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;WHEN C =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;END CASE ;
Moore FSM – Example 2: VHDL code (2)
ECE 545 – Introduction to VHDL 35
Moore FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
ECE 545 – Introduction to VHDL 36
Moore FSM
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y_present
Next State: y_next
Output: z
clockresetn
process(w, y_present)
concurrent statements
process(clock, resetn)
ECE 545 – Introduction to VHDL 37
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y_present, y_next : State_type ;
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THENy_next <= A ;
ELSEy_next <= B ;
END IF ;WHEN B =>
IF w = '0' THENy_next <= A ;
ELSEy_next <= C ;
END IF ;
Alternative VHDL code (1)
ECE 545 – Introduction to VHDL 38
WHEN C =>IF w = '0' THEN
y_next <= A ;ELSE
y_next <= C ;END IF ;
END CASE ;END PROCESS ;
PROCESS (clock, resetn)BEGIN
IF resetn = '0' THENy_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THENy_present <= y_next ;
END IF ;END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;END Behavior ;
Alternative VHDL code (2)
ECE 545 – Introduction to VHDL 39
A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
resetn
w 1 = z 0 =
Mealy FSM – Example 2: State diagram
ECE 545 – Introduction to VHDL 40
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
Mealy FSM – Example 2: State table
ECE 545 – Introduction to VHDL 41
Mealy FSM
Next Statefunction
Outputfunction
Input: w
Present State: yNext State
Output: z
Present StateRegister
clockresetn
process(clock, reset)
concurrent statements
ECE 545 – Introduction to VHDL 42
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END Mealy ;
ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
Mealy FSM – Example 2: VHDL code (1)
ECE 545 – Introduction to VHDL 43
Mealy FSM – Example 2: VHDL code (2)
CASE y IS WHEN A => IF w = '0' THEN
y <= A ;ELSE
y <= B ;END IF ;
WHEN B =>IF w = '0' THEN
y <= A ;ELSE
y <= B ; END IF ;END CASE ;
ECE 545 – Introduction to VHDL 44
Mealy FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
ECE 545 – Introduction to VHDL 46
State Encoding Problem
• State Encoding Can Have a Big Influence on Optimality of the FSM Implementation• No methods other than checking all possible
encodings are known to produce optimal circuit• Feasible for small circuits only
• Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool
ECE 545 – Introduction to VHDL 47
Types of State Encodings (1)
• Binary (Sequential) – States Encoded as Consecutive Binary Numbers• Small number of used flip-flops• Potentially complex transition functions leading
to slow implementations
• One-Hot – Only One Bit Is Active• Number of used flip-flops as big as number of
states• Simple and fast transition functions• Preferable coding technique in FPGAs
ECE 545 – Introduction to VHDL 48
Types of State Encodings (2)
State Binary Code One-Hot CodeS0 000 10000000
S1 001 01000000
S2 010 00100000
S3 011 00010000
S4 100 00001000
S5 101 00000100
S6 110 00000010
S7 111 00000001
ECE 545 – Introduction to VHDL 49
(ENTITY declaration not shown)
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;ATTRIBUTE ENUM_ENCODING : STRING ;ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ;SIGNAL y_present, y_next : State_type ;
BEGIN
con’t ...
Figure 8.34
A user-defined attribute for manual state assignment
ECE 545 – Introduction to VHDL 50
Using constants for manual state assignment (1)
ARCHITECTURE Behavior OF simple IS SUBTYPE ABC_STATE is STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT A : ABC_STATE := "00" ;CONSTANT B : ABC_STATE := "01" ;CONSTANT C : ABC_STATE := "11" ;
SIGNAL y_present, y_next : ABC_STATE;BEGIN
PROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THEN y_next <= A ;ELSE y_next <= B ;END IF ;
… con’t