George Mason University ECE 545 – Introduction to VHDL Mixed Style RTL Modeling ECE 545 Lecture 6.

ECE 545 – Introduction to VHDL George Mason University

Mixed Style RTL Modeling

ECE 545Lecture 6

ECE 545 – Introduction to VHDL 2

Structural Modeling:

Generate Statements

Examples


w 8

w 11

s 1

w 0

s 0

w 3

w 4

w 7

w 12

w 15

s 3

s 2

f

Example 1


A 4-to-1 Multiplexer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE Dataflow OF mux4to1 ISBEGIN

WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ;

END Dataflow ;


Straightforward code for Example 1

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY Example1 IS

PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;

s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

f : OUT STD_LOGIC ) ;

END Example1 ;


Straightforward code for Example 1

ARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;


f : OUT STD_LOGIC ) ;END COMPONENT ;

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGIN

Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;




Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


Modified code for Example 1

ARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1

PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;


f : OUT STD_LOGIC ) ;

END COMPONENT ;


BEGIN

G1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (

w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;

Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


Example 2

w 0

En

y 0 w 1 y 1

y 2 y 3

y 8 y 9 y 10y 11

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

w 0

En

y 0 w 1 y 1

y 2 y 3

y 12y 13y 14y 15

w 0

En

y 0 w 1 y 1

y 2 y 3

w 3

En w


A 2-to-4 binary decoder


ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= "1000" WHEN "100", "0100" WHEN "101",

"0010" WHEN "110", "0001" WHEN "111",

"0000" WHEN OTHERS ;END Dataflow ;


VHDL code for Example 2 (1)

LIBRARY ieee ;


ENTITY dec4to16 IS

PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;

END dec4to16 ;


VHDL code for Example 2 (2)

ARCHITECTURE Structure OF dec4to16 IS

COMPONENT dec2to4PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;


BEGING1: FOR i IN 0 TO 3 GENERATE

Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );G2: IF i=3 GENERATE

Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ;END GENERATE ;

END GENERATE ;END Structure ;


Mixed Modeling:

Example


architecture ARCHITECTURE_NAME of ENTITY_NAME is

• Here you can declare signals, constants, functions, procedures…

• Component declarations• No variable declarations !!

beginConcurrent statements:

• Concurrent simple signal assignment • Conditional signal assignment • Selected signal assignment• Generate statement

• Component instantiation statement

• Process statement• inside process you can use only sequential

statements

end ARCHITECTURE_NAME;

Mixed Style Modeling

Concurrent Statements


Simple Processor

R 3 i n

Bus

Clock

R 0 i n R 0 o u t R 3 o u t

Control circuit Function

G

R 0 R3 A

AddSub

A i n G i n G o u t

Extern

Data

w

Done

B


N-bit register with enableLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

En : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESSBEGIN

IF (Clock'EVENT AND Clock = '1‘) THEN IF En = '1' THEN Q <= D ;

END IF;END IF ;

END PROCESS ;END Behavior ;


N-bit tristate buffer


ENTITY trin ISGENERIC ( N : INTEGER := 8 ) ;PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

En : IN STD_LOGIC ;Y : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)

) ;END trin ;

ARCHITECTURE Behavior OF trin ISBEGIN

Y <= (OTHERS => 'Z') WHEN En = '0' ELSE X ;END Behavior ;


Packages and component declarations


PACKAGE exec_components IS

COMPONENT regn -- registerGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; En : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;

COMPONENT trin -- tri-state buffersGENERIC ( N : INTEGER := 8 ) ;PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

En : IN STD_LOGIC ;Y : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;

END exec_components ;


Processor – Execution Unit (1)LIBRARY ieee ;


USE work.exec_components.all ;

USE ieee.std_logic_signed.all ;

ENTITY Proc_Exec IS

PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

Clock : IN STD_LOGIC ; Rin : IN STD_LOGIC_VECTOR(0 to 3);

Rout : IN STD_LOGIC_VECTOR(0 to 3);

Ain : IN STD_LOGIC ;

Gin : IN STD_LOGIC ;

Gout : IN STD_LOGIC ; AddSub : IN STD_LOGIC;

Extern : IN STD_LOGIC;

BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;

END Proc_Exec ;


Processor – Execution Unit (2)

ARCHITECTURE Mixed OF Proc_Exec IS

TYPE RegArray is ARRAY(0 to 3) of STD_LOGIC_VECTOR(7 downto 0);

SIGNAL R : RegArray;

SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ;

SIGNAL G : STD_LOGIC_VECTOR(7 DOWNTO 0) ;

SIGNAL Sum : STD_LOGIC_VECTOR(7 DOWNTO 0) ;



BEGIN

G1: FOR i IN 0 TO 3 GENERATE

Regs: regn PORT MAP (

D => BusWires,

En => Rin(i),

Clock => Clock,

Q => R(i)) ;

Trins: trin PORT MAP (

X => R(i),

En => Rout(i),

Y => BusWires) ;

END GENERATE ;



RegA: regn PORT MAP (

D => BusWires,

En => Ain,

Clock => Clock,

Q => A) ;

RegG: regn PORT MAP (

D => Sum,

En => Gin,

Clock => Clock,

Q => G) ;

triG: trin PORT MAP (

X => G,

En => Gout,

Y => BusWires) ;



ALU: WITH AddSub Select

Sum <= A + B WHEN ‘0’,

A – B WHEN OTHERS;

Tri_extern: trin PORT MAP (

X => Data,

En => Extern,

Y => BusWires) ;

END Mixed;


Processor – Control Unit (1)

LIBRARY ieee ;


USE work.control_components.all ;

ENTITY Proc_Control IS

PORT ( Func : IN STD_LOGIC_VECTOR(1 TO 6) ;

w : IN STD_LOGIC ;

Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ;

Rin : OUT STD_LOGIC_VECTOR(0 to 3);

Rout : OUT STD_LOGIC_VECTOR(0 to 3);

Ain : OUT STD_LOGIC ;

Gin : OUT STD_LOGIC ;

Gout : OUT STD_LOGIC ; AddSub : OUT STD_LOGIC;

Extern : OUT STD_LOGIC;

Done : OUT STD_LOGIC;

END Proc_Control ;


Processor Instructions


Processor

R 3 i n

Bus

Clock

R 0 i n R 0 o u t R 3 o u t

Control circuit Function

G

R 0 R3 A

AddSub

A i n G i n G o u t

Extern

Data

w

Done

B


Counter of instruction clock cycles

Reset

Up-counterClear

w 0 En

y 0

w 1

y 1 y 2 y 3

1

T 1 T 2 T 3

2-to-4 decoder

Q 1 Q 0 Clock

T 0

Count


The Function Register and Decoders

Clock

X 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

X 1 X 2 X 3

2-to-4 decoder

Function Register

Y 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

Y 1 Y 2 Y 3

2-to-4 decoder

I 0

En

y 0 y 1 y 2 y 3

1

I 1 I 2 I 3

2-to-4 decoder

FRin

f 1 f 0 Rx1 Rx0 Ry1 Ry0

w 0 w 1

Function


Control signals asserted in each operation and time step


Packages and component declarations


PACKAGE control_components IS

COMPONENT dec2to4PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;

COMPONENT upcountGENERIC ( N : INTEGER := 2 ) ;PORT ( Clock : IN STD_LOGIC ;

Reset : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;

END control_components ;


N-bit Up Counter (1)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY upcount ISGENERIC ( N : INTEGER := 2 ) ;PORT (Clock : IN STD_LOGIC ;

Reset : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO

0) ) ;END upcount ;


N-bit Up Counter (2)

ARCHITECTURE Behavior OF upcount ISBEGIN

upcount: PROCESS ( Clock )BEGIN

IF (Clock'EVENT AND Clock = '1') THENIF Reset = '1' THEN

Q <= (OTHERS => ‘0’);ELSE

Q <= Q + 1 ;END IF ;

END IF;END PROCESS;

END Behavior ;



ARCHITECTURE Mixed OF Proc_Control IS

SIGNAL Clear : STD_LOGIC;

SIGNAL Count: STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL T : STD_LOGIC_VECTOR(0 TO 3);

SIGNAL FRin : STD_LOGIC;

SIGNAL FuncReg: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;

SIGNAL I : STD_LOGIC_VECTOR(0 TO 3);

SIGNAL X : STD_LOGIC_VECTOR(0 TO 3);

SIGNAL Y : STD_LOGIC_VECTOR(0 TO 3);

SIGNAL High : STD_LOGIC;


Counter of instruction clock cycles

Reset

Up-counterClear

w 0 En

y 0

w 1

y 1 y 2 y 3

1

T 1 T 2 T 3

2-to-4 decoder

Q 1 Q 0 Clock

T 0

Count



BEGIN

counter: upcount PORT MAP (

Clock => Clock,

Reset => Clear,

Q => Count ) ;

Clear <= Reset OR Done OR (NOT w AND T(0)) ;

High <= '1' ;

decT: dec2to4 PORT MAP (

w => Count,

En => High,

y => T );


The Function Register and Decoders

Clock

X 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

X 1 X 2 X 3

2-to-4 decoder

Function Register

Y 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

Y 1 Y 2 Y 3

2-to-4 decoder

I 0

En

y 0 y 1 y 2 y 3

1

I 1 I 2 I 3

2-to-4 decoder

FRin

f 1 f 0 Rx1 Rx0 Ry1 Ry0

w 0 w 1

Function



functionreg: regn GENERIC MAP ( N => 6 )

PORT MAP (

D => Func,

En => FRin,

Clock => Clock,

Q => FuncReg ) ;

FRin <= w AND T(0);

decI: dec2to4 PORT MAP (

w =>FuncReg(5 DOWNTO 4),

En => High,

y => I ) ;



decX: dec2to4 PORT MAP (

w => FuncReg(3 DOWNTO 2),

En => High,

y => X ) ;

decY: dec2to4 PORT MAP (

w => FuncReg(1 DOWNTO 0),

En => High,

y => Y ) ;


Control signals asserted in each operation and time step



control_signals: PROCESS (T, I, X, Y)

BEGIN

Extern <= '0' ; Done <= '0' ; Ain <= '0' ; Gin <= '0' ;

Gout <= '0' ; AddSub <= '0' ; Rin <= "0000" ; Rout <= "0000" ;

CASE T IS

WHEN “1000” => null; -- no signals asserted in the time step T0

WHEN “0100” =>

CASE I IS

WHEN “1000" => -- Load

Extern <= '1' ; Rin <= X ; Done <= '1' ;

WHEN "0100" => -- Move

Rout <= Y ; Rin <= X ; Done <= '1' ;

WHEN OTHERS => -- Add, Sub

Rout <= X ; Ain <= '1' ;

END CASE ;

END PROCESS;


Processor – Control Unit (6)WHEN “0010” =>

CASE I IS

WHEN “0010" => -- Add

Rout <= Y ; Gin <= '1' ;

WHEN “0001" => -- Sub

Rout <= Y ; AddSub <= '1' ; Gin <= '1' ;

WHEN OTHERS => -- Load, Move

END CASE ;

WHEN OTHERS => -- define signals asserted in time step T3

CASE I IS

WHEN “1000" => -- Load

WHEN "0100" => -- Move

WHEN OTHERS => -- Add, Sub

Gout <= '1' ; Rin <= X ; Done <= '1' ;

END CASE ;

END CASE ;



END PROCESS;

END Mixed;


Using Arrays of Test Vectors

In Testbenches


Testbench (1)LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY sevenSegmentTB isEND sevenSegmentTB;

ARCHITECTURE testbench OF sevenSegmentTB IS

COMPONENTsevenSegment PORT ( bcdInputs: IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); );end COMPONENT;

CONSTANT PropDelay: time := 40 ns;CONSTANT SimLoopDelay: time := 10 ns;


Testbench (2)TYPE vector IS RECORD bcdStimulus: STD_LOGIC_VECTOR(3 downto 0); sevSegOut: STD_LOGIC_VECTOR(6 downto 0);END RECORD;

CONSTANT NumVectors: INTEGER:= 10;

TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector;

CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus => "0001", sevSegOut => "1001111"), (bcdStimulus => "0010", sevSegOut => "0010010"), (bcdStimulus => "0011", sevSegOut => "0000110"), (bcdStimulus => "0100", sevSegOut => "1001100"), (bcdStimulus => "0101", sevSegOut => "0100100"), (bcdStimulus => "0110", sevSegOut => "0100000"), (bcdStimulus => "0111", sevSegOut => "0001111"), (bcdStimulus => "1000", sevSegOut => "0000000"), (bcdStimulus => "1001", sevSegOut => "0000100"));


Testbench (3)

SIGNAL StimInputs: STD_LOGIC_VECTOR(3 downto 0);

SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 downto 0);

BEGIN

u1: sevenSegment PORT MAP (

bcdInputs => StimInputs,

seven_seg_outputs => CaptureOutputs);


Testbench (4)

LoopStim: PROCESS

BEGIN

FOR i in 0 TO NumVectors-1 LOOP

StimInputs <= vectorTable(i).bcdStimulus;

WAIT FOR PropDelay;

ASSERT CaptureOutputs == vectorTable(i).sevSegOut

REPORT “Incorrect Output”

SEVERITY error;

WAIT FOR SimLoopDelay;

END LOOP;


Testbench (5)

WAIT;

END PROCESS;

END testbench;

George Mason University ECE 545 – Introduction to VHDL Mixed Style RTL Modeling ECE 545 Lecture 6.

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Transcript of George Mason University ECE 545 – Introduction to VHDL Mixed Style RTL Modeling ECE 545 Lecture 6.