The Role of Wafer Foundries in Next Generation Packaging
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Page 1 Page 1 The Role of Wafer Foundries in Next Generation Packaging David McCann, VP Packaging R+D May 28, 2013 1
Transcript of The Role of Wafer Foundries in Next Generation Packaging
Page 1 Page 1
The Role of Wafer Foundries in
Next Generation Packaging
David McCann, VP Packaging R+D
May 28, 2013
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Solutions are Increasingly Silicon-Based
RF moves from QFN to wlCSP
Driven by footprint and cost
Memory moves much closer to the logic in 2.5D and 3D
Driven by power reduction and increased bandwidth
3D memory stacks replace 2D DIMMs
Driven by bandwidth, density, footprint
Interconnect density increases
Driven by progressively denser Si nodes
Driven by SoC disaggregation
Courtesy: Micron Technology
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Disaggregation
SOC scaling is not delivering full entitlement of cost/area improvement
Enables SoC “fission” into best cost-performance fit node for each chip
Enables high bandwidth and increased performance per joule
Enables re-use without re-design…lower risk and lower cost
But requires more complex packaging solutions
Cache GPU
Core
Analog Cache
Core Cache GPU
Core
Core
Cache Analog
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Reliability in New Packaging Technologies
Si Qualification
What Applications?
What Packages? What BEoL Stacks?
Test Chips
What Needs to be Solved?
Solution Paths
What Customers?
How to Ensure Supply Chain is Ready?
Application Specific Test Chips
Customer Specific Supply Chains
Market Analysis
Leading Adaptors
Understand Drivers
Understand Barriers with Customer Architecture
and Product Groups
Understand system solution requirements (BW,
power, height, cost)
Understand impact to silicon physical
environment, interconnect, structure
Customer and supply chain participation in test
chip design
Supply Chain Design Rules, PDK, DfT Strategy,
Yield Verification, Cost Roadmap, Lots of Silicon
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New Supply Chain Model: Collaboration
Supply chain
collaboration is
required to
develop and
deliver solutions to
customers,
developed around
the customer’s
preferred supply
chain.
Consortia
Tool Suppliers
Material Suppliers
Assembly
Test
Log
ic F
oun
dry
Mem
ory
Foundry
Custo
mer
Collaboration by the experts in each field
Development of solutions in one location with partners, aligned to customers preferred supply chain
Early development to support BEoL definition
Aligned Design Rules, PDK, Systems
Partners fan-out technologies to their factories for smooth production ramp
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Supply Chain Inter-Dependencies
3D
Impact of Packaging on
TSVs and Transistors
Impact of Thinning
Design Rules for
Supply Chain Yield
Definition of Yield Loss
Ownership
TSV + M3
√
√
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√
2.5D
Interposer Supply
Design Rules for
Supply Chain Yield
Metallurgy and Process
Decisions
Definition of Yield Loss
Ownership
√
√
√
√
CuPillar
Impact of Packaging on
BEoL stack
Stress of CuP on ELK
Design Rules that Work
for Packaging
Test Chips for Supply
Chain
√
√
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Drive Adoption by Driving Yield which Drives Cost
FMEA Detect Method
Detect At Test
Capability Design Macros
Drive Yield
Defect Pareto
Gather Data
Correlation
Systematic Feedback
Process Control
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Technology Development Center at Fab 8
Ground Break April, 2013
TDC Fab 8.1
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Collaborative Development at TDC for Solutions
Key Elements of Technology
Leading edge (14nm, 10nm, 7nm)
2.5D, 3D
BSI, Bump, Assembly Development
Eco-system Partners
Supply chain initiatives
Solutions before the industry
Made in America
Strategic
Engagement
Partners
Technology
Customers
OSAT Partners Tool Partners Memory Partners Key Customers
Aligned Consortia Projects
DfT Partners
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Trademark Attribution
GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the
United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be
trademarks of their respective owners.
©2009 GLOBALFOUNDRIES Inc. All rights reserved.
Thank You
