1

THREE DIMENSIONAL INTEGRATION AND ON-WAFER PACKAGING FOR

HETEROGENEOUS WAFER-SCALE CIRCUIT ARCHITECTURES

Linda Katehi, Barry Perlman1, William Chappell2, Saeed Mohammadi2 and Michael Steer3

University of Illinois, Urbana-Champaign, IL, Katehi@uiuc.edu

1CERDEC, US Army RDECOM, Ft. Monmouth, NJ, Barry.Perlman@us.army.mil

2 Purdue University, West Lafayette, IN 3 North Caroline State University, NC

I. INTRODUCTION

Advanced Network Centric Warfare (NCW) systems are critical to the successful implementation of the Army’s Future Force. These systems require a new generation of circuits with deployable, agile, versatile, lethal, survivable and sustainable capabilities. Both manned and unmanned vehicles are required to established dominance in the battlefield via use of multi-band, agile, multifunctional mobile systems that can control, command and communicate. However, at very high frequencies and with wide analog and digital bandwidths, conventional chip-substrate integration techniques and filtering technologies (e.g. solder bumps and wire-bonds) such as the ones mentioned above, limit system capability and compromise efficiency.

The super-heterodyne radio architecture, most prevalent in present systems, necessitates multiple passive off-chip components including IF filters adapted to the channel filtering requirements to support different standards. A newer direct conversion (including low IF) architecture has evolved that lends itself to a single- or few-chip mixed signal implementation although performance is compromised primarily because of the loss and finite Q of on-chip passives leading to low RF efficiency, increased power consumption and high phase noise. In this circuit architecture, digital noise is coupled into the RF circuitry further limiting detectability. For future NCW systems, the above attributes must be obtained with performance superior to that available commercially and delivered with volumes

Figure 1: Multi-wafer Three-Dimensional Integration

6 mm 6 mm

2-4 mm

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relatively small in comparison to that in the commercial world.

These performance requirements put a put a premium on heterogeneous integration whereby various optimized chip and component technologies can be combined to obtain superior overall performance. For example, combining the high power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating with 1.2 V supply, provides circuits with the density of flash memory and with

the agility afforded by the evolving technologies of ferroelectrics and MEMS actuators.

Our experience of the past ten years has shown that the requirement of good performance, low cost and high operating frequencies cannot be achieved either by monolithic or hybrid integration. It is the synergistic development of technologies and RF architectures that will enable us to achieve superior performance while constraining costs and achieving multi-functionality and agility. Three-dimensional integration and on wafer packaging of

RF Filter

LOLNARF

in

fsignal

f1

f2

AMP/Filter

To IF Circuitry

IM3

RF Filter

LOLNARF

in

fsignal

f1

f2

Conventional ReceiverWideband RF Filter

Direct Conversion Receiver

(Selective RF filter)

RF Filter

LOLNARF

in

fsignal

f1

f2

AMP/Filter

To IF Circuitry

IM3

RF Filter

LOLNARF

in

fsignal

f1

f2

Conventional ReceiverWideband RF Filter

Direct Conversion Receiver

(Selective RF filter)

Figure 3: Comparison of Conventional and Direct Conversion Receiver Architectures

3

heterogeneous wafers (see Figure 1) is the future in high frequency circuit design and circuit architecture. It leads to the development of novel RF front-end transceiver architectures that consume very little power, are highly compact, very low-cost and high-performance and are appropriate for future NCW systems.

To achieve high performance the passives are required to exhibit high Q, small size and low cost. It is known that on chip passives suffer from low Q while off-chip components are not easy to integrate with the active chips. A new concept introduced recently, the use of a high-frequency interposer layer, allows for the combination of high-performance, low cost and the ability to integrate in three dimensions. The use of an interposer layer (see Figure 2) that can tightly integrate active chips with passives in a multi-wafer environment also provides multi-functionality due to the ability to integrate with high and intermediate permittivity dielectrics (relative permittivity of 600 and 25 respectively). The use of these dielectrics on the interposer leads low parasitics, high density and low cost. The interposer can incorporate heterogeneous materials for more functionality. As an example, ferroelectric components using BST (Barium Strontium Titanate) and designs that exploit their tunable characteristics have been developed. The BST has been integrated into the interposer using a heterogeneous integration method.

The potential of using high density, low-loss interconnects and integrated high quality passives, in order to complement the advances in high speed device technology, has been shown to provide maximum benefit for integrated microwave systems. Both design cycle times and system performance have been advanced through the use of high-resistivity silicon in a unique Si-based Self-Aligned Wafer Level Integration Technology (SAWLIT), that was developed as part of this project. In this technology the CMOS or SiGe ICs are integrated within the Si interposer using low-loss interconnects with a definition better than 1 micron. This integration approach allows the removal of passives from the expensive

IC chip and their integration on the interposer for lower cost and better performance. Additionally, the use of a multi-layer package integrated with the interposer allows for the high density integration of high quality components such as cavity based filter with unloaded Q’s > 1500s. In this paper we will present the implementation of the interposer concept on a transceiver architecture that easily lends itself to a three-dimensional heterogeneous integration along with the passives that make this integration possible [7-9]. The three-dimensional circuit architecture will be demonstrated on a 10GHz CMOS receiver. II. TRANCEIVER ARCHITECTURE Herein, we present a futuristic three-dimensional transceiver architecture which utilizes a high-Q integrated filter and relies on vertical integration for the development of a compact three-dimensional wireless front end. This system has an antenna structure intimately integrated with the highly selective multi-frequency substrate and incorporates a novel mixed signal digital IF circuitry including integration of the ICs with the mixed signal circuitry through a uniquely designed Si interposer layer. The design of this transceiver can be accomplished effectively through a holistic mixed circuit approach that accurately takes into account high frequency effects including dispersion, radiation and electromagnetic coupling. This transceiver has the potential to outperform many existing systems such as JTRS and SATCOM. Further it demonstrates the potential of many novel circuit technologies to provide the functionality and density needed in systems such as Cognitive Radio, the next generation sensors, etc. This three-dimensional architecture promises compatibility with multiple standards for multifunction, high-density of integration for very small volume and lower fabrication cost, and low power consumption. Some of the important aspects of this architecture are RF compatible packaging, low-frequency IF, all-Si based circuit realization for up to Ka-band frequency, relaxed

4

specifications on linearity, dynamic range, image frequency rejection, phase noise and digital IF down-conversion, filtering, demodulation and signal processing [1]-[5].

Good transceiver performance critically depends on the ability to integrate on wafer heterogeneous materials, technologies and high-Q embedded passives with the active chips. Cost reduction is a major reason for the use of the interposer concept. The ability to integrate a very high Q filter with the LNA, VCO and antenna allows for a direct conversion as shown in the schematic of Figure 3.

Direct conversion receivers are very sensitive to LO leakage, DC offset and baseband noise sources, which cause severe performance

degradation compared to super-heterodyne architectures. The ability to integrate a high-Q filter allows for the use of a low IF frequency selected close to the baseband, above the 1/f noise corner frequency, but still low enough for direct A/D conversion. With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage-controlled oscillator (VCO), the image frequency rejection requirement and the dynamic range of the A/D converter can be substantially relaxed (Figure 3). The value of the IF that can be utilized in this architecture critically depends on the characteristics of the receiver including the quality factor of the RF filters. Traditional analog signal processing such as I and Q separation (In-phase and Quadrature-phase), channel-select filtering, down-conversion to baseband frequency

and moving target indication (MTI) can be moved into the digital domain, thereby avoiding the sensitivity of this process to various analog circuit impairments and providing adaptation to the multiplicity of standards and multifunctional capability.

The receiver architecture of Figure 3 requires a number of novel technologies which have been developed and are described below. These technologies, when applied to transceiver designs can lead to state of the art system architectures with unparalleled performance. A detailed description of the development effort for each of these novel technologies is described in the following sections.

III. HETEROGENEOUS INTEGRATION AND THE CONCEPT OF INTERPOSER

To achieve high performance in the transceiver architecture of Figure 3, the passives are required to exhibit high Q, small size and low cost. It is known that on chip passives suffer from low Q while off-chip components are occupying a large volume and are not easy to integrate with the active chips. A new concept introduced recently, the use of a high-frequency interposer layer, see Figures 1 and 2, allows for the combination of high-performance, low cost and the ability to integrate in three dimensions. The use of an interposer layer, as shown in Figure 2, that can tightly integrate active chips with passives in a multi-wafer environment also provides multi-

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

24GHz fully integrated receiver24GHz fully integrated receiver

5 to 25 micron interconnect width was easily achieved5 to 25 micron interconnect width was easily achieved

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

24GHz fully integrated receiver24GHz fully integrated receiver

5 to 25 micron interconnect width was easily achieved5 to 25 micron interconnect width was easily achieved

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

CM OS Chip H igh resistivity Si

M etal Interconnect

25μm

24GHz fully integrated receiver24GHz fully integrated receiver

5 to 25 micron interconnect width was easily achieved5 to 25 micron interconnect width was easily achieved

Figure 4: Si-based Self-Aligned Wafer Level Integration Technology (SAWLIT) for a Si Interposer

5

functionality due to the ability to integrate with high and intermediate permittivity dielectrics (relative permittivity of 600 and 25 respectively). The use of these dielectrics on the interposer leads to low parasitics, high density and low cost in addition to providing more functionality. As an example, ferroelectric components using BST (Barium Strontium Titanate) and designs that exploit their tunable characteristics have been developed. The BST has been integrated into the interposer using a heterogeneous integration method [10].

The integration of heterogeneous layers may compromise reliability as operating power increases due to thermal mismatch issues. In this case distributed cooling will be required to provide better control of the thermal environment. The use of passive or active cooling via use of three-dimensional cooling channels is compatible with the three-dimensional technology presented herein. Integrated cooling is a growing research area in high-frequency circuit design.

Through DARPA’s TEAM project led by Purdue University and North Carolina State University we have demonstrated the use of interposer integration and packaging techniques using high

frequency CMOS and SiGe circuits. The potential of using high density, low-loss interconnects and integrated high quality passives, in order to complement the advances in high speed device technology, has been shown to provide maximum benefit for integrated microwave systems. Both design cycle times and system performance have been advanced through the use of high-resistivity silicon in a unique Si-based Self-Aligned Wafer Level Integration Technology (SAWLIT) [6], see Figure 4, that was developed as part of this project. In this technology the CMOS or SiGe ICs are integrated within the Si interposer using low-loss interconnects with a definition better than a few microns. This integration approach allows the removal of passives from the expensive IC chip and their integration on the interposer for lower cost and better performance. Additionally, the use of a multi-layer package integrated with the interposer allows for the high density integration of high quality components such as cavity based filter with unloaded Q’s > 1500s.

High-valued components such as decoupling capacitors or choke inductors, high-Q components with quality factors greater than 100, or tunable components which require precise fabrication

CMOS Chip High res. Si

Metal Interconnect

10μm

25μm

CMOS Chip High res. Si

Metal Interconnect

10μm

25μm

CMOS Chip High res. Si

Metal Interconnect

10μm

25μm

CMOS Chip High res. Si

Metal Interconnect

10μm

25μm

Figure 5: Interposer integration for a wireless transceiver system. A CMOS chip is integrated inside a high resistivity Si. Interconnects as narrow as 25μm are used

6

conditions not compatible with CMOS fabrication lines cannot be integrated into a single piece of silicon despite the advances of high frequency transistors.

Through the use of a silicon interposer as a heterogeneous integration platform, each of these components can be added to a mixed-signal System on a Chip (SOC) design providing improved performance in fully integrated systems. Additionally, the use of high quality passives in an interposer, which are in close proximity to the circuit through high density interconnects, allows for circuit rework without altering the expensive mask set needed for the CMOS/SiGe components, greatly reducing circuit design cycle and cost.

By developing novel three-dimensional integration schemes, we have demonstrated, for a first time, a fully integrated Si receiver at 10GHz using a Si-based interposer. Using SAWLIT [6,11], the 10GHz receiver designed in 180nm CMOS technology has been integrated with an embedded Si-based matching network, BST bypass capacitors and an integrated high-Q filter. The overall receiver system performance has been characterized, showing substantial improvement over other fully integrated systems operating at the same frequency and with similar bandwidth. Due to its inherent self-aligned characteristics, this technology allows for batch integration of multiple chips and is key to developing low cost and high performance fully integrated RF circuits and systems.

The high-Q filter for the receiver of Figure 2 is a three-dimensional structure that has been designed to provide high Q along with small size and the ability to become fully integrated with the interposer. In this arrangement, using the interposer as an integration platform, cavities within a Si wafer or a multilayer polymer materials have been fabricated to provide a multipole filter performance. For the polymer material, a three-dimensional laser fabrication method has been utilized to create evanescent filters with unprecedented quality factors Q greater than 1,000.

The multi-wafer architecture discussed above, shown in Figures 1 and 2, comprises three main structural and functional layers: the Interposer Layer (1) the HBT/CMOS Device Layer (2) and the EBG/Filtering and Antenna Layer (3). These layers are shown on the schematic of Figure 2. In this architecture the various ICs are bonded using SAWLIT to the multi-layered interposer layer which incorporates high-performance integrated passives and RF routing and is then integrated with a high-Q filter using Si or Polymer. Alternatively it can be integrated with an Electromagnetic Band-Gap (EBG) Layer and Antenna Layer for high-Q filtering and high-efficiency radiation.

An IBM 0.18μm CMOS technology has been used for the implementation of the low-power RF. In the following we will present the implementation of the interposer concept on a transceiver architecture that easily lends itself to a three-dimensional heterogeneous integration along with the passives that make this integration possible. The three-dimensional circuit architecture is demonstrated on a 10GHz CMOS receiver. IV. 10 GHz CMOS INTEGRATED RECEIVER

Using the concepts developed above, a 10GHz CMOS receiver was designed and fabricated. The CMOS chip was fabricated on 7RF and was designed to operate at 10 GHz. The amplifier was tuned using a matching network printed on the interposer as shown on Figure 5. Using high Q passives on the low loss high resistivity Si Interposer, the input matching of the amplifier was improved from 13dB at 11 GHz to -30dB at the design frequency (10.2GHz). This improved matching increased the convergence gain of the receiver from 21 dB to 23 dB as shown on Figure 6. In this initial design the conversion gain at the center frequency was about 7 dB (about 2 dB higher than anticipated due to additional losses introduced by the coupling to the filter. At present design changes are implemented which are expected to reduce the Noise Figure to almost 5.5 dB at 10 GHz.

7

V. CONCLUSIONS

This paper has presented circuit architectures which allow for the three-dimensional integration and on-wafer packaging through the concept of a Si interposer. The presented three-dimensional integration schemes have allowed for the design and fabrication of fully integrated receiver which performs at 10 GHz. High-Q passives and three-dimensional interconnects allow for the design oh high-cost, high density circuits that also exhibit very high performance.

VI. ACKNOWLEDGEMENTS

The work was performed under the DARPA TEAM Project

VII. REFRENCES

1. A. Bateman and D.M. Haines, “Direct

conversion transceiver design for compact low-cost portable mobile radio terminals,” in Proc. IEEE Veh. Technol. Conf., May 1989, pp. 57-62

2. A.A. Abidi, “Direct conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.

3. J.F. Wilson et al., “A single chip VHF and UHF receiver for radio paging,” IEEE J. Solid-State Circuits, vol. 26, pp. 1944-1950, Dec. 1991.

4. R.M. Henderson, K.J. Herrick, T.M. Weller, S.V. Robertson, R.T. Kihm and L.P.B. Katehi, “Three Dimensional High Frequency Distribution Networks. Part II: Packaging and Integration,” IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 10, October 2000.

5. Katherine Herrick, Linda P.B. Katehi and Robert T. Kihm, “Interconnects for a Multi-layer Three-Dimensional Silicon Architecture”, Microwave Journal, May 2001, Vol. 44, No. 5.

6. H. Sharifi, T. Choi and S. Mohammadi, Self-Aligned Wafer-Level Integration Technology with High Density Interconnects and Embedded Passives for a 10GHz CMOS Receiver Front-End, in press,

7. A. Margomenos and L.P.B. Katehi, “High Frequency Parasitic Effects for On-Wafer Packaging of RF MEMS Switches”, IEEE International Microwave Symposium, Philadelphia PA, June 2003.

8. A. Margomenos and L.P.B. Katehi, “DC to 40 GHz On-Wafer Package for RF MEMS Switches”, IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 91-94, October 2002.

9. A. Margomenos, L.P.B. Katehi, “Ultra-Wideband Three-Dimensional Transitions for On-Wafer Packages”, European Microwave Conference, September 2004.

10. Michael Steer , individual communication 11. Saeed Mohammadi et al. SAWLIT, US

Patent Application, Pending

Figure 6: Convergence Gain of the 10GHz RFIC Before and after Adding the Embedded

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College of Engineering

Linda Katehi, Saeed Mohammadi and William Chappell* (Speaker)Linda Katehi, Saeed Mohammadi and William Chappell* (Speaker)Purdue University, West LafayettePurdue University, West LafayetteMichael Steer, Angus Michael Steer, Angus KingonKingonNorth Carolina State University, Rayleigh, North CarolinaNorth Carolina State University, Rayleigh, North CarolinaBarry PerlmanBarry PerlmanCERDEC, US Army RDECOM, Fort Monmouth, N. J.CERDEC, US Army RDECOM, Fort Monmouth, N. J.

Heterogeneous On-Wafer and Multilayer Integration

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OutlineOutlineHeterogeneous Integration of IC’s

Silicon in Silicon RFIC Wafer Integration

High-Q Wafer Scale Passive ComponentsHighHigh--Q Filter Integration Q Filter Integration –– RF CubeRF Cube

Multilayer High Quality Filters (Q’s > 1,000)

Tunable Filters ( 1.5:1 Tuning ratios with Q’s > 800)

Demonstration of Wafer Scale Integrated RFICDemonstration of Wafer Scale Integrated RFIC

10 10 GHz and 24 GHz Receiver Examplesand 24 GHz Receiver Examples

Integrated OnIntegrated On--Wafer Antennas and Future Large Array SystemsWafer Antennas and Future Large Array Systems

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Problem StatementProblem StatementProblem: The push towards integration onto IC (mixed signal or RFIC integration) is often incompatible with military needs.

Large Non-recurring Engineering Costs

Design at Central Locations

Non-optimal Material Choices (Sub-optimal Performance)

Solution: Massively Integrated Hybrid Systems

Flexibility of Hybrid with Large Scale Integration of SOC

Integration at the Wafer Scale Using Silicon Interposer

Wafer-in-Wafer and 3-D Heterogeneous Integration

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Typical EW System

Pre-Selector

&Antenna Interface

RF IN(2-18 GHz)

LOGenerator

BPF

RF IN(0-2 GHz)

Microwave Converter Chip

Wide-band IF Converter chip

FPGADigital

Processing

BPF

BPF

SystemClock

Reference

14.4 GHz

4.8 GHz

Courtesy:Richard ElderFrank StroiliBAE Systems

= Differential Signal Path

= Target insertions

DecouplingPassives We fit in:

Tunable FiltersDifferential Signal PathsEmbedded Passives

PROBLEMSADDRESSED

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Heterogeneous Integration Concept

Utilize Wafer Scale Silicon in Silicon Integration and Multilayer Packaging to Create Miniature Self-

Contained RF and Microwave Systems

QQ’’s of 10s of 10

QQ’’s of 100s of 100

QQ’’s of 1000s of 1000

BSTBST

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Fully Integrated Chip/SiFully Integrated Chip/Si--InterposerInterposer

Integrated HighIntegrated High--Q CavityQ CavityQ>1000 Q>1000

RFIC: RFIC: QQ’’s of 10s of 10

Antenna Antenna

EffEff> 80%> 80%

Distributed Elements Integrated and Packaged Distributed Elements Integrated and Packaged in Interposer: in Interposer: QQ’’s over 100 s over 100

Lumped Integrated and Packaged Lumped Integrated and Packaged in Interposer: in Interposer: QQ’’s of 50 s of 50

High Valued Decoupling Components

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Heterogeneous Integration at theHeterogeneous Integration at theChip Level Chip Level

CMOS Chip High resistivity Si

Metal Interconnect

25μm

CMOS Chip High resistivity Si

Metal Interconnect

25μm

24GHz fully integrated receiver24GHz fully integrated receiver

CMOS transimpedance Amplifier (13GHz BW, 52dBΩ gain)

High resistivity Si

InP PIN Photodiode

Before MetallizationBefore Metallization

After MetallizationAfter Metallization

15Gb/sec CMOS/15Gb/sec CMOS/InPInPOptoelectronic ReceiverOptoelectronic Receiver

5 to 25 micron interconnect width was easily achieved5 to 25 micron interconnect width was easily achieved(SAWLIT) Wafer Level Integration(SAWLIT) Wafer Level Integration

IC Interposer Post metallized for I/O’s

View of Assembled IC in Interposer

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SAWLIT FabricationSAWLIT FabricationSelf Aligned Wafer Level Integration TechnologySelf Aligned Wafer Level Integration Technology

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CMOS IC

matching network

DC

IF OUTPUT

RF INPUTDC

PDMS

Metal over transition

GND

RF

GND

Via

Carrier substrate RFIC

Metal over transition

GND

RF

GND

Via

Carrier substrate RFIC

SAWLIT for 10GHz ReceiverSAWLIT for 10GHz Receiver

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Advantages Specific to Advantages Specific to Military SystemsMilitary Systems

Lower power dissipation :Lower power dissipation :• Seamless integration between IC’s with no line drivers or parasitic pad reactance

Utilize different technologies / optimize cost and performance :Utilize different technologies / optimize cost and performance :• Example: use 0.13um SiGe/CMOS for RF receiver, GaAs for RF PA, RF MEMS for

transmit receive switch, High-ρ interposer for passives and 0.25um CMOS for IF amplifier / control circuits.

Implement passives on carrier substrate (interposer):Implement passives on carrier substrate (interposer):• Smaller size active chips on a Low Loss Substrate

Mask programmable:Mask programmable:• Same actives for RF but different routing and different passives to create different

circuits.

Heterogeneous integration (Massively Integrated Hybrid Circuits)Heterogeneous integration (Massively Integrated Hybrid Circuits)• Designs at Numerous Locations with Optimal Materials as Needed.

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Off Chip Wafer Level ComponentsOff Chip Wafer Level ComponentsHighHigh--Q 3D InductorsQ 3D Inductors

0

25

50

75

100

125

150

0 5 10 15 20 25 30 35 40Frequency [GHz]

Qua

lity

Fact

or

0

1

2

3

4

5

6

7

8

Indu

ctan

ce [n

H]

Q (1 Turn)

Q (2 Turn)

L (1 Turn)

L (2 Turn)

3D inductors based on Au/Cr stressed metal combination3D inductors based on Au/Cr stressed metal combination

SubstrateWidth

Gap

Diameter

14.225.431

18.512.916High-Resistivity

(>10 kΩ·cm)

4.1128.231

4.9813.816Low-Resistivity(10 -20 Ω·cm)

QmaxL (nH)# of turnSubstrate

FOM=(InductanceFOM=(Inductance--nHnH) x (Quality factor)) x (Quality factor)

OneOne--Turn Turn MicromachinedMicromachined Inductors: FOM=150Inductors: FOM=150

ToroidalToroidal: FOM=361: FOM=361

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Off Chip Wafer Level ComponentsOff Chip Wafer Level Components3D Transformers3D Transformers

Input Output

0.0

0.2

0.4

0.6

0.8

1.0

0 5 10 15 20 25 30 35 40

Frequency [GHz]

Pout

/Pin

1:1 Transformer 1:4 Transformer

0

0.2

0.4

0.6

0.8

1

0 5 10 15 20 25 30 35 40

Frequency [GHz]

Pout

/Pin

1:1 xformer1:2 xformer2:2 xformer2:3 xformer3:3 xformer3:4 xformer

Unlike spiral transformers3D transformers are extremely wideband(3GHz<BW<~35GHz)

*U.S. Patent Filed

SubstrateWidth

Diameter

Gap

Primary Turns

3:4 3D Transformers (95% power efficiency)3:4 3D Transformers (95% power efficiency)

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BST ComponentsBST Components

IDC MIMBST BST VaractorsVaractors

Embedded Passive, Agility using BST varactors

Explore New Architecture

Tunable Filters; Matching Networks; Tunable Filters; Matching Networks; VCOsVCOs

Embedded HighEmbedded High--Valued PassivesValued Passives

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5 10 15 20 250 30

20

40

60

80

0

100

Freq (GHz)

Q fa

ctor

Q factor of 28 @ 26 GHz

Tunable Lumped Element Tunable Lumped Element BandpassBandpass FiltersFilters

3 rd order 3 rd order bandpass bandpass filter @ filter @ 1.7 GHz, 1.7 GHz, 20% 3dB BW20% 3dB BW

CuCr

BSTAluminaAluminaInterposer

CuCr

BST

CuCr

BST

0 to 200 V

0.6 1.1 1.6 2.1 2.60.1 3.0

-40

-30

-20

-10

-50

0

Freq (GHz)

S21

(dB

)

0 to 200 V

50% varactor 50% varactor tuning leads tuning leads to 25% tuning to 25% tuning of the filterof the filter

0.2

0.25

0.3

0.35

0.4

0

100

200

300

400

500

600

-40 -30 -20 -10 0 10 20 30 40

Cap

acita

nce

(pF)

Q factor

Bias (V)

@ 1 MHz

4.5 dB

(metal liftoff)

(REDUCE TO 2.5 dB in 12 months) VERY LINEAR

C = 0.4 pF

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Layer by Layer Packages to Create Three-Dimensional Integrated Components

Q> 1,000 - Enables low loss filtering

Protection of Circuitry Without Degradation

Eliminate Deficiencies of On-Chip Antennas

Efficiency > 70%, Wideband, Directional

Filter/ Antenna Integration : Tight integration of high quality components (Q>1000) with an IBM7RF RFIC in a silicon carrier

wafer and highly efficient antennas

QQ’’s of 100 on s of 100 on interposerinterposerQQ’’s of 1000 in s of 1000 in

multilayer filtermultilayer filter((preselectpreselect filtering)filtering)

High Valued CapHigh Valued Cap’’s (BST)s (BST)

Heterogeneous RF Cube

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Cavity Based Integrated Filters

Horizontal Integrated Cavities

200 Layers of Polymer:

Insertion loss = 0.262 dB

BW = 1.83% - Q~ 3,000

FOM= Q/Area = 6000/λ2

Frequency, GHz

31 32 33

S21

, dB

-50

-40

-30

-20

-10

Single Embedded Cavity Resonator:

200 Layers of Polymer: Demonstrated Unloaded Q’s of 3,000

Figure of Merit= Q/Area = 6,000/λ2

Page 17

DARPA

NC STATE UNIVERSITY

Reduced Size Vertically Integrated Cavities

I.L. = 0.262 dB, BW = 1.83 %

Q~ 3,000, FOM = 12,346/λ2

-60

-50

-40

-30

-20

-10

0

17 18 19 20 21 22 23

Frequnecy (GHz)

Inse

rtion

Los

s (d

B)

-40

-30

-20

-10

0

10

20

Ret

urn

Loss

(dB

)

Meas.

Simu.

Evanescent Filter: Reduction to ¼ of Cavity

I.L. = 0.35 dB, BW = 1.8 %

Q’s ~ 1200, FOM = 5,164/λ2

HighHigh--Q Reduced Size FiltersQ Reduced Size Filters

Cap Post

Page 18

DARPA

NC STATE UNIVERSITY

Tunable HighTunable High--Q FiltersQ Filters

Unloaded Q’s ~ 900Insertion Loss < 1.3 dB for a 1.75 % Filter

Preselect Tuning is Now Possible Without Degradation in Performance

Capacitive Gap

5 micron 40 micron

IL = 1.3 dB

Piezo-actuated Tunable diaphragms

Measured Tuned Evanescent Cavity 2-Pole Filter

Page 19

DARPA

NC STATE UNIVERSITY

-30

-20

-10

0

10

20

9 10 11 12Frequency (GHz)

Ret

urn

Loss

(dB

).

-50

-40

-30

-20

-10

0

Inse

rtion

Los

s (d

B) .

Measured FilterSimulated Filter

Silicon Interposer Integrated Silicon Interposer Integrated Evanescent FiltersEvanescent Filters

10.3 GHz Filter Results: Measurement and Simulation in Good Agreement.

Consistent and

Repeatable Results

Allows for Integration

with RFIC

Silicon Interposer>150 Layers of Laser Cured Polymer

Page 20

DARPA

NC STATE UNIVERSITY

-30

-20

-10

0

10

20

9 10 11 12Frequency (GHz)

Ret

urn

Loss

(dB

).

-50

-40

-30

-20

-10

0

Inse

rtion

Los

s (d

B) .

Measured FilterSimulated Filter

Silicon Interposer Integrated Silicon Interposer Integrated Evanescent FiltersEvanescent Filters

10.3 GHz Filter Results: Meas and Sim in Good Agreement.

IL = -.64 dB for ~ 4 % filter.

Center Fo = 0.8 % off of design frequency

-40

-30

-20

-10

0

9 9.5 10 10.5 11 11.5 12Frequency (GHz)

S-Pa

ram

eter

s (d

B)

Measured filterBroadband loss

Δf = 0.8%

IL = .64 dB

Consistent and

Repeatable Results

Allows for Integration

with RFIC

Page 21

DARPA

NC STATE UNIVERSITY

High Efficiency Antenna forHigh Efficiency Antenna forSilicon Interposer IntegrationSilicon Interposer Integration

4.5 mm

Planar Slot Antenna

Readily Integrated on Interposer with RFIC/Filter Combination

Resonant Frequency - <1% off

Interposer > 85% Efficiency

Improved Bandwidth (3 x BWon-chip)

-20

-15

-10

-5

0

Ret

urn

Loss

(dB

)

SimulatedMeasuredMeasured

fo=15GHz

020406080

100

0 0.1 0.2 0.3 0.4 0.5Length in Wavelengths

Effic

ienc

y (%

)

On Chip

On Interposer

Wheeler/Chu Fundamental Limitation

Page 22

DARPA

NC STATE UNIVERSITY

System DemonstrationsSystem Demonstrations10 GHz Front10 GHz Front--EndEnd (IBM 7RF CMOS)(IBM 7RF CMOS)

VCO ( 950 VCO ( 950 μμm x 720 m x 720 μμm) m) FrontFront--end ( LNA + Mixer + VCO ) end ( LNA + Mixer + VCO ) ( 1250 ( 1250 μμm x 1200 m x 1200 μμm )m )

BIAS

VDD

CONTROL

LO OUTPUT

RF INPUT

CONTROL

IF OUTPUT

BIAS

VDD

CONTROL

LOOUTPUT

RF INPUT

CONTROL

IF OUTPUT

VCO

Mixer

LNA

Page 23

DARPA

NC STATE UNIVERSITY

Highly Stable 10GHz CMOS LC OscillatorHighly Stable 10GHz CMOS LC Oscillator

Figure of Merit for VCO (FOM)Figure of Merit for VCO (FOM)

VCO Schematic.

Vcont

Bias<Buffer>

M3 M4

M1 M2

M5

Var1

M6 M7

M8 M9

Var2

R1 R2L1

L2

C1

Output spectrum of the VCO @10.3GHz.

)1

log(10)log(20)(mWP

fffPNFOM DC

offset

ooffset +−=

[ 13 ]

[ 10 ][ 4 ]

[ 11][ 5 ]

[ 6 ][ 12 ]

Thi s wor k wi t h buf f e r

[ 7 ]

Thi s wor k w/ o buf f e r

[ 6 ]

[ 9 ]

[ 8 ]

- 19 5

- 19 0

- 18 5

- 18 0

- 17 5

- 17 0

- 16 5

9 10 11 12 13

Frequency ( GHz)

Our Results

FO

M(d

Bc/

Hz)

L1 L2

OUTN OUTP

Vcc_core Vcc_buf

Vctrl IbiasLtail

Ctail Cb

NP-pairvaractor

buff

er

buff

er

Current mirror

Phase Noise of the the VCO at carrier frequency of 10.3GHz.

Page 24

DARPA

NC STATE UNIVERSITY

Low Power CMOS LC OscillatorLow Power CMOS LC Oscillator

VCO Schematic.

Vcont

Bias<Buffer>

M3 M4

M1 M2

M5

Var1

M6 M7

M8 M9

Var2

R1 R2L1

L2

C1

[Ref.11]

[Ref.10]

[Ref .12]

[Ref .2]

[Ref.7][Ref.8]

[Ref.9]

[Ref .13]

[Ref.14]

-190

-185

-180

-175

-170

0.1 1.0 10.0 100.0

Power Consumption [mW]Fi

gure

of M

erit

[dB

c/Hz

]

This Work

IBM 7RF CMOSIBM 7RF CMOS

1.8GHz

Page 25

DARPA

NC STATE UNIVERSITY

Layout and Photograph of 10GHz Layout and Photograph of 10GHz PackagePackage

Input matching is improved by embedded matching circuits

Page 26

DARPA

NC STATE UNIVERSITY

Measurement Results of 10GHz Measurement Results of 10GHz PackagePackage

Noise Figure of IC and Package

-30

-20

-10

0

10

20

30

9 9.5 10 10.5 11 11.5

Frequency (GHz)

Gai

n (d

B)

Before Packaging

After Packaging w/o filter

After Packaging w/ filter

4

8

12

16

20

24

28

32

36

40

44

9.2 9.4 9.6 9.8 10 10.2 10.4 10.6 10.8 11 11.2Frequency (GHz)

NF(

dB)

Before Pacakging

After Packaging w/o Filter

After Packaging w/ Filter

Conversion Gains of IC and Package

Linearity of Packaged System

Page 27

DARPA

NC STATE UNIVERSITY

ConclusionConclusion

Both Component and System Level Advantages were Demonstrated

Components:

High-Q inductors/ transformers (Q’s greater than 1000)

Filters (Q’s greater than 1,000) and tunable

High-valued components

System Demonstration

10 GHz Receiver Integrated at Wafer Scale