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The Increasing Role of Dielectric LayersThe Increasing Role of Dielectric Layersin Flipin Flip--Chip and Wafer Level PackagingChip and Wafer Level Packaging
Keynote Address
R.L. HubbardIMAPS Device Packaging Conference 2007
Bob Hubbard
Lambda Technologies, Inc.
What; more layers?!What; more layers?!
� The “planarization” of packaging
� The drivers to add layers
� Planar package constructions
� An update on polymer dielectric layers
R.L. HubbardIMAPS Device Packaging Conference 2007
� Material characteristics and reliability
� Changing demands on flip-chip
� Alternatives and directions
The Planarization of TransistorsThe Planarization of Transistors
� From vertically assembled and wired transistors to monolithic layers of semiconductors
R.L. HubbardIMAPS Device Packaging Conference 2007
from Jack Kilby’s notebook
The Planarization of Integrated CircuitsThe Planarization of Integrated Circuits
� Cu wiring with SiO2 dielectric layers (1982!)
“fat”
metal
R.L. HubbardIMAPS Device Packaging Conference 2007
� Cu wiring with low-k dielectric layers (2000)
� Now 4 layers for DRAM, 9 layers for logic
device
W plug
The Planarization of PackagingThe Planarization of Packaging
R.L. HubbardIMAPS Device Packaging Conference 2007
� Planarization: adding dielectric and metal layers for interconnects
The Planarization of SystemsThe Planarization of Systems
� The component list is getting longer:
� passives
� sensors
� power
� connectors
� optics
� MEMS
Integration will come
with new organic and
composite materials
R.L. HubbardIMAPS Device Packaging Conference 2007
� MEMS
� thermal
� video
� RF
composite materials
( this is a much slower process
outside the silicon infrastructure)
From Passivation to Wafer Level PackagingFrom Passivation to Wafer Level Packaging
� Stress buffer / passivation layers
� Silicon nitride for moisture and halogen protection (passivation)
� Polymer layer for stress relief from encapsulation/molding
� One more re-distribution layer (RDL)
� Transition from WB to bumps
� Transition from periphery to array
R.L. HubbardIMAPS Device Packaging Conference 2007
� Transition from periphery to array
� Two – eight interconnection layers (WLP)
� Moderate (50-200) I/O devices
� Fan-out beyond IC borders
A Universal Package?A Universal Package?
� The old “chips first” re-visited
� Assemble an array of tested
dice
� Protect the die back and
sides with encapsulant
� Add layers of interconnect to
R.L. HubbardIMAPS Device Packaging Conference 2007
� Add layers of interconnect to
die faces
� Fan-out pads for high density
chips
� Bump and dicecourtesy Infinieon Technologies
The Drivers of ChangeThe Drivers of Change
� Cost
� Wafer processes are bulk
� Fewer total process steps
� Additional costly substrate not necessary
� Test at wafer or known-good-die approaches add cost
� Thickness
� Thin
R.L. HubbardIMAPS Device Packaging Conference 2007
� Thin is in! (Motorola RAZR, Motorola Q, Samsung A900)
� Stacked dice were already forcing wafer thinning to 50 um
� Reliability
� Fewer material interfaces
� Fewer separate parts to protect
� Fewer adhesive joints
The Death of WireThe Death of Wire--Bonding?Bonding?
� No.
� The majority of devices will continue to
be wire-bonded for some time
� All existing technologies fight
DIP
QFP
SOIC
BGA
Bare
CSP
Other
R.L. HubbardIMAPS Device Packaging Conference 2007
� All existing technologies fight
replacement
� Can DDR3 and DDR4 be wire-bonded?
� Two studies; two answers
time
mark
et
Dielectric Material PropertiesDielectric Material Properties
R.L. HubbardIMAPS Device Packaging Conference 2007
Changing Material Property Needs Changing Material Property Needs -- WLPWLP
� Stress buffer layer needs before 2000
� High temperature stability for reflow
� High elongation for die stresses
� Low outgassing
� Adhesion to die
� Current multilayer RDL and WLP
� High temperature stability for multiple processes and reflow
R.L. HubbardIMAPS Device Packaging Conference 2007
� High temperature stability for multiple processes and reflow
� High elongation for die and multi-layer stresses, and shock testing
� Chemical resistance to develop solvents and etchants
� Water based development for the environment
� Lower thermal budget for curing (die yield)
� Low temperature curing for sensitive devices (<200°C)
� Fast curing for mulitple layer throughput (>50 WPH)
� Adhesion to previous layer
Dielectric Material Properties Dielectric Material Properties -- PIPI
� Polyimides for stress buffer layers
� High elongation, low modulus, planarizing, “soft” coating
� High temperature stability, chemically resistant, αααα particle barrier
� Photo-sensitive, solvent based development, linear
� High temperature, long cure (350°C, 4 hrs), 2% moisture retention
O
R.L. HubbardIMAPS Device Packaging Conference 2007
C
N
O
CO
O H
ArH
C
N
O
C
O
Ar
Material Properties Material Properties -- PBOPBO
� Polybenzoxazoles for re-distribution
� High elongation, low modulus, planarizing, “soft” coating
� High temperature stability, chemically resistant, αααα particle barrier
� Photo-sensitive, water based development, cross-linked
� High temperature, long cure (380°C, 4 hrs), 2% moisture retention
OH
R.L. HubbardIMAPS Device Packaging Conference 2007
C
O
OH
H
N
C
O
N
Material Properties Material Properties -- BCBBCB
� Benzocylobutene (Cyclotene) for re-distribution
� Low elongation, low dielectric constant, planarizing, “hard” coating
� High temperature stability, oxygen sensitive, αααα particle barrier
� Photo-sensitive, solvent based
� Moderate temperature, long cure (250°C, 5 hrs)
R.L. HubbardIMAPS Device Packaging Conference 2007
Si
O Si
CH3
CH3
CH3
CH3
Si O
Si
CH3
CH3
CH3
CH3
Si
O
Si
CH3
CH3
CH3
CH3
Material Properties Material Properties -- EpoxiesEpoxies
� Epoxy “hybrids” for wafer level packaging
� Low temperature, shorter cure (175-190°C, 3 hrs)
� Low elongation, high modulus, “hard” coating
� Lower temperature stability, chemically resistant
� Photo-sensitive, solvent based, resin or film
� Cross-linked
� Thermal processing affects mechanical properties
R.L. HubbardIMAPS Device Packaging Conference 2007
� Thermal processing affects mechanical properties
Dielectric Material ComparisonsDielectric Material Comparisons
� Choices depend on number of layers, low-k dielectric layers, type of device,
device properties, type of application, throughput, size of wafers, technology
node (45 nm?), environment, etc.
Tg Cure time* Cure
Temp
Elong. Process Stability
PI 300 5 hr 350 80% Solvent >400°C
R.L. HubbardIMAPS Device Packaging Conference 2007
PBO 300 5 hr 380 100% Water >400°C
BCB 280 8 hr 250 5% Solvent >300°C
Epoxy 200 3 hr 190 4% Solvent ?
* customer variation can be significant
Is Your Dielectric Layer Really Cured?Is Your Dielectric Layer Really Cured?
� Polymer dielectrics must be highly cured to have good adhesion
� Many dielectric layers now in use are not highly cured
� Historical use of 180°C polyimide coatings
� Epoxy based microvia boards with un-cured resin may crack internally
after reflow processes
� Shifting modulus, CTE, elongation affects layer stresses
R.L. HubbardIMAPS Device Packaging Conference 2007
� Shifting modulus, CTE, elongation affects layer stresses
� “Standard” processes are not aways full cure
� DSC or FTIR will show extent of cure until about 90%
� TMA or DMA will provide Tg, which is more cure sensitive
� How cured is cured enough?
Epoxy Adhesive FilmsEpoxy Adhesive Films
� Flip-chip under-fill, CSP/BGA under-fill
� Process drivers Reliability drivers
� Fast flow ▪ low warpage
� Fast cure ▪ thermal stability
� Fine pitch ▪ adhesion
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� Self filleting ▪ low stress
� Flux compatible ▪ large die
� Long pot-life ▪ high I/O
� Two new drivers
� Higher reflow temperatures (no-lead)
� Fragile low-k dielectric layer(s)
Material Supplier DirectionsMaterial Supplier Directions
� Wafer Dielectrics
� Faster and lower temperature cure of PI and PBO
� New chemistries and formulations
� Epoxy “hybrids” and photo-resists
� Lower temperature cure
Flip-chip underfills
R.L. HubbardIMAPS Device Packaging Conference 2007
� Flip-chip underfills
� Lower shrinkage, lower stress
� Compatibility with low-k dielectrics
� Lower Tg + lower modulus but low CTE
� New families of materials
� Packaging consortia all have chemical partners
� Focus is on mechanical properties (CTE, E’, Tg, etc.)
The Dielectric Curing ProcessThe Dielectric Curing Process
R.L. HubbardIMAPS Device Packaging Conference 2007
(for cross-linked polymers)
“Liquid State” and “Solid State” Curing“Liquid State” and “Solid State” Curing
� Low temperature cure step:
� majority of shrinkage occurs in liquid state
� size of agglomerates determined by cross-link density
� “network” extent of cure constrained by cross-link density
� gellation: change from liquid to solid state curing
� entrapment of uncured molecules in “network”
� High temperature cure step
R.L. HubbardIMAPS Device Packaging Conference 2007
� High temperature cure step
� continued growth of agglomerates
� completion of cross-linking if possible
� some cross-linking physically blocked
� curing of entraped molecules
� thermal and chemical resistance enhanced
� yield strength and adhesion enhanced
� continued shrinkage during cooling
Total shrinkage (not simply highest temperature)Total shrinkage (not simply highest temperature)
1. Liquid state shrinkage (>50%)
2. Solid state shrinkage (difference between gel and RT)
R.L. HubbardIMAPS Device Packaging Conference 2007
shri
nkag
e
shri
nkag
e
Note: The Tg of both materials is the same.
Closer Look at CrossCloser Look at Cross--linkinglinking
� PBO dielectric layers for WLP
� Epoxy dielectric layers and adhesives for flip-chip
� Example of epoxy cross-linking:
DGEBA (resin)
O O O ONH2NH2
MDA (hardener)
R.L. HubbardIMAPS Device Packaging Conference 2007
O
OH
O
DGEBAMDA
cross-linked
network
Change the Curing Process?Change the Curing Process?
� Lower the cure temperature, for example
� Change the balance of low and high temperature steps
DGEBAMDA
larger network
(mesh size)
R.L. HubbardIMAPS Device Packaging Conference 2007
� Benefits:
� increases elongation, toughness, resistance to crack propagation
� decreases shrinkage, tension and compression modulus, brittleness
Curing with MicrowavesCuring with Microwaves
� Obviously faster curing: 5 hours to 15 minutes
� Lower temperatures for PI and PBO:
VFMconvection
1 2 3 4 5 hrs
400
300
200
100Cu
re T
emp
(°C
)
VFMconvection
1 2 3 4 5 hrs
400
300
200
100Cu
re T
emp
(°C
)
Various Polyimides
1.1
Various PBOs
1.1
R.L. HubbardIMAPS Device Packaging Conference 2007
0.7
0.8
0.9
1
125 150 175 200 225
VFM Cure Temp
Tg
Ra
tio
1
2
3
4
5
6
7
8
9NPS PS- PS+
0.7
0.8
0.9
1
1.1
125 150 175 200 225 250
VFM Cure TempT
g R
ati
o
1
2
3
4
5
6
350°C – 5 hrs 175°C – 1 hr
Modified Properties with MicrowavesModified Properties with Microwaves
� Tg must remain the same (adhesion, thermal stability)
� Lower modulus with low temperature cure
Flexural test of FP4651
40.000
60.000
80.000
100.000
120.000
Str
es
s, M
Pa
Flexural test of FP4651
40.000
60.000
80.000
100.000
120.000
Str
es
s, M
Pa
R.L. HubbardIMAPS Device Packaging Conference 2007
� Raise or lower the CTE with cure profile
0.000
20.000
40.000
0.000000 0.002000 0.004000 0.006000 0.008000 0.010000 0.012000
Strain, mm/mm
0.000
20.000
40.000
0.000000 0.002000 0.004000 0.006000 0.008000 0.010000 0.012000
Strain, mm/mm
60
40
20
0
20 40 60 80 100 120 140
Temperature (C)
Dim
ensi
on
al
Ch
ang
e (u
m)
60
40
20
0
20 40 60 80 100 120 140
Temperature (C)
Dim
ensi
on
al
Ch
ang
e (u
m) Profile MW Conv MW
CTE (ppm/C) 44 68 109
SummarySummary
� As planarization continues
� dielectric materials and processes become more critical
� Material properties affect package reliability
� Material requirements continue to change
R.L. HubbardIMAPS Device Packaging Conference 2007
� Material requirements continue to change
� new chemistries and new processes
Change Grinds On!Change Grinds On!
R.L. HubbardIMAPS Device Packaging Conference 2007