1

PERFORMANCE ANALYSIS OF SPACE VECTOR BASED PULSE WIDTH MODULATION

Being A Thesis Presented In Partial Fulfilment Of The Requirements For The Award Of Master In Engineering Degree (M.Engr) In Electronic Engineering

Author: .........................................................,

Anoliefo Edward C.

(PG/M.Engr/07/43499)

Supervisor: ................................................

Prof: O.U. Oparaku

External Examiner: ..................................................

Head of Department ........................................................

Ven. Prof.T. Madueme

2

CERTIFICATION PAGE

3

TITLE PAGE

PERFORMANCE ANALYSIS OF SPACE VECTOR BASED PULSE WIDTH MODULATION

4

DECLARATION

I, Edward Anoliefo, do hereby declare that the this work has not been published earlier nor has it been presented elsewhere as a thesis in partial fulfilment of the requirement for the award of any degree. People whose works and ideas were profusely used were acknowledged.

..................................

Anoliefo Edward

5

DEDICATION

THIS WORK IS DEDICATED TO PROF O.U. OPARAKU MY MENTOR AND SUPERVISOR. PROF M.U. AGU

6

ACKNOWLEDGEMENT

Towards the completion of this work, I am eternally grateful to God who gave me the strength, wisdom and insight that sustained me throughout the period of the work.

I am also grateful to my amiable supervisor, Prof. O.U Oparaku. The doyin of power electronics at the University of Nigeria Nsukka, Prof. M.U Agu was always at my beck and call. I remain grateful to Omeje Onyebuchi for his immense contribution. My friend, Uche Ejiofor was ever present. I could not have finished without him.

The management, staff and colleagues at National Centre for energy research and development, UNN have their share of my gratitude. I thank in a special way, the acting director, Dr. Unachukwu G. The funds he released for research into inverter helped a lot.

7

ABSTRACT

The need for efficient DC-AC has led to ground breaking modulation theories and techniques. The ultimate effort of this research work is to analyse the performance of Space Vector Based Pulse Width Modulation (PWM) techniques and see whether it is possible to use it as a basis for producing a chip which can effectively replace the use of SG3524.

SG3524 is chip used for generating the switching patern for building single phase inverter. The operation of SG3524 is based on two level carrier based pulse width modulation. Space vector modulation belongs to the family of pulse width modulation. Some experts see it as a form of regular sampled pulse width modulation.

In this work, having noted the limitation of sg 3524 based pulse width modulation such as dv/dt stress. Low utilizatio9n of DC voltage, high THD, the mathematical foundation of space vector modulation is explored, subsequently, MATLAB/SIMULINK model of space vector based modulation is developed and studied.

Theoretical analysis finally led tothe development of a set timing constraints that formed the basis for the development of a practical switching pattern that could be implemented on microcontrollers. Different patterns were studied using ISIS professional (a simulation software that is capable of implementing programmes installed in its virtual microcontroller.

Results from the SIMULINK model and ISIS professional, therefore formed the basis for laboratory prototype which involved programming a chip, PIC16/f84A which would adequately supply the switching pattern for building inverters.

8

LISTS OF FIGURES

1. Amplitude-Time graph showing rectangular pulses.

2. A graph describing various duty cycles

3. Figures 3 Circuit diagram of a typical buck-boost converter.

4. Figure 4: A simple inverter circuit.

5. Figure 5: Essential elements of sinusoidal modulation.

6. Figure 6: Pin configuration of 555 timer.

7. Figure 7: the circuit diagram of 555 timer by Tony Van Roon

8. Figure 8: 555 timer configured as DC-DC converter

9. Figure 9: Block diagram of sg 3524.

10. Figure 10: Pin configuration

11. Figure 11: Sg 3524 based inverter circuit.

12. Figure 12: Basic circuit of inverter

13. Figure 13: Block diagram of 16F84.

14. Figure 14: Pin configuration of 16f84

15. Figure 15: Schematic of PIC16F84 based space modulation

16. Figure 16: Three phase wye and delta connection

17. Figure 17: a three phase inverter circuit.

9

18. Figure 18: A basic Space Vector diagram.

19. Figure 19: schematic of three phase inverter.

20. Figure 20: 3 level NPC inverter topology.

21. Figure 21: Space vector diagram of a three level inverter

22. Figure 22: Space diagram illustrating basic parameters for space vector analysis

23. Figure 23: Pulse generation with Method 1

24. Figure 24: Pulse generation with method 11

25. Figure 25: Pulse generation with Basic Bus Clamping SVM

26. Figure 26: Pulse generation with Boundary Sampling SVM

27. Fig 27: Some of the possible switching sequences for the first sector.

28. Fig 28: Generated space diagram for two level inverter.

29. Fig 29: generated space vector for three level inverter

30. Figure 30: MATLAB model of three level inverter

31. Figure 31: Block diagram for Simulink modelling oof three level inverter

32. Figure 32: 3-level space vector modulation waveform for a modulation index 0.8.

33. Figure 33: ISI circuit for two level inverter

34. Figure 34: ISIS result of Conventional SVM

35. Figure 35: ISIS result of Boundary sampling SVM

10

36. Figure 36: ISIS result of Asymmetric Clamping SVM

37. Figure 37: ISIS result of Basic Bus Clamped SVM.

11

LISTS OF TABLES

Table 1: possible switching states of a two level inverter.

Table 2: generated results of alpha and beta planes of two level inverter.

Table 3: Generated g-plot of two level inverter

Table4: Truth table for the 3-level 27-voltage states

Table 5: 3-level output voltage and per unitized Vα and Vβ values

Table 6: g-plot of three level inverter.

12

LIST OF SYMBOLS

® .............................................................................................. Angular Frequency

ᶿ ............................................................................................... Phase Angle

α ............................................................................................... Alpha Equivalent

β ............................................................................................... Beta Equivalent

ϒ ............................................................................................ Gamma Equivalent

Vref ......................................................................................... Reference Voltage

Vα ............................................................................................ Alpha Voltage

Vβ ............................................................................................. Beta voltage

ta ........................................................................................ Switching time for Vα

tb ....................................................................................... Switching time for Vβ

t0 ...................................................................................... Switching time for V0

13

LIST OF MAJOR ABBREVIATIONS

pwm = Pulse Width Modulation

SPWM = Sinusoidal Pulse Width Modulation

SVPWM = Space Vector Pulse Width Modulation

14

TABLE OF CONTENTS

Approval page ...................................................................................i

Certification page .............................................................................ii

Title page ..........................................................................................iii

Dedication .........................................................................................v

Acknowledgment ...............................................................................vi

Abstract .............................................................................................vii

List of Figures ...................................................................................viii

List of Tables ......................................................................................x

List of Symbols ...................................................................................xi

List of Abbreviations ..........................................................................xii

Table of contents ..............................................................................xiii

CHAPTER ONE ..................................................................................1

INTRODUCTION..................................................................................2

1.0 Background of study ................................................................1

1.1 Statement of the problem .........................................................2

1.2 Purpose of study .......................................................................3

15

1.3 Significance of study..................................................................4

1.4 Scope of study ......................................................................5

1.5 Study methodology ...............................................................6

CHAPTER TWO

PULSE WIDTH MODULATION

2.0 Concept of pulse width modulation.............................................7

2.1 Pwm for power control................................................................9

2.2 Pwm as a tool for power conversion........................................12

2.3 Pulse width modulation and d.c –a.c conversion .....................17

2.4 Pulse width modulators ...........................................................22

2.4.1 555 Timer as a pulse width modulator ...................................23

2.4.2 SG 3524 as a pulse width modulator ......................................30

2.4.3 Microcontrollers as pulse width modulators..............................34

CHAPTER THREE

SPACE VECTOR MODULATION

3.0 From sinusoidal pwm to space vector pwm..............................39

3.1 Three phase alternating current................................................40

16

3.2 Introduction to space vector analysis.......................................44

CHAPTER FOUR

INVERTER TOPOLOGIES

4.1 Basic conceptual framework for space vector modulation analysis..............52

4.2 Switching sequences....................................................................58

4.2.1: Conventional Scheme ..............................................................59

4.2.2: Basic Bus Clamping SVM ..........................................................62

4.2.3: Boundary Sampling SVM ............................................................63

4.2.4: Asymmetric Zero Clamping SVM ................................................64

CHAPTER FIVE

SIMULATION/RESULTS

5.1 Simulation details of two level inverter ............................................66

5.2 Simulation details of three level inverter .........................................70

5.3 Simulink block of 3-level neutral point clamped inverter at modulation

indices of 0.8. ..........................................................................................76

5.4 Simulation using Proteus Lite

17

CHAPTER SIX

OBSERVATIONS AND CONCLUSION

6.1 Observations ...................................................................................86

6.2 Conclusion/recommendations .........................................................88

Appendix 1 .............................................................................................90

Appendix 2 ..........................................................................................104

Appendix 3. ..........................................................................................105

18

CHAPTER ONE

INTRODUCTION

1. 0 BACKGROUND OF PROBLEM

There is increasing conflict between our future energy demands and the need

to limit emissions of greenhouse gases that contribute to global warming.

This has led to growing awareness of the dire environmental

consequences of the more conventional sources of energy. Engineers and

scientists believe the solution is to supplement our traditional sources of

energy with clean, renewable energy sources such as wind, waves and solar

energy. [1]

Of these, solar power offers the most promise. Solar power promises to

address energy shortages without contributing to global warming. Engineers

are continually improving solar panels and efficiency figures are now above

20% under laboratory conditions. The overall efficiency figure, however,

hinges not only on the efficiency of the solar panels but also on how well the

DC

19

output is converted to a practical AC supply by the inverter circuit. The right

components and clever design can significantly improve efficiency.

1.1 STATEMENT OF THE PROBLEM

At present, Nigerian engineers and technicians use SG 3524 chip for the

purposes of designing Voltage Source Inverters. SG3524 is monolithic

integrated circuit which contains all the control circuitry for a regulating

power supply, inverter or switching regulator. Included in a 16 pin dual-in-

line package is voltage reference,error amplifier,oscillator, pulsewidth

modulator, pulse steering flip-flop, dual alternating output switches and

current limiting and shutdown circuitry. This device can be used for

switching regulators of either polarity, transformer coupled DC to DC

converters, transformerless voltage doublers and polarity converter as well

as other power applications.[3]

SG 3524 has some obvious shortcomings.

20

1. The chip produces square waves. This means that the best

kind of inverter that can be built out it is modified square

wave inverter.

2. The practical implication of this is that such an inverter

would not be suitable for every kind of application.

3. Again, the efficiency is lowered as a result of high total

harmonic distortion.

1.2 PURPOSE OF STUDY

The ultimate effort of this research work is to analyse the performance

of Space Vector Based Pulse Width Modulation techniques and see

whether it is possible to use it as a basis for producing a chip which

can effectively replace the use of SG 3524. Such a chip should

incorporate the essential functionalities of of SG 3524. Besides, the

chip should have added advantages that come with the introduction of

space vector pulse with modulation.

21

One of such expected inputs is the implementation of multi level

inverters by artisans. Artisans who may not understand the complexity of

space vector based pulsewidth modulation theory would be able to use the

chip after it has been programmed. This would represent a major gain for

Nigeria which is in dire need of alternative energy sources.

1.3 SIGNIFICANCE OF STUDY

The major significance of this is that it proposes a space vector pulse

width modulation that is based on DC capacitor voltage balance strategy.

This reduces the capacitor voltage drift(dv/dt) phenomenon of voltage

source inverters. Moreso, it allows for easy digital implementation using

power semi conductor devices.

In addition, this work also proposes a space vector modulation technique

that utilizes a switching frequency higher than the fundamental. This

minimizes the undue harmonic distortion encountered with much lower

frequency than the

22

fundamental value. Experience shows that the techniques used send the

harmonics to the higher frequency ranges. These high frequencies are then

filtered out.

The results obtained from this study will be useful to the following:

ü Home appliances where fairly sinusoidal waveforms are

needed fom a solar based power supply.

ü Prospective researches on Space Vector pulse width Modulation

ü Power semi conductor designers using digital signal with

space vector pulse width modulation control strategy in

reducing the excessive total harmonic distortion associated

with sinusoidal pulse with modulation.

1.4 SCOPE OF STUDY

The purpose of this study shall be achieved by going into some details

the theory of space vector modulation. In order to understand the

principles of space vector modulation, we located it within the family

of pulse width modulation. Finally, by exploring in some details, the

theoretical work already done on the issue of space vector modulation, we

sought to

23

understand the basic principles underlying the switching of the various

transistors, their duty cycle and sequence.

1.5 REPORT ORGANIZATION To achieve the purpose as outlined above, we devoted the second chapter

to an indept exploration of the concept of pulse width modulation. Its use in

power control was also discussed. This led toan appreciation of Pulse width

modulation as a tool for power conversion. Its applicability and application

in DC-AC was subsequently discussed. There was then an attempt to link

the theoretical work to the practical reality on ground by discussing

pulse width modulators such as 555 timers and SG 3524

Space vector modulation is in the domain three phase electricity. Hence,

analysis of voltage current relationship in three phase system formed a

necessary prelude to understanding the basics of space vector analysis.

Detailed analysis of space vector in the third chapter led smoothly to

the development of practical switching sequences in chapter four. The

fifth chapter dwelt on the simulation details of two and three level inverter

topologies. The final chapter discussed the results and arrived at some

conclusions.

24

CHAPTER TWO

PULSE WIDTH MODULATION

2.0 CONCEPT OF PULSE WIDTH MODULATION

The advent of Metal Oxide Semiconductor Field Effect

Transistors,(MOSFET) Insulated Gate Bipolar transistor (IGBT) and

associated devices brought about immense innovations in the area

of digital controls. The greatest beneficiary of these innovations is

power electronics. In the field of power electronics, Power

electronic converters are a family of electrical circuits which

convert electrical energy from one level of voltage/current/frequency

to another using semiconductor-based electronic switches.[4] The

process of switching the electronic devices in such a way as to

manipulate the on and off times of a continuous pulse is called

pulse width modulation.

The off and on times are technically related by concept of duty

cycle. The duty cycle of a pulse is defined as the ratio between the

25

pulse duration (τ) and the period (T) of a rectangular waveform as

showen in figure 2.1 below.

Figure 1: Amplitude-Time graph showing rectangular pulses.

Mathematically, the relationship of pulse duration and period can be

described thus: where τ is the duration that the function is active

high (normally when the signal is greater than zero); Τ is the period of the

function. Pulse width modulation is a means of using microcontrollers and

transistors to manipulate pulse duration for purposes of electrical

conversion or control.

In the past decades, semiconductor technology has followed”Moore’s law,”

doubling the number of transistors in digital integrated circuits (IC’s)

approximately every two years [5]. As a result, IC’s have become cheaper,

faster, more sophisticated, and more power efficient. This, in turn, has

26

triggered a revolution, making digital processing IC’s, such as

microprocessors, microcontrollers, digital signal processors (DSP’s), graphics

processors, and memory chips, ubiquitous in home and professional

applications. No wonder pulse width modulation has a lot of applications. It

can be used to convey either information over a communication channel or

control the amount of power sent to a load. PWM is employed in variety of

applications, ranging from measurements and communications to power

control and conversion, mainly because of its low power, noise-free and low

cost characteristics.

2.1 PWM FOR POWER CONTROL

Analog voltages and currents can be used to control things directly, like the

volume of a car radio. In a simple analog radio, a knob is connected to a

variable resistor. As the knob is turned, the resistance goes up or down. As

that happens, the current flowing through the resistor increases or decreases.

This changes the amount of current driving the speakers, thus increasing or

decreasing the volume. An analog circuit is one, like the radio, whose output

is linearly proportional to its input.

27

As intuitive and simple as analog control may seem, it is not always

economically attractive or otherwise practical. For one thing, analog circuits

tend to drift over time and can, therefore, be very difficult to tune. Precision

analog circuits, which solve that problem, can be very large, heavy , and

expensive. Analog circuits can also get very hot; the power dissipated is

proportional to the voltage across the active elements multiplied by the

current through them. Analog circuitry can also be sensitive to noise. Because

of its infinite resolution, any perturbation or noise on an analog signal

necessarily changes the current value.

Pulse Width Modulation is a way of digitally encoding analog signal levels.

Through the use of microcontrollers, the duty cycle of a square wave is

modulated to encode a specific analog signal level. The PWM signal is still

digital because, at any given instant of time, the full DC supply is either fully

on

28

or fully off. The voltage or current source is supplied to the analog load by

means of a repeating series of on and off pulses. The on-time is the time

during which the DC supply is applied to the load, and the off-time is the

period during which that supply is switched off. Given a sufficient bandwidth,

any analog value can be encoded with PWM.[6]

Figure 2.2 shows three different PWM signals. Figure 2.2a shows a PWM

output at a 10% duty cycle. That is, the signal is on for 10% of the period and

off the other 90%. Figures 2b and 2c show PWM outputs at 50% and 90%

duty cycles, respectively. These three PWM outputs encode three different

analog signal values, at 10%, 50%, and 90% of the full strength. If, for

example, the supply is 9V and the duty cycle is 10%, a 0.9V analog signal

results.

29

Figure 2.2: A graph describing various duty cycles.

2.2 PWM AS A TOOL FOR POWER CONVERSION

To appreciate pulse width modulation as a technique for power

conversion, let us consider a typical buck boost converter using the

principle of Pulse With modulation.

2 a

2 b

2 c

30

Figure 2.3 is a typical example.

Figure 1.3 Circuit diagram of a typical buck-boost converter.

The two operating states of a buck-boost converter are the off and the on

stages. When the switch is turned-on, the input voltage source supplies

current to the inductor and the capacitor supplies current to the resistor

(output load). When the switch is opened (provided energy is stored into the

inductor), the inductor supplies current to the load via the diode D.

The basic principle of the buck-boost converter is fairly simple:

31

• While in the On-state, the input voltage source is directly connected to

the inductor (L). This results in accumulating energy in L. In this stage,

the capacitor supplies energy to the output load;

• While in the Off-state, the inductor is connected to the output load and

capacitor, so energy is transferred from L to C and R.

• If the current through the inductor L never falls to zero during a

commutation cycle, the converter is said to operate in continuous mode.

From t=0 to D.T, the converter is in On-State, so the switch S is closed.

The rate of change in the inductor current (IL) is therefore given by:

...................................................................................2.1

• At the end of the On-state, the increase of IL is therefore:

.......................2.2

32

• D is the duty cycle. It represents the fraction of the commutation period

T during which the switch is On. Therefore D ranges between 0 (S is

never on) and 1 (S is always on).

• During the Off-state, the switch S is open, so the inductor current flows

through the load. If we assume zero voltage drop in the diode (we

consider an ideal diode), and a capacitor large enough for its voltage to

remain constant, the evolution of IL is:

.................................................................................... 2.3

...................................................2.4

• Therefore, the variation of IL during the Off-period is:

• As we consider that the converter operates in steady-state conditions,

the amount of energy stored in each of its components has to be the

same at

33

• the beginning and at the end of a commutation cycle. As the energy in

an inductor is given by:

................................................................................. 2.5

• It is obvious that the value of IL at the end of the Off state must be the

same as the value of IL at the beginning of the On-state, i.e the sum of

the variations of IL during the on and the off states must be zero:

..........................................................................................................2.6

• Substituting and by their expressions yields:

................2.7

This can be written as:

........................................................................... 2.8

• From the above expression it can be seen that the polarity of the output

voltage is always negative (as the duty cycle goes from 0 to 1), and that

34

its absolute value increases with D, theoretically, up to minus infinity

as D approaches 1. This means that increase and/or decrease in voltage

is simply a function of pulse width modulation.

2.3 PULSE WIDTH MODULATION AND D.C –A.C CONVERSION

In the pulse width modulation described above, one level of DC voltage is

converted to another, it is interesting to note that besides being used in

DC-DC conversion, PWM is also used in DC-AC conversion. This aspect

has been studied extensively during the past decades. Many different PWM

methods have been developed to achieve the following aims:

1. Wide linear modulation range;

2. Less switching loss;

3. Less total harmonic distortion (THD) in the spectrum of switching

waveform;

4. Easy implementation and less computation time.

35

The earliest and most straight forward modulation strategy is termed naturally

sampled PWM. A carrier-based PWM modulator is comprised of modulation

signals and carrier signal. It compares a low frequency (modulation signal)

target reference waveform usually sinusoidal, against a high frequency

carrier waveform using a comparator.

Figure 2.4: A simple inverter circuit.

The switches in the voltage source inverter in figure 2.4 above can be turned

on and off as required. In the simplest approach, if the top switch is turned on

and

36

off only once in each cycle, a square wave waveform results. However, if

turned on several times in a cycle an improved harmonic profile may be

achieved.

In the most straightforward implementation, generation of the desired output

voltage is achieved by comparing the desired reference waveform

(modulating signal) with a high-frequency triangular ‘carrier’ wave as

depicted schematically in figure 2.5. Depending on whether the signal

voltage is larger or smaller than the carrier waveform, either the positive or

negative dc bus voltage is applied at the output. Over the period of one

triangle wave, the average voltage applied to the load is proportional to the

amplitude of the signal during this period.

37

Figure 1.5: Essential elements of sinusoidal modulation.

As seen in the figure 2.5 above, the resulting chopped square waveform

contains a replica of the desired waveform in its low frequency components,

with the

38

higher frequency components being at frequencies of an close to the carrier

frequency. In this configuration, the root mean square value of the ac

voltage waveform is still equal to the dc bus voltage, and hence the total

harmonic distortion is not affected by the Pulse Width Modulation process.

The harmonic components are merely shifted into the higher frequency range

and are automatically filtered due to inductances in the ac system. If the

carrier frequency is very high, an averaging effect occurs, resulting in a

sinusoidal fundamental output with high-frequency harmonics, but minimal

low-frequency harmonics.[8]

When the modulating signal is a sinusoid of amplitude V control and the

amplitude of the triangular carrier is Vtri, the ratio m= V control / Vtri, is known

as the modulation index.

......................................2.9

A01A0

10

Vofcomponentfrequencylfundamenta:)(Vwhere,

,2/

)(

dc

A

tri

control

VVofpeak

vvm ==

39

Controlling the modulation index controls the amplitude of the applied output

voltage.

The operation of PWM can be divided into two modes

1) Linear Mode.—In the linear mode, the peak of a modulation signal is less

than or equal to the peak of the carrier signal. When the carrier frequency fcar

is greater than 20 modulation signal frequency , the gain of PWM ≈ 1.

2) Nonlinear Mode—When the peak of a modulation signal is greater than

the peak of the carrier signal, overmodulation occurs with G>1

2.4 PULSE WIDTH MODULATORS

As already noted, pulse width modulation is possible through the

manipulation of the switching function of MOSFETS. The rate of

switching on and off is fast that no human being can effect it. As a

result, integrated circuits are used to effect the switching action required

in pulse width modulation. The integrated circuits used for this job are

Called pulse width modulators. We now spend some time in discussing the

pulse width modulators

40

2.4.1 555 TIMER AS A PULSE WIDTH MODULATOR

The 555 monolithic timing circuits is a highly stable controller capable of

producing accurate time delays, or oscillation. In the time delay mode of

operation, the time is precisely controlled by one external resistor and

capacitor. For a stable operation as an oscillator, the free running frequency

and the duty cycle are both accurately controlled with two external resistors

and one capacitor. The circuit may be triggered and reset on falling

waveforms, and the output structure can source or sink up to 200mA. [9]

The pin configuration of the i.c is shown in figure 2.6 below :

Figure 2. 6:Pin configuration of 555 timer . [10]

Pin 1 is the ground.

Pin 2 is the trigger. It triggers the beginning of a new timing sewquence.

When it goes low, it makes the output pin 3 to go high. The trigger is

41

activated when the voltage on the pin falls below 1/3 of the input voltage

on pin 8.

Pin 3 is the output pin. The pin usually drives the external circuitry. As

seen in the block diagram of 555 timer as shown in figure 7 below, it has a

totem pole configuration. This means that it can source or sink current. The

high output is usually 1.7 volts lower than +V when sourcing current. The

trigger drives pin 3 low while the threshold pin drives it high.

Pin 4 resets the integrated circuit.

Pin 5 is the voltage control . It allows the input of external voltages to affect

the timing of the 555 chip. When not used, it should be bypassed to ground

through an 0.01uF capacitor.

Pin 6 is the threshold pin. It causes the output to be driven LOW when its

voltage rises above 2/3 of input voltage.

42

Pin 7 is the discharge pin. It shorts to ground when the output pin goes

HIGH. This is normally used to discharge the timing capacitor during

oscillation. Finally pin 8 is the input voltage pin. The 555 timer ic

accepts between 3 and 18 +VDC.

Figure 2.7: The circuit diagram of 555 timer by Tony Van Roon[11]

43

A careful study of the internal configuration of 555timer shows than be

manipulated to serve as pulse width modulator ic. In this regard it can be

used for DC-DC converter as well as DC-AC inverter. In order to use 555

timer as a DC-DC converter, it may be configured as below.

Figure 2.8: 555 timer configured as DC-DC converter.

44

In figure 2.8 above, the reset pin is connected to +V, so it has no effect on the

circuit's operation. When the circuit powers up, the trigger pin is LOW as

capacitor C1 is discharged. This begins the oscillator cycle, causing the output to

go HIGH . When the output goes HIGH, capacitor C1 begins to charge through

the right side of R1 and diode D2. When the voltage on C1 reaches 2/3 of +V, the

threshold (pin 6) is activated, which in turn causes the output (pin 3), and

discharge (pin 7) to go LOW. When the output (pin 3) goes LOW, capacitor C1

starts to discharge through the left side of R1 and D1. When the voltage on C1

falls below 1/3 of +V, the output (pin 3) and discharge (pin 7) pins go HIGH, and

the cycle repeats. Pin 5 is not used for an external voltage input, so it is bypassed

to ground with an 0.01uF capacitor. A careful look at the configuration of R1,

D1, and D2 shows that Capacitor C1 charges through one side of R1 and

discharges through the other side. The sum of the charge and discharge resistance

is always the same, therefore the wavelength of the output signal is constant.

Only the duty cycle varies with R1. The overall frequency of the PWM signal in

this circuit is determined by the values of R1 and C1. In the

45

schematic above, this has been set to 144 Hz. To compute the component values

for other frequencies, this formula is used:

Frequency = 1.44 / (R1 * C1) .................................. ... 2.10

In this circuit, the output pin is used to charge and discharge C1, rather than

the discharge pin. This is done because the output pin has a "totem pole"

configuration. It can source and sink current, while the discharge pin only

sinks current.The discharge pin is used to drive the output. In this case, the

output is a IRFZ46N MOSFET. The gate of the MOSFET must be pulled high

as the discharge pin is open collector only. Being an N channel MOSFET, the

IRFZ46N will conduct from drain to source when the gate pin rises above 4

volts or so. It will stop conducting when the gate voltage falls below this

voltage.

This understanding of the working of 555 timer can also be

manipulated to produce a square wave. Here a timing interval starts when

the trigger input goes lower than 1/3 Vin, or 3.33V. When this happens, the

555 output goes high, and the 555 waits for the threshold input to reach 2/3

input voltage or 6.67V.

46

As the capacitor charges, the threshold input slowly rise until it reaches the

required level. Then, the timing interval ends, the output goes low, and the

capacitor is discharged through the discharge input. When the capacitor is

discharged enough so that the trigger reaches 3.33V, then a new timing

interval begins. The end result is a square wave. Noting that the "high

period" of the cycle takes 0.693×(R1+R2)×C1 seconds and the low period

takes 0.693×R2×C1 seconds. With the values of R1, R2 and C1, this produces

a nearly square wave at at a desired frequency. A useful formular is given

below:

.......................................................................................2.11

We would not end the discussion on 555 timer as pulse width

modulator without noting that the main flaw of 555 timer is that it

does not have internal feedback system. This inadequacy is taken care

of by sg3524.

47

2.4.2 SG 3524 AS A PULSE WIDTH MODULATOR.

SG 3524 belongs to the family of naturally sampled pulse width

modulators. The block diagram is shown below.

Figure2. 9: Block diagram of sg3524.[12]

48

Figure 2.10: Pin configuration of sg3524.

Pin 1 is the inverting input pin for error amplification. It is usually given

feedback signal for output regulation. Pin 2 is the non inverting input for

error amplification. This pin is given a constant reference voltage from

pin 16`. If the input to the non inverting pin is less than the input given

to the inverting inpout pin, the op amp will be low. The opposite situation

yields a high which affects the PWM. Pin 3 is the output pin for the

oscillation section. Pins 4 and 5 are used for current limiting function. Pin

6 is related to the oscillation section. The external resistor working with the

external capacitor at pin 7 connected to the pin determines the frequency of

the oscillation. Usually a fixed value of capacitor is while a variable

resistor is used. Pin 8 is the ground. Pin 9 is the compensation input. The

voltage at pin 9 determines the pulse

49

width of the integrated circuit. Pin 10 is the shutdown input. A high at the

pin shuts the ic down. This is used in effecting crucial controls. Pins 11

and 14 are the outputs of two signals that drive two sets of MOSFETs.

Pins 12 and 13 are the collectors of internal transistors. On them are

connected the supply voltage from the battery pin 15 is the positive supply

for the ic. Pin 16 is the output of the internal voltage regulator. This is

tapped for a number of analogue controls.

Figure2.11 below shows a typical configuration of sg3524 for purposes

of converting DC to AC.

50

Figure 2.11 : Sg3524 based inverter circuit.

In the operation of the circuit above, two switches are connected to emitter

A and B(of the internal transistors) respectively. The switching of the

transistors is in part controlled by the output of the internal comparator. Pin 9

is the compensation input. On that pin is connected a rectified feedback from

the inverter output. The feedback voltage acts as a control signal to the

triangular signal generated at pin 7. The feedback incorporated in sg3524

51

recorded a significant improvement in performance. There is however, still a

snag. The output is square wave. The implication is that the best possible

output from the inverter is modified square wave. Hence, we look another

form of pulse width modulator that can generate sinusoidal wave.

2.4.3 MICROCONTROLLERS AS PULSE WIDTH MODULATORS

PIC is a family of Harvard architecture microcontrollers made by Microchip

Technology, derived from the PIC1650 originally developed by General

Instrument's Microelectronics Division. The name PIC was originally an acronym

for "Programmable Interface Controller". PICs are known for their low cost,

wide availability, large user base, extensive collection of application notes,

availability of low cost or free development tools, and serial programming (and

reprogramming with flash memory) capability.

Microchip Technology has produced a range of micro-controllers with

different bits such as 8-bit micro-controller (i.e. PIC16, PIC17, PIC18), 16-bit

microcontrollers (i.e. PIC24) and 16-bit digital signal controllers (i.e. dsPIC30

52

and dsPIC33F). For the purpose of this study, PIC16F84 was chosen.

Below is the block diagram.

Figure 2.13: Block diagram of 16F84.

The diagram showing the pin-outs of the PIC 16F84 is shown next. We will

go through each pin, explaining what each is used for.

53

Figure 14: pin configuration of 16f84

RA0 To RA4

RA is a bidirectional port. That is, it can be configured as an input or an

output. The number following RA is the bit number (0 to 4). So, we have

one 5-bit directional port where each bit can be configured as Input or Output.

RB0 To RB7

RB is a second bidirectional port. It behaves in exactly the same way as RA,

except there are 8 - bits involved.

54

VSS And VDD

These are the power supply pins. VDD is the positive supply, and VSS is the

negative supply, or 0V. The maximum supply voltage that you can use is 6V,

and the minimum is 2V

OSC1/CLK IN And OSC2/CLKOUT

These pins is where we connect an external clock, so that the microcontroller

has some kind of timing.

MCLR

This pin is used to erase the memory locations inside the PIC (i.e. when we

want to re-program it). In normal use it is connected to the positive supply

rail.

INT

This is an input pin which can be monitored. If the pin goes high, we can

cause the program to restart, stop or any other single function we desire.

T0CK1

This is another clock input, which operates an internal timer. It operates in

isolation to the main clock.

55

Microcontrollers are used for generating the switching patterns of space

vector modulation. A typical schematic is given below

Figure 2.15: Schematic of PIC16F84 based space modulation

We now explore the space vector modulation. In the next chapter.

56

CHAPTER THREE

SPACE VECTOR MODULATION

3.1 FROM SINUSOIDAL PWM TO SPACE VECTOR PWM

Space vector modulation belongs to the family of PWM. Some experts

see it as a form of regular sampled PWM.[14] This research work is

based on space vector modulation. The simplest understanding we can

have is that it is an algorithm that aids the determination of switching

pulse width and their position in a complex plane.

Space vector is a single three dimensional vector existing in a three

dimensional orthogonal space. It is a simultaneous representation of all the

three-phase quantities. It can be defined as

+ ..............................................................................3.1

Space vector modulation, therefore applies to three phase inverters.

57

3.1 THREE PHASE ALTERNATING CURRENT

Most alternating-current (AC) generation and transmission, and a good part of

its use, take place through three-phase circuits. To understand electric power,

one must three-phase concepts. Phase is a frequently-used term around AC.

The word comes from Greek fasis, "appearance," from fanein, "to appear." It

originally referred to the eternally regular changing appearance of the moon

through each month, and then was applied to the periodic changes of some

quantity, such as the voltage in an AC circuit. Electrical phase is measured in

degrees, with 360° corresponding to a complete cycle. A sinusoidal voltage is

proportional to the cosine or sine of the phase.

Three-phase, abbreviated 3φ, refers to three voltages or currents that differ by

a third of a cycle, or 120 electrical degrees, from each other. They go through

their maxima in a regular order, called the phase sequence. The three phases

could be supplied over six wires, with two wires reserved for the exclusive

use of each phase. However, they are generally supplied over only three

wires, and the phase or line voltages are the voltages between the three

possible pairs of

58

wires. The phase or line currents are the currents in each wire. Voltages and

currents are usually expressed as rms or effective values, as in single-phase

analysis.

When a load is connected to the three wires, it should be done in such a way

that it does not destroy the symmetry. This means that three equal loads have

to be connected across the three pairs of wires. One of such connections

looks like an equilateral triangle, or delta, and is called a delta load. Another

symmetrical connection would result if you connected one side of each load

together, and then the three other ends to the three wires.[15] This looks like a

Y, and is called a wye load. These are the only possibilities for a symmetrical

load. The center of the Y connection is, in a way, equidistant from each of the

three line voltages, and will remain at a constant potential. It is called

the neutral, and may be furnished along with the three phase voltages. The

benefits of three-phase are realized best for such a symmetrical connection,

which is called balanced.

59

Three-phase systems that are roughly balanced (the practical case) can be

analysed profitably by a method called symmetrical components. Here, only

balanced three phase circuits as shown in the figure below shall be

considered

Figure 3.1 : Three phase wye and delta connection.

The key to understanding three-phase is to understand the phasor diagram for

the voltages or currents. In the diagram at the right, a, b and c represent the

three lines, and o represents the neutral. Vab, Vbc and Vca are the line or

delta voltages, the voltages between the wires. Vob, Voc and Voa are the wye

voltages, the voltages to neutral. They correspond to the two different ways a

symmetrical load can be connected. The vectors can be imagined rotating

60

anticlockwise with time with angular velocity ω = 2πf, their projections on the

horizontal axis representing the voltages as functions of time.

Considerations such as above provide grounds for the principles of

space vector modulation. As already noted, space vector modulation

applies primarily to three phase inverters. It is therefore necessary at this

point to examine an arrangement of switches that generate three phase

alternating current from direct current. Such an arrangement is shown

in figure 2.17.

Figure 3.2: A three phase inverter circuit.

where, upper transistors: S1, S3, S5

61

lower transistors: S4, S6, S2

switching variable vector: a, b, c

A basic three-phase inverter shown in figure 2.17 above consists of three

pairs of switch. Each pair is complementary. If a switch is off, its

complement is and vice versa. Again, each pair is connected to one of the

three load terminals. For the most basic control scheme, the operation of the

three switches is coordinated so that one switch operates at each 60 degree

point of the fundamental output waveform. This creates a line-to-line output

waveform that has six steps. It is the six step structure that inform the six

segment arrangement of the space vector.

3.2 INTRODUCTION TO SPACE VECTOR ANALYSIS

Space vector analysis starts with the space vector diagram. The space

vector diagram is a visual representation of the basic parameters whose

scientific manipulation would enable a sine wave to be generated from

a DC source. A basic space vector diagram is shown in figure 3.3

62

Figure 3.3: A basic Space Vector diagram.

Consistent with earlier analysis of three phase inverter, the space vector

diagram of a basic three-phase inverter consists of six sectors as shown

above. The six sectors divide 360 degrees into six with each having an

angle of 60. In the basic inverter, there are two levels of DC voltage at the

output as an analysis of figure 2. 19 shows:

63

Figure 3.4: schematic of three phase inverter.

It is however possible to have more voltage levels by modifying the

basic design of figure 9 above. This modification is done by the

introduction of some DC capacitors and clamping diode. This has earned it

the name Neutral Point Clamped(NPC) or Diode Clamped Inverter.[16]

Because they involve more than one level, they are also called multi-level

inverters. Basically, NPC multilevel inverters synthesize the small step of

staircase output voltage from several levels of DC capacitor voltages. An n-

level NPC inverter consists of (n-1) capacitors on the DC bus, 2(n-1)

switching devices per phase and 2(n-2)

64

clamping diodes per phase. Figure 20 shows the structure of 3-level NPC.

The DC bus voltage is split into 3 levels by using 2 DC capacitors, C1 and

C2.

Figure 3.5: 3 levels NPC inverter topology.

65

Each capacitor has Vdc/2 volts and each voltage stress will be limited to one

capacitor level through clamping diodes. The number of levels can be extended

to a higher level by additional switching devices and with these additions, the

inverter will be able to achieve higher AC voltage, producing more voltage

steps that will be approaching sinusoidal with minimum harmonics

distortion.[17]

One important difference between the conventional 2-level and multilevel

NPC is the clamping diode. In case of 3-level NPC inverter, clamping diode,

D1 and D4 clamped the DC bus voltage into three voltage level, +Vdc/2, 0

and -Vdc/2.

Regarding n-level inerter, the following general points are important:

1. Each sector of n- level inverter consists of (n − 1)2 triangles. In the

basic three phase inverter( generally referred to as two level

inverter), each sector represents one triangle. In three level

inverter, there are four triangles per sector.

2. Each vertex of any triangle represents a switching vector .

66

Because of Kirchoff’s law, the sum of line to line voltages is always zero.

This shows an equation of the plane in line to line co-ordinate system. This

means that all the vectors of n-level inverter lies in a plane and they are so

represented. Hence the α β transformation is an important transformation in

space vector analysis. It is very useful in the development of the conceptual

framework for space vector analysis. A set of balanced three-phase voltages in

abc frame can be transformed into a two-dimensional complex frame by the

following transformation[18]

.....................................................................................................3.2

where Va, Vb, and Vc are the three-phase voltages in the abc frame, and Vα and

Vβ are the corresponding voltages in the αβ plane. Applying the transformation

to the output phase voltages corresponding to the n3 switching states results in a

set of switching voltage vectors that form a (n-1)layer hexagon centered at the

67

origin of the αβ plane, and n zero voltage vectors located at the origin. The

hexagon is divided into six 60 degrees sectors specified by I to VI. Projection of

three-phase reference voltages into the αβ plane is a vector called the reference

voltage vector, Vref , with a constant magnitude.

Figure 3.2 which shows a basic space vector diagram has one hexagon.

Similarly, a three level inverter would have two hexagons as shown below

in figure 3.6.

Figure 3.6 : Space vector diagram of a three level inverter

68

CHAPTER FOUR

INVERTER TOPOLOGIES

4.1 BASIC CONCEPTUAL FRAMEWORK FOR SPACE

VECTOR MODULATION

ANALYSIS

Figure 4.1: Space diagram illustrating basic parameters for space

vector analysis.

69

A look at figure 4.1 above shows the essential parameters, the determination

of which defines known SVM topologies and enable analytical determination

of the switching pattern that make Space Vector Modulation possible.

The Reference Vector

Ȗ, is the reference vector (Vref) which by its anti clockwise

movement in the αβ plane traces the sine wave. The aim of SVM is to

generate a reference vector Vref in the αβ plane for each modulation

cycle. Nevertheless as the reference vector may not be the same as

any vector produced by the inverter, its average value can be

generated using more than one vector per modulation cycle by

PWM averaged approximation.

In steady state conditions, the reference vector rotates at a constant

angular speed which defines the frequency of the output voltages.

The amplitude of the voltages is proportional to the length of the

reference vector.

70

Any set of vectors ṽ1, ṽ2, ṽ3 in α β plane can generate reference

vector Vref in the same plane using PWM averaged approximation,

if the reference lies in the triangle connecting the tips of ṽ1, ṽ2,

ṽ3. The average reference vector can be obtained by sequentially

applying these vectors in a modulation period in accordance with

........................................................................................................... 4.1

The assumption here is that Vref remains approximately constant during

a modulation period. This is the foundation for Volt-second balancing

principle which applies in three phase inverter analysis. The volt-second

principle states that the product of the reference voltage Vref and sampling

period Ts equals the sum of the voltage multiplied by the time interval of

chosen space vectors. This gives rise to this equation.

ȖTs = Ȗata + Ȗbtb. .....................................................................................4.2

71

Equation 4.2 above is described as volt-second balance equation. Where

ȖTs =reference voltage * sampling time, Ȗata component of reference

vector in α * the time allotted to it and Ȗbtb component of reference

vector in β * the time allotted to it. On-time calculation is based on the

location of the reference vector within a sector and it is given by

Ts = Ta + Tb + To. ......................................................................................4.3

The time intervals Ta, Tb, and T0 have to be calculated such that the

average volt seconds produced by the vectors, v1,v2 and V0/1 along αβ are

the same as those produced by the desired reference space vector, Ȗ. The

modulation index or amplitude ratio is defined as

M =

Resolving Ȗs along αβ plane, we get:

(Vdc*Ta) + Vdc*cos = ................................... 4.4

and Vdc*sin = Ts

solving for Ta and Tb we get

Ta =Ts* 4.5

72

Tb = Ts* ..........................................................................4.6

From figure 4.1, it is also evident that the reference vector is also a

rotating vector with angle at any instance defined by where f1 is

the fundamental frequency of the inverter output voltage. For a given

magnitude (length) and position, Vref can be synthesized by three nearby

stationary vectors, based on which of the switching states of the inverter can

be selected and gate signals for the active switches can be generated. When

Vref passes through sectors one by one, different sets of switches will be

turned on or off. As a result, when Vref rotates one revolution in space, the

inverter output voltage varies one cycle over time. The inverter output

frequency corresponds to the rotating speed of Vref, while its output voltage

can be adjusted by the magnitude of Vref.

The Stationary Vectors

Besides the rotational Vref we need to determine the stationary vectors.

The determination is based on finding all the possible combination of

votage

73

level with the three phases. Hence for n-level inverter all the possible states

are given by n3 . Hence two level inverter has 8 possible states, while three

level inverter have twenty seven possible states. From the possible states is

generated the per unitized voltage levels given by Vao/Vdc, Vbo/Vdc and

Vco/Vdc. The line to line voltage level is generated from the unitized

voltage by the following relationship

Vab = Vao-Vbo

Vbc = Vbo-Vco

Vca = Vco-Vao

The phase voltage for different swiching states is then got from the

relationship below

van = 2/3* Vao - 1/3*(Vbo + Vco) ...........................................................4.7

vbn = 2/3*Vbo - 1/3*(Vao + Vco) .............................................................4.8

vcn = 2/3*Vco - 1/3*(Vao + Vbo) .............................................................4.9

Finally, the diphase voltage in the alpha Beta plane is got from the

relationship below:

74

Vα = sqrt(2/3)*(van - 0.5*(vbn + vcn)) ................................................4.10

Vβ = sqrt(2/3)*((sqrt(3)/2)*(vbn - vcn)) .................................................4.11

This relationship is based on Clark’s transform. It is very important for

the location of Valpha and Vbeta. When transiting from abc plane to αβ

plane using Clark’s transformation, there are states that give the value of

zero in Vα and Vβ. Those that give values other than zero are called

active vectors and the are located on αβ co-ordinates depending on their

value.

Thus armed, we can use MATLAB tools to plot the space vector diagram

and then do further analysis on different inverter topologies. For this work,

it suffices to investigate two and three level inverters with a view to

determining their switching patterns.

4.2 SWITCHING SEQUENCES

There are several methods suggested in the literature for arrangement of states

in a sampling period. These methods are different with respect to the number

of states used, their order, and shares of zero-vectors, which further

75

lead to different number of switching actions, switching losses, and harmonic

behavior of the inverter. Although two active space-vectors and the zero

space-vector must be applied, their sequence is left unspecified.

The averaging principle used in SVM does not provide any requirement on

zero vector generation during To. Moreover, the sequence of the active

vectors within the sampling period is not unique. The time intervals allocated

to the zero vectors remains To = TS − T1 − T2. We now look at some of

the common schemes.

4.2.1: Conventional Scheme

To reduce the number of the inverter switching, it is necessary to distribute the

switching sequence in such a way that the transition from one state to the next is

performed by switching only one inverter leg at a time. This results in starting the

sampling period with one zero state and ending at the other state. For instance, if

the desired vector is in the first sector of 11, referring to converter states by their

numbers, the conventional SVM uses successions of 0127 and

76

7210 in the first sector, to take advantage of the inherent symmetry in this

method. The switching sequence has to be …0127210… The only remaining

degree of freedom consists in the way we are sharing t0 between the vectors V0

and V7. The two extreme situations are:

Method I - equal sharing of the zero vector intervals on each sampling

interval (t0=t7) This generates a graph as shown in fig 4.2

Fig. 4.2: Pulse generation with Method I

Method II: - Another suggested strategy for the first sector is 012 followed

by 721.

77

Use of only a zero vector interval within each sampling period (Ex: t0=0, t7=Ts-

ta-tb):The time intervals allocated to the homopolar component can be shared in

different ways between V0 and V7 and the way we are placing the active states

within the sampling period influences the content in fundamental or the Total

Harmonic Distortion coefficient. Equal sharing provides a good compromise

between simplicity and Harmonic Current Factor ( HCF ) performance.

Method II can be used only at high sampling frequencies, otherwise important

even harmonics are present in the output phase voltage since the waveform

symmetries are not longer respected. On the other hand, if the sampling

frequency is large enough, the spectral differences between the voltages carried

out by Method I or Method II will be very reduced. Both methods presented

determine three switching/sampling period.

78

Fig. 4.3: Pulse generation with Method II

4.2.2: Basic Bus Clamping SVM

A simple way to synthesize the output voltage vector is to turn-on all the

switches connected to the same DC link busbar at the beginning of the

switching cycle and to turn off sequentially in order to split the zero vector

interval between V0 and V7 (t0=t7)

This method is similar to usual sine-triangle comparison based PWM.

79

The gragh generated is as shown in figure 4.4

Fig. 4.4: Pulse generation with Basic Bus Clamping SVM

4.2.3: Boundary Sampling SVM

This modulation scheme is based on symmetrical sequence within each

sampling period. It looks like “conventional SVM” methods but the

conventional SVM sequence are inside the sampling period. Even if it looks

unnecessarily complicated, this method presents the advantage of a direct

80

implementation on the existing PWM IC working on the basis of center-

aligned PWM. The graph is shown in Figure4.5

Fig. 4.5: Pulse generation with Boundary Sampling SVM

4.2.4: Asymmetric Zero Clamping SVM

By eliminating one zero-vector in each cycle, this method ensures minimum

number of switching by alternating between states that are different only in

one

81

leg state. This method is called discontinuous (or asymmetric zero-clamped), in

contrast to the conventional SVM, which is identified as a continuous method. In

discontinuous strategies, each phase is clamped to the top or bottom dc rail for

one-third (120°), one-sixth (60°), or one-twelfth (30°) of the fundamental cycle,

which eliminates the switching of that phase during the corresponding period.

Fig. 4.6: Some of the possible switching sequences for the first sector. (a), (b):

120o asymmetric zero-clamped, and (c), (d): 60 o asymmetric zero-clamped.

82

CHAPTER FIVE

SIMULATION/RESULTS

5.1 SIMULATION DETAILS OF TWO LEVEL INVERTER

As already noted , a two level inverter has the following schematic

diagram as shown in fig. 5.1

Figure 5.1 : 2 level three phase inverter

Two level inverter has two voltage levels and eight possible switching

states. The table below is an application of the principles and formulars

stated in section 4.1 of this work.

83

Table 5.1: Possible switching staes of two level inverter

Key :

Vab = Vao-Vbo

Vbc = Vbo-Vco

Vca = Vco-Vao

The phase voltage for different swiching states is then got from the

relationship below .

van = 2/3* Vao - 1/3*(Vbo + Vco).............................................................5.1

vbn = 2/3*Vbo - 1/3*(Vao + Vco)..............................................................5.2

vcn = 2/3*Vco - 1/3*(Vao + Vbo)...............................................................5.3

The result using MATLAB is shown below:

>> Vao = [0;0;0;0;1;1;1;1];.....................................................................5.4

S/N

Vab Vbc Vca

0 0 0 0 0 0 0 1 0 0 1 0 - Vdc 2 0 1 0 -Vdc V 0 3 0 1 1 - Vdc 0 Vdc 4 1 0 0 Vdc 0 - Vdc 5 1 0 1 Vdc - 0 6 1 1 0 0 V - Vdc 7 1 1 1 0 0 0

84

Vbo = [0;0;1;1;0;0;1;1];...........................................................................5.5

Vco = [0;1;0;1;0;1;0;1];...........................................................................5.6

van = 2/3* Vao - 1/3*(Vbo + Vco);......................................................5.7

vbn = 2/3*Vbo - 1/3*(Vao + Vco);..........................................................5.8

vcn = 2/3*Vco - 1/3*(Vao + Vbo);..............................................................5.9

valpha = sqrt(2/3)*(van - 0.5*(vbn + vcn));..............................................5.10

vbeta = sqrt(2/3)*((sqrt(3)/2)*(vbn - vcn));...............................................5.11

numb = 1:8;...............................................................................................5.12

Display = [numb' van vbn vcn valpha vbeta]

Display =

Table 5.2 :The generated result of alpha and beta planes of two level

inverter.

1.0000 0 0 0 0 0 0

2.0000 -0.3333 -0.3333 0.6667 -0.4082 -0.7071

3.0000 -0.3333 0.6667 -0.3333 -0.4082 0.7071

4.0000 -0.6667 0.3333 0.3333 -0.8165 0

5.0000 0.6667 -0.3333 -0.3333 0.8165 0

85

6.0000 0.3333 -0.6667 0.3333 0.4082 -0.7071

7.0000 0.3333 0.3333 -0.6667 0.4082 0.7071

8.0000 0 0 0 0 0 0

The space vector diagram for the two level space vector can be

visualised using the G plot function as in table 5.3 below

Table 5.3: generated g plot of two level inverter

A = [0 1 1 1 1 1 1; ... 0 0 1 0 0 0 1; ... 0 0 0 1 0 0 0; ... 0 0 0 0 1 0 0; ... 0 0 0 0 0 1 0; ... 0 0 0 0 0 0 1; ... 0 1 0 0 0 0 0]; B = [0 0; 0.8165 0; 0.4082 0.7071;-0.4082 0.7071;-0.8165 0; ... -0.4082 -0.7071;0.4082 -0.7071; ]; gplot(A,B,'y');

The result is as follows:

86

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

Figure 5.2 :Generated space diagram for two level inverter.

5.2 DETAILS OF THREE LEVEL SIMULATION USING MATLAB

Three level inverter has three voltage levels and twenty seven possible

switching states. Here is the table.

Table 5.4 Truth table for the 3-level 27- voltage states

S/NO NORMALIZED DC VOLTAGE Vao/Vdc Vbo/Vdc Vco/Vdc 1 0 0 0 2 0 0 1 3 0 0 2 4 0 1 0 5 0 1 1

87

6 0 1 2 7 0 2 0 8 0 2 1 9 0 2 2

10 1 0 0 11 1 0 1 12 1 0 2 13 1 1 0 14 1 1 1 15 1 1 2 16 1 2 0 17 1 2 1 18 1 2 2 19 2 0 0 20 2 0 1 21 2 0 2 22 2 1 0 23 2 1 1 24 2 1 2 25 2 2 0 26 2 2 1 27 2 2 2

Key :

Vab = Vao-Vbo

Vbc = Vbo-Vco

88

Vca = Vco-Vao

The phase voltage for different swiching states is then got from the

relationship below .

van = 2/3* Vao - 1/3*(Vbo + Vco)

vbn = 2/3*Vbo - 1/3*(Vao + Vco)

vcn = 2/3*Vco - 1/3*(Vao + Vbo)

The result using MATLAB is shown below:

% M-file for determining Van, Vbn, Vcn, Valpha and Vbeta matrix

% for 3phase 3level inverter Vao =[0;0;0;0;0;0;0;0;0;1;1;1;1;1;1;1;1;1;2;2;2;2;2;2;2;2;2]; Vbo [0;0;0;1;1;1;2;2;2;0;0;0;1;1;1;2;2;2;0;0;0;1;1;1;2;2;2]; Vco =[0;1;2;0;1;2;0;1;2;0;1;2;0;1;2;0;1;2;0;1;2;0;1;2;0;1;2]; Van = 2/3 * Vao - 1/3 * (Vbo + Vco); Vbn = 2/3 * Vbo - 1/3 * (Vao + Vco); Vcn = 2/3 * Vco - 1/3 * (Vao + Vbo); Valpha = sqrt (2/3) * (Van - 1/2 * (Vbn + Vcn)); Vbeta = sqrt (2/3) * (sqrt (3)/2*(Vbn - Vcn)); numb = 1:27;

89

Display = [numb' Van Vbn Vcn Valpha Vbeta]

Display = as shown in table 5.6

Table 5.5:

3-level output voltages and per unitized Vα and Vβ values

numb Van Vbn Vcn Vα Vβ

1.0000 0 0 0 0 0

2.0000 -0.3333 -0.3333 0.6667 -0.5000 -0.8660

3.0000 -0.6667 -0.6667 1.3333 -1.0000 -1.7321

4.0000 -0.3333 0.6667 -0.3333 -0.5000 0.8660

5.0000 -0.6667 0.3333 0.3333 -1.0000 0

6.0000 -1.0000 0 1.0000 -1.5000 -0.8660

7.0000 -0.6667 1.3333 -0.6667 -1.0000 1.7321

8.0000 -1.0000 1.0000 0 -1.5000 0.8660

9.0000 -1.3333 0.6667 0.6667 -2.0000 0

10.0000 0.6667 -0.3333 -0.3333 1.0000 0

11.0000 0.3333 -0.6667 0.3333 0.5000 -0.8660

12.0000 0 -1.0000 1.0000 0 -1.7321

13.0000 0.3333 0.3333 -0.6667 0.5000 0.8660

14.0000 0 0 0 0 0

15.0000 -0.3333 -0.3333 0.6667 -0.5000 -0.8660

16.0000 0 1.0000 -1.0000 0 1.7321

90

17.0000 -0.3333 0.6667 -0.3333 -0.5000 0.8660

18.0000 -0.6667 0.3333 0.3333 -1.0000 0.0000

19.0000 1.3333 -0.6667 -0.6667 2.0000 0

20.0000 1.0000 -1.0000 0 1.5000 -0.8660

21.0000 0.6667 -1.3333 0.6667 1.0000 -1.7321

22.0000 1.0000 0 -1.0000 1.5000 0.8660

23.0000 0.6667 -0.3333 -0.3333 1.0000 0.0000

24.0000 0.3333 -0.6667 0.3333 0.5000 -0.8660

25.0000 0.6667 0.6667 -1.3333 1.0000 1.7321

26.0000 0.3333 0.3333 -0.6667 0.5000 0.8660

27.0000 0 0 0 0 0

>>

The space vector diagram for the three level space vector can be

visualised using the G plot function as follows

A = [0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1; 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0;... 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0; 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0; ... 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0; 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0;... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0; 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0;

91

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0; 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0;... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1; 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0;... 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0; 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0;.... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1; 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0;... 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0; 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1;... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]; B = [0 0; 1 0; 0.5 0.866; -0.5 0.866; -1 0; -0.5 -0.866; 0.5 -0.866; 2 0; 1.5 0.866; 1 1.732; 0 1.732; -1 1.732; -1.5 0.866;... -2 0; -1.5 -0.866; -1 -1.732; 0 -1.732; 1 -1.732; 1.5 -0.866]; gplot(A,B,'k'); text([-0.05,0,0.05, -0.05,-0.01,0.03, -0.05,0,0.05, 0.95,1,1.05, 0.95,1,1.05, 0.45,0.5,0.55, 0.45,0.5,0.55, -0.45,-0.5,-0.55,... -0.45,-0.5,-0.55, -0.95,-1,-1.05, -0.95,-1,-1.05, -0.45,-0.5,-0.55, -0.45,-0.5,-0.55, 0.45,0.5,0.55, 0.45,0.5,0.55,... 1.95,2,2.05, 1.45,1.5,1.55, 0.95,1,1.05, -0.05,0,0.05, -0.95,-1,-1.05, -1.45,-1.5,-1.55, -1.95,-2,-2.05,... -1.45,-1.5,-1.55, -0.95,-1,-1.05, -0.05,0,0.05, 0.95,1,1.05, 1.45,1.5,1.55],[-0.09,-0.09,-0.09, 0.09,0.09,0.09,... 0.25,0.25,0.25, 0.1,0.1,0.1, -0.1, -0.1,-0.1, 0.966,0.966,0.966, 0.766,0.766,0.766, 0.966,0.966,0.966, 0.766,0.766,0.766,... 0.1,0.1,0.1, -0.1,-0.1,-0.1, -0.966,-0.966,-0.966, -0.766,-0.766,-0.766, -0.966,-0.966,-0.966, -0.766,-0.766,-0.766,... 0.1,0.1,0.1, 0.966,0.966,0.966, 1.832,1.832,1.832, 1.832,1.832,1.832, 1.832,1.832,1.832, 0.966,0.966,0.966, 0.1,0.1,0.1,... -0.766,-0.766,-0.766, -1.832,-1.832,-1.832, -1.832,-1.832,-1.832, -1.832,-1.832,-1.832, -0.966,-0.966,-0.966],... ('000111222211100221110121010221110100211101212200210220120020120220210200102202201')', 'HorizontalAlignment','center') axis([-2.3 2.3 -2 2])

The result is as follows:

92

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

000111222

211100

221110

121010

221110

100211

101212

200

210

220120020

120

220

210

200 102 202

201

Figure 5.3: generated space vector for three level inverter

5.3 SIMULINK BLOCK OF 3-LEVEL NEUTRAL POINT CLAMPED

INVERTER AT MODULATION INDICES OF 0.8.

In order to model the three level neutral point clamped inverter the

following functional blocks available in the Simulink were used as

shown in the figure below:

93

vmid v+ -

vac 1

[iac ]

[vac ]

[vabc ]

vab

v+ -

va v+ -

iac

i +-

g9

[g9]

g8

[g8]

g7

[g7 ]

g6

[g6]

g5

[g5 ]

g4

[g4]

g3

[g3]

[vabc ]

[vac ]

[iac ]

[g1]

[g9 ]

[g11]

[g12 ]

[g10 ]

g2

[g2]

[g5 ]

[g7 ]

[g8 ]

[g6 ]

[g3 ]

[g4 ]

[g2 ]

g12

[g12 ]

g11[g11]

g10

[g10 ]

g1

[g1]

Vdc2

Vdc1

To Workspace9

g1c

To Workspace3

vmidc

To Workspace2

vac

To Workspace 1

vabc

Three -PhaseSeries RLC Branch 1

ABC

ABC

Subsystem1

vabc

vac

iac

Scope 2

Scope 1

Scope

S9

g CE

S8

g CE

S7

g CE

S6

g CE

S5

g CE

S4

g CE

S3g C

E

S2

g CE

S12

g CE

S11

g CE

S10

g CE

S1

g CE

D6

D5

D4

D3

D2

D1

3levelsignal1

94

powergui

Discrete,Ts = 2.778e-006

To Workspace

trr

Three Level Inverter(Diode Clamped )

3levels ignal

SVPWM Signal Generator

MATLABFunction

Ramp time signal7 segment

Dwell time calculation block

MATLABFunction

Angle generator

thetha

wt

wt1

vq

2/3*(u(2)*sin(2*pi /3)+u(3)*sin(4*pi /3))

vd

2/3*(u(1)+u(2)*cos(2*pi /3)+u(3)*cos(4*pi /3))

Vcn

f(u)

Vbn

f(u)

Van

f(u)

To Workspace

tsp

Magnitude

MATLAB Fcn

MATLABFunction

Clock

0.16

Cartesian toPolar

The introduction of equation already generated for space vector

modulation into the model generated the reference angle and magnitude of

95

reference vector . A ramp signal was also generated using the repeating

sequence signal block obtained from source block in the Simulink sub-library.

Switching frequency of 4 KHz which corresponds to a sampling time of

250microsecond was applied in the dwell time calculation block using the

format mentioned in the flow chart of figure 2.24. The ramp signal was

multiplexed with the dwell time calculation and the output was fed into

SVPWM signal generator block. This block generates the pulse signal that

triggers the twelve IGBT/DIODE switches with the aid of the go-to and go-

from block obtained from signal routing block in the Simulink sub-library.

The result is as follows:

96

Figure 30: 3-level space vector modulation waveform for a modulation index

0.8.

5.4 SIMULATION USING PROTEUS LITE

The MATLAB simulation is rather theoritical. When the theoritically

calculated timing sequences were practicall implemented using

MPLAB(The

97

Integrated Development Environment developed by Microchip for

programming Programmable Integrated Circuits such as PIC16F84.), it was

evident that MATLAB could not be used for the simulation.

Consequently, Proteus Lite (ISIS) was subseqently used. A practically

implementable circuit as shown in figure 30 below below was developed

.

OSC1/CLKIN16

RB0/INT 6

RB1 7

RB2 8

RB3 9

RB4 10

RB5 11

RB6 12

RB7 13

RA0 17

RA1 18

RA2 1

RA3 2

RA4/T0CKI 3

OSC2/CLKOUT15

MCLR4

U1

PIC1684APROGRAM=..\..\Conventi onal SVM\Conventi onal 16\Conventional SVM16.hex

R5130RR6130R

R7130RR8130R

R9130RR10

130R

D1

LED-BLUED2

LED-BLUED3

LED-BLUED4

LED-BLUED5

LED-BLUED6

LED-BLUE

6

5

4

1

2

U2

OPTOCOUPLER-NPN

6

5

4

1

2

U3

OPTOCOUPLER-NPN

6

5

4

1

2

U4

OPTOCOUPLER-NPN

6

5

4

1

2

U5

OPTOCOUPLER-NPN6

5

4

1

2

U6

OPTOCOUPLER-NPN6

5

4

1

2

U7

OPTOCOUPLER-NPN

R122k

R222k

R322k

R422k

R1122k

R1222k

V112V

Q1BUZ10

Q2BUZ10

Q3BUZ10

Q4BUZ10

Q5BUZ10

Q6BUZ10

B112V

+88.8Volts

+88.8Volts

A

B

L4

2mH

L5

2mHL6

2mH

R13

5RR145R

R155R

C11000u

C21000u

98

The different program in appendix 1 yielded the following results

when slightly modified in terms of timing sequence:

Conventional SVM

Figure 31: ISIS result of Conventional SVM

99

Boundary sampling SVM

Figure 32: ISIS result of Boundary sampling SVM

100

Asymmetric zero clamping SVM

Figure 33: ISIS result of Asymmetric Clamping SVM

101

Basic Bus Clamped SVM

Figure 34: ISIS result of Basic Bus Clamped SVM.

102

CHAPTER SIX

OBSERVATIONS AND CONCLUSION

6.1 OBSERVATIONS

In the practical experience of manipulating space vector based pulse width modulation, one discovers that a more advanced switching algorithm, like space vector modulation (SVM), overcomes the drawbacks of sine PWM algorithm and increases the overall system efficiency. The designer is in charge to a large extent. He has the freedom to switch the mosfets in way that would yield the best result.

Aside from freedom in arranging the converter states within one sampling - period, which is absent in the conventional waveform-comparing PWM methods, SVM is superior to conventional PWM in that it is innately designed for digital implementation. This makes it readily available for microcomputer-based implementation as well as simulation with digital .simulators just as it was possible to do with ISIS professional.

It is possible to summarise the advantages of space vector modulation as follows:

• Line to line voltage amplitude can be as high as VDC, Thus 100% d.c voltage utilization is possible in the output region

• In the linear operating range, modulation index range is 0.0 to 1.0 in the sine PWM; whereas in SVM, it is 0.0 to 0.866. Line to line voltage amplitude is 15% more in the SVM with the modulation index = 0.866, compared to the sine PWM with modulation index = 1.0. Hence, it has a better usage of the modulation index dept.

• With the increased output voltage, the user candesign a motor control system with reduced current rating. Keeping the horse power rating the

103

same. The reduced current helps to reduce inherent conduction loss in voltage source inverters.

• Only one reference space vector is controlled to generate three phase sine waves.

• Implementation of the switching rules gives less TDH (total harmonic distortion) and less switching loss.

• Flexibility to select inactive states and their distribution in the switching time periods gives two degree of freedom.

• As the reference space vector is a two dimensional quantity, it is feasible to implement more advanced vector control using SVM.

6.2 CONCLUSION

The work on space vector based pulse width modulation has proved to be exceptionally simulating. The underlying mathematics may to some extent appear to be complex, but its application is one of the sweetest experience an electronic engineer would have.

In practice, however, the bigger challenge is not in the development switching pattern or the space vector modulation techniques. The real, challenge lies in the area of developing practical filters that would effectively separate the high frequency from the lower ones.

This was exceptionally challenging because the components and machines that would make things easy are no where to be found around the country. The efforts to improvise, though it paid us, but there was a very big price-impression.

104

It is, therefore hoped that further research work would need to be undertaken in the area of designing and appropriate realizable filters for space vector based inverters.

REFERENCES

[1] T.G. Wang. X. Zhou, and F.C. Less, A low voltage high efficiency and high power density DC/DC converter. In Proc. IEEE power Electron. Spec. Conf. Volume 1, pp240-245, 1997.

[2] www.epia.org. Solar Generation V Report, Sept.08.

[3] www.alldatsheet.come. SG5324

[4] Gottlieb. I.M., Power Supplies, inverter and converters, BPB pub, New Delhi, p5.

[5] Malvino, Electronic principles, McGraw-Hill International edition,2001 p. 12

[6] Adler M. Pulse width modulation: Mecano Pub, India p.4

[7] Gottlieb. I.M. Power Suppliers, inverter and converters, New Delhi, BPB pub, pp229-241

[8] Lipo T.A., Analysis of Space vector modulation Techniques, John Wiley and sons inc. Canada, 2003, pp. 105-109

[9] Lipo T.A., Analysis of Space vector Modulation Techniques, John Wiley and sons inc. Canada, 2003, p.124.

[10] www.aldatasheet.com 555 timer

[11] Room, T.V., Understanding 555 timer in www.hobbycircuit. Com.

[12] www.aldatsheet.con. SG5324

105

[13] www.aldatsheet.com. 16F84

[14] Lipo, T.A., Analysis of Space vector Modulation Techniques, John . Wiley and sons inc. Canada, 2003, pp. 105-109. Pp. 319-320

[15] Rizzoni Giorgi, Principles nad Application of electrical engineering. Mcgraw Hill, Toronto, 2000,

[16] Nabae, A.I., et al, “A new neutral-point clamped pwm inverter,” IEEE Trans Ind. Apppl.vol. IA-17, no. 5, Sep./Oct. 1981, pp. 518-523.

[17] Barbose P. Et al. “active neutral point clamped multilevel converter technology .” in IEEE Proceeding ofthe European Power Electronics Conference EPE, September 2005.p200.

[18] Seo, I. Et al, “A new simplified space-vector pwm methodforthree-level inverters.” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 545-550, Jul. 2001.

[19] Loh, P.C. Et al., “Implementation and control of distributed pwm cascaded multilevel inverters with minimal harmonic distortion and common-mode voltage,” IEE Trans. Power Electron., vol. 20, no. 1, pp. 90-99, Jan 2005.

[20] Jennis, D andWueest, F., “The optimization parameters of space vector modulation,” in proc. 5th European Conf. Power Electronics and Applications, 1993, pp. 376-381.

[21] Nashiren F. M, “Neutral-Point Clamped Multilevel Inverter Using Space Vector Modulation” in European Journal of Scientific Research Vol.28 No.1 (2009), pp.82-91

[22] Gupa, A.K. Et. Al, “A two-level inverter based svpwm algorithm for a multilevel inverter,” in Proc. Annu. Conf. IEEE Ind. Electron. Soc. (IECON), Nov. 2004, vol 2, pp. 1823-1823.

106

APPENDIX 1

A microchip based programm that can realize rtwo level space vector inverter.

Start ORG 0x00 ;This sets up the ports

BSF 03,

MOVLW 00h

MOVWF 05h

MOVWF 06h

BCF 03,5

; This routine generates appriopriate SVM signals that switches

inverter transistors

call clrghost

clrf0ah;clears the PCLATH and takes care of the program counter upper bit

movlw 00h

Movwf 10h ;file 10h is the table pointer

movlw 13h

movwf 04h ; le selects register 13h

107

getnext incf 10h,1 increment file 10h to point at the next pattern on the table

movf10h,0 ;move the content of 10h to the working reg so as to point at the pattern on

the table

xorlw 83h

btfsc 03h,2;

goto inc_PCLATCH

continue movf 10h,00h

call tableSVM movwf 00h ;store the value of the pattern returned from the table in

file 23h

ncf 04h,1

xorlw0a ;XOR 0aah with the content of the working file (reg)

btfsc03,2 ;check if zero flag in the STATUS reg is set i.e (=1) i.e the value of W is

0aah

goto gen_svm

goto getnext

inc_PCLATCH ncf 0ah,1

108

goto continu

;this subroutine clears the ghost files

Clrghost movlw 13h

movwf 04h

movlw .8

movwf 0dh

loopg clrf 00h

ncf 04h,

decfsz 0dh,1

goto loopg

return

;the subroutine generates SVM pattern

gen_svm

movlw .8

movwf 0dh

109

space1 movf 13h,0

movwf 06h

CALL DelT0

movf 17h,0

movwf 06h

CALL DelT1

movf 18h,

movwf 06h

CALL DelT2

movf 15h,0

movwf 06h

CALL DelT0;space 1 pattern

movf 15h,0

movwf 06h

CALL DelT0

movf 18h,0

movwf 06h

CALL DelT2

movf 17h,0

movwf 06h

CALL DelT1

110

movf 13h,0

movwf 06h

CALLDelT0 ;space 1 pattern

decfsz 0dh,1

goto space1

movf 15h,0

movwf 06h

CALLDelT0 ;space 2 pattern

movf 15h,0

movwf 06h

CALL DelT0

movf 18h,0

movwf 06h

CALL DelT1

movf 19h,0

movwf 06h

CALL DelT2

movf 13h,0

movwf 06h

CALLDelT0 ;space 2 pattern

111

decfsz 0dh,1

goto space2

movlw .8

movwf 0dh

space2 movf 13h,0

movwf 06h

CALL DelT0

movf 19h,0

movwf 06h

CALL DelT2

movf 18h,0

movwf 06h

CALL DelT1

112

movlw .8

movwf 0dh

space3

movf 13h,0

movwf 06h

CALL DelT0

movf 19h,0

movwf 06h

CALL DelT1

movf 1ah,0

movwf 06h

CALL DelT2

movf 15h,0

movwf 06h

CALLDelT0 ;space 3 pattern

movf 15h,1

movwf 06

CALL DelT0

movf 1ah,0

movwf 06h

CALL DelT2

movf 19h,0

113

movwf 06h

CALL DelT1

movf 13h,0

movwf 06h

CALLDelT0 ;space 3 pattern

decfsz 0dh,1

goto space

movlw .8

movwf 0dh

space4

movf 13h,0

movwf 06h

CALL DelT0

movf 14h,0

movwf 06h

CALL DelT2

movf 1ah,0

movwf 06h

CALL DelT1

movf 15h,0

movwf 06h

CALLDelT0 ;space 4 pattern

114

movf 15h,0

movwf 06h

CALL DelT0

movf 1ah,0

movwf 06h

CALL DelT1

movf 14h,0

movwf 06h

CALL DelT2

movf 13h,0

movwf 06h

CALLDelT0 ;space 4 pattern

decfsz 0dh,1

goto space4

movlw .8

movwf 0dh

space5

movf 13h,0

movwf 06h

CALL DelT0

movf 14h,0

movwf 06h

115

CALL DelT1

movf 16h,0

movwf 06h

CALL DelT2

movf 15h,0

movwf 06h

CALL DelT0

space 5 pattern

movf 15h,0

movwf 06h

CALL DelT0

movf 16h,0

movwf 06h

CALL DelT2

movf 14h,0

movwf 06h

CALL DelT1

movf 13h,0

movwf 06h

CALL DelT0

space 5 pattern

decfsz 0dh,

116

goto space5

movlw .8

movwf 0dh

space6

movf 13h,0

movwf 06h

CALL DelT0

movf 17h,0

movwf 06h

CALL DelT2

movf 16h,0

movwf 06h

CALL DelT1

movf 15h,0

movwf 06h

CALL DelT0

space 6 pattern

movf 15h,0

movwf 06h

CALL DelT0

movf 16h,0

movwf 06h

117

CALL DelT1

movf 17h,0

movwf06h

CALL DelT2

movf 13h,0

movwf 06h

CALLDelT0 ;space 6 pattern

decfsz 0dh,1

goto space6

GOTO gen_svm

; subroutine for delay(T0,T1, and T2)

DelT0 movlw .1

del0 DECFSZ 0fh,1 Delay for T0

GOTO del0

RETURN

DelT1 movlw .5

movwf 0fh

del1 DECFSZ 0fh,1 ;Delay for T1

GOTO del1

RETURN

DelT2 movlw .15

movwf 0fh

118

del2 DECFSZ 0fh,1 ;Delay for T2

GOTO del2

RETURN

;routine for WELCOME TO movement (right to left) pattern

tableSVM ADDWF 02h,1 ;Add W to Program Counter

RETLW 00h

retlw 1ch ; space 1

retlw 38h

retlw 0e0h

retlw 0a8h

retlw 8ch ;assumed space 2

retlw 0c4h ;assumed space 3

retlw 54h ;assumed space 4

retlw 70h ;assumed space 5

retlw 0aah ;assumed space 6

end

119

Appendix 12

Dwell time calculation program

function [y]=omeje3(u) ln=2; % for 3-level inverter ts=1/4000; h=(sqrt(3))/2; m=0.80; %modulation index vs=3*m*ln/pi; wt1=u(1); wt2=u(2); yh=rem(wt2,pi/3); si=floor((wt1/(pi/3))+1); if ((si>=-2) && (si<-1)) si=4; else if ((si>=-1) && (si<0)) si=5; else if ((si>=0) && (si<1)) si=6; else si=si; end end end va=vs*cos(yh); vb=vs*sin(yh); k1=floor(va+vb/sqrt(3)); k2=floor(vb/h); vai=va-k1+0.5*k2; vbi=vb-k2*h; if vbi<=vai*sqrt(3) vao=vai; vbo=vbi; tri=(k1^2)+(2*k2); else vbi>vai*sqrt(3)

120

vao=0.5-vai; vbo=h-vbi; tri=(k1^2)+(2*k2)+1; end ta=ts/2*(vao-vbo/(2*h)) tb=ts/2*vbo/h2 to=(ts/2-ta-tb) y=[ta tb to tri si wt2 wt1]; Appendix 13. The SVPWM signal generator program function [y]=test335(u) s=u(5); %input from dwell time calculation block for sector determination tri=u(4); %input from dwell time calculation block for triangle determination tr=u(8); % ramp input from seven segment repeating sequence block ta=u(1); % input time for the first active vector derived from dwell time block tb=u(2); % input time for the second active vector derived from dwell time block to=u(3); % input time for the zero vector derived from dwell time block wt=u(6); % input angle for the zero and active vector derived from dwell time block m1=[0 0 0 0 0 0 0]; % seven segment binary controlled logic values m2=[1 1 1 1 1 1 1]; % for the twelve switching pattern using the upper m3=[0 0 0 1 0 0 0]; % and lower switching method m4=[1 1 1 0 1 1 1]; % the lower switches are assigned m5=[0 0 1 1 1 0 0]; % the inverse value of the upper switches m6=[1 1 0 0 0 1 1]; % for the whole switching sequence m7=[0 1 1 1 1 1 0]; % In the six sectors m8=[1 0 0 0 0 0 1]; %sector 1 triangle 0 if (s<=1) & (tri<=0) & (wt<pi/6) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t);

121

v1=m3; v3=m4; v2=m2; v4=m1; v5=m1; v7=m2; v6=m7; v8=m8; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 1 triangle 1 if (s<=1) & (tri>0) & (tri<=1) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m1; v7=m2; v6=m5; v8=m6; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 1 triangle 2 if (s<=1) & (tri>1) & (tri<=2) & (wt<pi/6) t=[tb/2 ta to tb to ta tb/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m1; v7=m2; v6=m7; v8=m8; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end

122

%sector 1 triangle 2 if (s<=1) & (tri>1) & (tri<=2) & (wt>=pi/6) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 1 triangle 3 if (s<=1) & (tri>2) & (tri<=3) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m5; v7=m6; v6=m2; v8=m1; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 1 triangle 0 if (s<=1) & (tri>-1) & (tri<=0) & (wt>=pi/6) t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end

123

%sector 2 triangle 0 if (s>1) & (s<=2) & (tri>-1) & (tri<=0) & (wt<pi/2) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m3; v3=m4; v2=m2; v4=m1; v5=m5; v7=m6; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 2 triangle 1 if (s>1) & (s<=2) & (tri>=1) & (tri<2) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m7; v7=m8; v6=m2; v8=m1; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 2 triangle 2 if (s>1) & (s<=2) & (tri>1) & (tri<=2) & (wt<pi/2) t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m3; v3=m4; v2=m2; v4=m1; v5=m7; v7=m8; v6=m2; v8=m1; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end

124

end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j);end %sector 2 triange 2 if (s>1) & (s<=2) & (tri>1) & (tri<=2) & (wt>=pi/2) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m7; v4=m8; v5=m5; v7=m6; v6=m2; v8=m1; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 2 triangle 3 if (s>1) & (s<=2) & (tri>2) & (tri<=3) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m7; v7=m8; v6=m2; v8=m1; v9=m1; v11=m2; v10=m3; v12=m4; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 2 triangle 0 if (s>1) & (s<=2) & (tri<=0) & (wt>pi/2) t=[tb/2 ta to tb to ta tb/2]; t=cumsum(t); v1=m1; v3=m2; v2=m7; v4=m8; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7

125

if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 3 triangle 0 if (s>2) & (s<=3) & (tri<=0) & (wt<5*pi/6) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 3 triangle 1 if (s>2) & (s<=3) & (tri>=1) & (tri<2) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4; v5=m7; v7=m8; v6=m2; v8=m1; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 3 triangle 2 if (s>2) & (s<=3) & (tri>=2) & (tri<3) & (wt<=5*pi/6) t=[tb/2 ta to tb to ta tb/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4;

126

v5=m5; v7=m6; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 3 triangle 2 if (s>2) & (s<=3) & (tri>=2) & (tri<3) & (wt>=5*pi/6) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m7; v7=m8; v6=m2; v8=m1; v9=m3; v11=m4; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 3 triangle 3 if (s>2) & (s<=3) & (tri>2) & (tri<=3) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4; v5=m7; v7=m8; v6=m2; v8=m1; v9=m5; v11=m6; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %section 3 triangle 0 if (s>2) & (s<=3) & (tri<=0) & (wt>=5*pi/6)

127

t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m1; v3=m2; v2=m7; v4=m8; v5=m5; v7=m6; v6=m2; v8=m1; v9=m3; v11=m4; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 4 triangle 0 if (s>3) & (s<=4) & (tri<=0) & (wt<7*pi/6) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m7; v4=m8; v5=m5; v7=m6; v6=m2; v8=m1; v9=m3; v11=m4; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end %sector 4 triangle 1 if (s>3) & (s<=4) & (tri>=1) & (tri<2) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4; v5=m5; v7=m6; v6=m2; v8=m1; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end

128

%sector 4 triangle 2 if (s>3) & (s<=4) & (tri>1) & (tri<=2) & (wt<7*pi/6) t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m3; v7=m4; v6=m2; v8=m1; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end %sector 5 triangle 0 if (s>4) & (s<=5) & (tri<=0) & (wt<3*pi/2) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m7; v4=m8; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end %sector 5 triangle 1 if (s>4) & (s<=5) & (tri>=1) & (tri<2) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m1; v7=m2; v6=m3; v8=m4; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end

129

%sector 5 triangle 2 if (s>4) & (s<=5) & (tri>=2) & (tri<3) & (wt>=3*pi/2) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m3; v3=m4; v2=m2; v4=m1; v5=m1; v7=m2; v6=m5; v8=m6; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end %sector 5 triangle 3 if (s>4) & (s<=5) & (tri>2) & (tri<=3) t=[to/2 ta tb to tb ta to/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m1; v7=m2; v6=m3; v8=m4; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j);

130

s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 5 triangle 0 if (s>4) & (s<=5) & (tri<=0) & (wt>=3*pi/2) t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m3; v3=m4; v2=m2; v4=m1; v5=m5; v7=m6; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end %sector 6 triangle 0 if (s>5) & (s<=6) & (tri<=0) & (wt<11*pi/6) t=[ta/2 to tb ta tb to ta/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end %sector 6 triangle 1 if (s>5) & (s<=6) & (tri>=1) & (tri<2) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m1; v7=m2; v6=m3; v8=m4; v9=m5; v11=m6; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end

131

s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 6 triangle 2 if (s>5) & (s<=6) & (tri>=2) & (tri<3) & (wt<11*pi/6) t=[tb/2 to ta tb ta to tb/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m1; v7=m2; v6=m5; v8=m6; v9=m3; v11=m4; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 6 triangle 2 if (s>5) & (s<=6) & (tri>=2) & (tri<3) & (wt>=11*pi/6) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t); v1=m5; v3=m6; v2=m2; v4=m1; v5=m1; v7=m2; v6=m3; v8=m4; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 6 triangle 3 if (s>5) & (s<=6) & (tri>2) & (tri<=3) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m7; v3=m8; v2=m2; v4=m1; v5=m1; v7=m2; v6=m3; v8=m4; v9=m1; v11=m2; v10=m5; v12=m6;

132

for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 6 triangle 0 if (s<=6) & (tri<=0) & (wt>=11*pi/6) & (wt<12*pi/6) t=[tb/2 ta to tb to ta tb/2]; t=cumsum(t); v1=m3; v3=m4; v2=m2; v4=m1; v5=m1; v7=m2; v6=m7; v8=m8; v9=m1; v11=m2; v10=m5; v12=m6; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v9(j); s6=v10(j); s7=v11(j); s8=v12(j); s9=v5(j); s10=v6(j); s11=v7(j); s12=v8(j); end y=[s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12];

133

if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 4 triangle 2 if (s>3) & (s<=4) & (tri>1) & (tri<=2) & (wt>=7*pi/6) t=[ta/2 tb to ta to tb ta/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4; v5=m1; v7=m2; v6=m7; v8=m8; v9=m5; v11=m6; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j); end %sector 4 triangle 3 if (s>3) & (s<=4) & (tri>2) & (tri<=3) t=[to/2 tb ta to ta tb to/2]; t=cumsum(t); v1=m1; v3=m2; v2=m3; v4=m4; v5=m1; v7=m2; v6=m5; v8=m6; v9=m7; v11=m8; v10=m2; v12=m1; for j=1:7 if (tr<t(j)) break end end s1=v1(j); s2=v2(j); s3=v3(j); s4=v4(j); s5=v5(j); s6=v6(j); s7=v7(j); s8=v8(j); s9=v9(j); s10=v10(j); s11=v11(j); s12=v12(j);

134

end %sector 4 triangle 0 if (s>3) & (s<=4) & (tri<=0) & (wt>7*pi/6) t=[tb/2 ta to tb to ta tb/2]; t=cumsum(t); v1=m1; v3=m2; v2=m5; v4=m6; v5=m3; v7=m4; v6=m2; v8=m1; v9=m1; v11=m2; v10=m7; v12=m8; for j=1:7 if (tr<t(j)) break end

2. Sci-Tech Dictionary. McGraw-Hill Dictionary of Scientific and Technical Terms. Copyright © 2003, 1994, 1989, 1984, 1978, 1976, 1974 by McGraw-Hill Companies, Inc

3. Philips Semiconductors Linear Products