UNIT .4 I/O INTERFACING 8085

Syllabus Memory Interfacing and I/O interfacing Parallel communication interface Serial communication interface Timer Keyboard /display controller Interrupt controller DMA controller Programming and applications.

OVERVIEW

CPU and main memory are very fast compared with electromechanical

input or output devices like printers, etc. In such case it is essential that the data

lines of the computer are not kept engaged for a long time during communication

with input/output devices. Otherwise, the overall speed of the computer system

comes down drastically. So I/O devices are connected to a computer through I/O

ports.

For example, to communicate with a printer, the CPU loads the output port

connected to the printer at electronics speed. The printer slowly prints this. When

printer has finished printing, the output port requests the CPU for further data.

This way, the CPU is allowed to work at its full speed, with no degradation in the

overall speed of the computer system.

In fact, to further improve the speed, a printer will have printer buffer. For

example, the dot matrix printer has buffer size of 3KB. The microcomputer fills

this buffer in a fraction of second. Then as far as the computer is concerned the

printing is over. But the user would not have witnessed the printing of a single

character yet. The printer prints the entire information in about 15-20s. Then a

printer requests for further data to be printed, from the computer.

The I/O devices are never directly connected to a computer. Computer

and an I/O device always communicate with an I/O port as the middleman.

LEARNING OBJECTIVES

Need for I/O ports

Memory interfacing and I/O interfacing

Serial communication interface

Timer

Keyboard/display controller

Interrupt controller

DMA controller

Programming and applications

1.THE 8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI).

8255 IS A WIDELY USED, PROGRAMMABLE, PARALLEL I/O DEVICE.

It can be programmed to transfer data under various conditions from simple

I/O to interrupt I/O.

It is flexible, versatile & economical (when multiple I/O ports are required),

but somewhat complex.

It is an important general purpose I/O device that can be used with almost

any P.

BLOCK DOAGRAM OF 8255.

It has two 8-bit ports (A&B), two 4 bit ports (Cu & CL), the data bus buffer,

& control logic (Fig 1a).

Fig 1b shows a simple but expanded version of internal structure including

control register.

Fig 1a Fig 1b Control Logic. It has 6 lines ___

1. RD: Enables read operation. When low, MPU reads data from selected I/O port of the 8255A.

2. WR bar: Enables write operation to selected port or control register. 3. RESET: Active high signal that clears the control register & sets all pots in

input mode. __ __ 4. CS bar, A0, A1: Theses are device select signals. CS is connected to a

decoded address & A0 & A1 are generally connected to MPU address lines A0 & A1.

The CS bar signal is master chip select & A0, A1 specify one of the I/O ports or control register s given below: __

8255A

Port A

Port B

Port C

Cu

CL

D7 D6 D5 D4 D3 D2 D1 D0

I/O mode

Mode0 Mode1 Mode2

Simple I/O for ports A, B, C

Hand-shake I/O for ports A, &/or B Port C bits used for H/S

Bi-direction-al data bus for port A Port B either in Mode 0 or 1 Port C bits used for h/s

BSR Mode Bit set/ Reset For port C No effect on I/O mode

0/1

CS A1 A0 Selected 0 0 0 Port A 0 0 1 Port B 0 1 0 Port C 0 1 1 Control register 1 X X 8255 not selected As an example, port addresses in Fig 2a are determined by CS bar, A0 & A1. The CS bar line goes low when A7=1 & A6 thru A2 are at logic 0. When these signals are combined with A0 & A1, the port addresses range from 80H to 83H as shown in Fig 2b.

Fig 2: 8255A Chip select logic (a) & I/O port addresses (b) CONTROL WORD.

8255 __ CS A1 A0 __ RD __ WR

A7 A6 A5 A4 A3 A2

A1 A0 ___ IOR ___ IOW

A=80H

C=82H

B=81H

__ Hex Addr Port CS A7A6A5A4A3A2 A1 A0 1 0 0 0 0 0 0 0 = 80H A 0 1 = 81H B 1 0 = 82H C 1 1 = 83H Control Reg

Fig 2(a)

Fig 2(b)

Fig 1b shows a register called Control Register. The contents of this register called the control word specify an I/O function for each port. This register can be accessed to write a control word when A0 & A1 are at logic 12. The register is NOT accessible for a Read operation. Bit D7 of the control register specifies either a BSR Mode or I/O function mode. If D7=1, D6 thru D0 determine I/O functions in various modes. To communicate with peripherals thru 8255A, 3 steps are necessary:

1. Determine the addresses of ports A, B, C & the control register according to Chip Select logic & address lines A1 & A0.

2. Write a control word in the control register. 3. Write I/O instructions to communicate with peripherals thru ports A, B, C.

MODE: Simple Input or Output Ports A & B are used as 2 simple 8-bit ports & Port C as two 4-bit ports. Each port (or half port for C) can be programmed to function as simple Input/ Output Port. The I/O features in Mode 0 are:

1. Outputs are latched 2. 2. Inputs are not latched. 3. Ports do NOT have handshake or interrupt capability.

Program:

1. Identify port addresses in following figure. 2. Identify Mode 0 control word to configure port A & CU as input ports & port

B & CL as output ports.

3. Write a program to read DIP switches & display the reading from port B at

port A & from CL to port CU.

D7 D6 D5 D4 D3 D2 D1 D0 Port C (Lower PC3-PC0) 1 = Input 0 = Output

Port B 1 = Input 0 = Output

Mode selection 0 = Mode 0 1 = Mode 1

GROUP B

Port C (Upper PC7-PC4) 1 = Input 0 = Output

Port A 1 = Input 0 = Output

Mode selection 00 = Mode 0 01 = Mode 1, 1X = Mode 2

1 = I/O Mode 0 = BSR Mode

GROUPA

8255 A

Buffer

Buffer

DIP switches

PA7 PA0 PC7 PC4 PC3 PC0 PB7 PB0

A15 A1 A0 MEMR MEMW RESET OUT

8085

+ 5V

+5V

LEDs

CS A1 A0 __ RD WR Reset

Ans:1. Port Addresses. This is a memory mapped I/O; when address line A15 is high, Chip Select is enabled. Assuming all don’t care lines are at logic 0, port addresses are as follows: Port A = 8000H (A1 = 0, A0 = 0) Port B = 8001H (A1 = 0, A0 = 1) Port C = 8002H (A1 = 1, A0 = 0) Control register = 8003H (A1 = 1, A0 = 1) 2. Control Word D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 1 | | | | | | | | = 83H V ____ V | | V V I/O | Port A | | Port B Port CL function V = output | | = Input = Input Port A | |

In mode0 | | | | V |-> Port B in mode0 Port CU = Output

4. Program MVI A, 83H ; LOAD ACC with control word. STA 8003 ; Write word in control register to initialize the ports LDA 8001 ; Read switches at port B STA 8000 : display the reading at port A LDA8002 ; Read switches at port C ANI 0FH ; Mask the upper 4 bits of port C, these bits are not input

data RLC ; rotate & place data in the upper half of ACC RLC ; RLC ; RLC ; STA 8002H ; display data at port CU. HLT

Program Description: The circuit is designed for memory mapped I/O; so the instructions are written as if all 8255 ports are memory locations. Ports are initialized by loading the control word 83H in the control register. STA & LDA are equivalent to 8 bit port I/O instructions IN & OUT respectively.

The low 4 bits of port C are configured as input & high 4 bits are configured as output. Read & Write memory operations are differentiated by control signals MEMR bar & MEMW bar. BSR (Bit Set/Rest Mode) – It is concernd only with the 8 bits of port C which can be set/ reset by witing appropriate control word in th control register. A control word with bit D7 = 0 is rcognized as a BSR control word & it DOES NOT ALTR any previously transmitted control word with bit D7 = 1. thus, I/O operations of ports A & B are NOT AFFECTED by a BSR control word. In this mode, individual bits of port C can be used as ON/OFF switches.

Fig: 8255 Control Word format in the BSR Mode Q: Write a BSR Control word subroutine to set PC7 & PC3 & reset them after 10 ms. Use the following figure & assume that delay s/r is available. A: BSR Control Words: D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 0 X X X Bit Select S/R

SET = 1 Reset = 0

000 = Bit 0 001 = Bit 1 010 = Bit 2 011 = Bit 3 100 = Bit 4 101 = Bit 5 110 = Bit 6 111 = bit 7

BSR Mode

Not used, generally set to 0

To set bit PC7 : 0 0 0 0 1 1 1 1 = 0FH To reset bit PC7 : 0 0 0 0 1 1 1 0 = 0EH To set bit PC3 : 0 0 0 0 0 1 1 1 = 07H To reset bit PC3 : 0 0 0 0 0 1 1 0 = 06H Port address Control register address = 83H SUBROUTINE BSR: MVI A, 0FH ; Load byte in ACC to set PC7

OUT 83H ; Set PC7 = 1 MVI A, 07H ; Load byte in ACC to set PC3 OUT 83H ; Set PC3 = 1 CALL DELAY; This is 10ms delay MVI A, 06H ; Load byte in ACC to reset PC3 OUT 83H ; Reset PC3 MVI A, 0EH ; Load byte in ACC to reset PC7 OUT 83H ; Set PC7 RET

MODE1: input or Output with handshake. Handshake signals are exchanged between the MPU and peripherals prior to data transfer. Features of this mode are:

1. 2 ports A & B function as 8 bit I/O ports. May be configured either as input or output ports.

2. Each port uses 3 lines from port C as h/s signals. Remaining 2 lines of port c may be used for simple I/O functions.

3. Input & Output data are latched. 4. Interrupt logic is supported.

In 8255, Input & output functions are discussed separately. Mode1: Input control signals.

INTEA

PC3

PC5

PC4

PA0

PA7

INTEB

___

RD

PC6,7

PC2

PC0

PC1

___ STBA IBFA INTRA

Port A Input

___ STBB IBFB INTRB

Port B Input

I/O

1 0 1 1 1/0 1 1 X

I/O mode

Port A mode 1

Port A input

PC6,7 1 = i/p 0 = o/p

Port B input

Port B input

Control Word – Mode 1 input

8255A Mode 1 : I/p configuration

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

Status Word – Mode 1 input

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

____ STB: Strobe Input: Active low signal is generated by a peripheral device to indicate that it has transmitted a byte of data. 8255 generates IBF & INTR in response to STB bar. IBF (Input Buffer Full): It is an acknowledgement by 8255 to indicate that the input latch has received the data byte. It is reset when MPU reads the data byte. INTR (Interrupt request): This is an output signal that may be ued to interrupt the MPU. This signal is generated if STB bar, IBF & INTE (Interrupt Enable internal flip-flop) are all at logic 1. this is reset by falling edge of the RD bar signal. INTE (Interrupt Enable): Internal f/f used to enable/disable the generation of INTR signal. 2 f/f s (INTEA& INTEB) are set/reset using BSR mode. The former is enabled/ disabled thru PC4 & latter thru PC2.

Fig: 8255A mode 1: Timing Waveforms for strobed input with handshake.

STB

IBF

INTR

RD

Input from peripheral

Programming the 8255A in Mode1. 8255A may be programmed to function in either status check or interrupt I/O. Both flowcharts are shown in figure. In (a), MPU continues to check data status thru IBF line until it goes high. It is a simplified flow chart, it does NOT show how to handle data transfer if 2 ports are being used. Disadvantage of status check I/O with h/s is that MPU is held up in the loop. Fig (b) shows steps for interrupt I/O assuming vectored interrupts are available. Fig: Flow charts: (a) Status Check (b) Interrupt I/O Mode1: Output control signals.

Continue

INTEA

PC3

PC6

PC7

INTEB

___

WR

PC4,5

PC2

PC0

PC1

___ OBFA ACKA INTRA

Port A Output

ACKB _____ OBFB INTRB

Port B Input

I/O

1 0 1 0 1/0 1 0 X

I/O mode

Port A mode 1

Port A output

PC4,5 1 = i/p 0 = o/p

Port B Mode 1

Port B output

Control Word – Mode 1 input

8255A Mode 1 : O/p configuration

_____ _____ OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB

Status Word – Mode 1 output

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

OBF (Output Buffer Full): It is an o/p signal that goes low when the MPU writes data to o/p latch of 8255A. It indicates to peripheral that new data is available for reading. It goes high again after 8255A receives ACK bar from peripheral. ___ ACK: This is an input acknowledge signal from a peripheral that must o/p a low when peripheral receives the data from the 8255A ports. INTR (Interrupt request): This is an output signal that may be used to interrupt the MPU. This signal is generated if OBF, ACK bar & INTE (Interrupt Enable internal flip-flop) are all at logic 1. This is reset by falling edge of the WR bar signal. INTE (Interrupt Enable): Internal f/f used to enable/disable the generation of INTR signal. 2 f/f s (INTEA& INTEB) are set/reset using BSR mode. The former is enabled/ disabled thru PC6 & latter thru PC2.

Fig: 8255A mode 1: Timing Waveforms for strobed output with handshake. Mode 2: Bidirectional data transfer: Used for transfer of data between 2 computers or floppy disk controller interface. Port A can be configured as bidirectional port & port B in either Mode 0 or 1. Port A uses 5 signals from port c as h/s signals. The remaining 3 signals from port C may be used as simple I/O or h/s for port B.

WR

____ OBF

INTR

ACK

Output from peripheral

PC3 PA7-PA0 PC7 PC6 PC4 PC5 PC2-0 PB7-PB0

INTRA 8 OBF ACKA STBA IBFA I/O 8

RD __ WR

1 1 X X X 0 1 1/0

D7 D6 D5 D4 D3 D2 D1 D0

PC2-0 1= i/p 0 = o/p

Control word

Port A Mode 2 and mode 0 (Input)

2.8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.

As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion.

This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.

PC3 PA7-PA0 PC7 PC6 PC4 PC5 PC1

PC2 PC0

PB7-PB0

INTRA 8 OBF ACKA STBA IBFA ____ OBFB ACKB INTRB 8

RD __ WR

1 1 X X X 1 0 X

D7 D6 D5 D4 D3 D2 D1 D0

Control word

Mode 2 and mode 1 (Input)

Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)

The 8251 functional configuration is programed by software.

Operation between the 8251 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device.

3.Programmable Keyboard/Display Interface - 8279 A programmable keyboard and display interfacing chip.

Scans and encodes up to a 64-key keyboard.

Controls up to a 16-digit numerical display.

Keyboard section has a built-in FIFO 8 character buffer.

The display is controlled from an internal 16x8 RAM that

stores the coded display information.

Pinout Definition 8279

� A0: Selects data (0) or control/status (1) for reads and

writes between micro and 8279.

� BD: Output that blanks the displays.

� CLK: Used internally for timing. Max is 3 MHz.

� CN/ST: Control/strobe, connected to the control key on

the keyboard. Pinout Definition 8279

� CS: Chip select that enables programming, reading the keyboard, etc.

� DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.

� IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.

� OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant

nibble of display.

� RD(WR): Connects to micro's IORC or RD signal, reads data/status registers.

� RESET: Connects to system RESET.

� RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix.

� Shift: Shift connects to Shift key on keyboard.

� SL3-SL0: Scan line outputs scan both the keyboard and displays.

Keyboard Interface of 8279 The keyboard matrix can be any size from 2x2 to 8x8.

Pins SL2-SL0 sequentially scan each column through a counting operation.

The 74LS138 drives 0's on one line at a time.

The 8279 scans RL pins synchronously with the scan.

RL pins incorporate internal pull-ups, no need for external resistor pull-ups.

The 8279 must be programmed first.

The first 3 bits of the byte sent to control port selects one of 8 control words.

D7 D6 D5 Function Purpose

0 0 0 Mode set Selects the number of display positions, type of key scan...

0 0 1 Clock Programs internal clk, sets scan and debounce times.

0 1 0 Read FIFO Selects type of FIFO read and address of the read.

0 1 1 Read Display Selects type of display read and address of the read.

1 0 0 Write Display Selects type of write and the address of the write.

1 0 1 Display write inhibit Allows half-bytes to be blanked.

1 1 0 Clear Clears the display or FIFO

1 1 1 End interrupt Clears the IRQ signal to the microprocessor.

4.8259 – PROGRAMMABLE INTERRUPT CONTROLLER

Features:

8 levels of interrupts.

Can be cascaded in master-slave configuration to handle 64 levels of

interrupts.

Internal priority resolver.

Fixed priority mode and rotating priority mode.

Individually maskable interrupts.

Modes and masks can be changed dynamically.

Accepts IRQ, determines priority, checks whether incoming priority >

current level being serviced, issues interrupt signal.

In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8

bit vector number.

Polled and vectored mode.

Starting address of ISR or vector number is programmable.

No clock required.

Pinout

D0-D7

Bi-directional, tristated, buffered data lines.

Connected to data bus directly or through

buffers

RD-bar Active low read control

WR-bar Active low write control

A0 Address input line, used to select control

register

CS-bar Active low chip select

CAS0-2

Bi-directional, 3 bit cascade lines. In master

mode, PIC places slave ID no. on these lines. In

slave mode, the PIC reads slave ID no. from

master on these lines. It may be regarded as

slave-select.

SP-bar Slave program / enable. In non-buffered

/ EN-

bar

mode, it is SP-bar input, used to distinguish

master/slave PIC. In buffered mode, it is

output line used to enable buffers

INT Interrupt line, connected to INTR of

microprocessor

INTA-

bar

Interrupt ack, received active low from

microprocessor

IR0-7 Asynchronous IRQ input lines, generated by

peripherals.

Block diagram

ICW1 (Initialisation Command Word One)

A0 D7 D6 D5 D4 D3 D2 D1 D0

0

A7 A6 A5 1 LTIM ADI SNGL IC4

D0: IC4: 0=no ICW4, 1=ICW4 required

D1: SNGL: 1=Single PIC, 0=Cascaded PIC

D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart

(0200, 0204, etc) 0=ISR's are 8 byte apart (0200, 0208, etc)

D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge

triggered

D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is

A7 A6 A5 A4 A3 A2 A1 A0

of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are

provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself:

ADI=1 (spacing 4 bytes)

IRQ A7 A6 A5 A4 A3 A2 A1 A0

IR0 A7 A6 A5 0 0 0 0 0

IR1 A7 A6 A5 0 0 1 0 0

IR2 A7 A6 A5 0 1 0 0 0

IR3 A7 A6 A5 0 1 1 0 0

IR4 A7 A6 A5 1 0 0 0 0

IR5 A7 A6 A5 1 0 1 0 0

IR6 A7 A6 A5 1 1 1 0 0

IR7 A7 A6 A5 1 1 1 0 0

ADI=0 (spacing 8 bytes)

IRQ A7 A6 A5 A4 A3 A2 A1 A0

IR0 A7 A6 0 0 0 0 0 0

IR1 A7 A6 0 0 1 0 0 0

IR2 A7 A6 0 1 0 0 0 0

IR3 A7 A6 0 1 1 0 0 0

IR4 A7 A6 1 0 0 0 0 0

IR5 A7 A6 1 0 1 0 0 0

IR6 A7 A6 1 1 0 0 0 0

IR7 A7 A6 1 1 1 0 0 0

ICW2 (Initialisation Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

ICW3 (Initialisation Command Word Three)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

Master S7 S6 S5 S4 S3 S2 S1 S0

Slave 0 0 0 0 0 ID3 ID2 ID1

Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct

interrupt

Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has

ICW3=04h (0000 0100)

ICW4 (Initialisation Command Word Four)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 SFNM BUF M/S AEOI Mode

SFNM: 1=Special Fully Nested Mode, 0=FNM

M/S: 1=Master, 0=Slave

AEOI: 1=Auto End of Interrupt, 0=Normal

Mode: 0=8085, 1=8086

OCW1 (Operational Command Word One)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

M7 M6 M5 M4 M3 M2 M1 M0

IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)

OCW2 (Operational Command Word Two)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

R SL EOI 0 0 L3 L2 L1

R SL EOI Action

0 0 1 Non specific EOI (L3L2L1=000)

EOI 0 1 1

Specific EOI command (Interrupt to

clear given by L3L2L1)

1 0 1 Rotate priorities on non-specific EOI

1 0 0 Rotate priorities in auto EOI mode

set Auto rotation of priorities

(L3L2L1=000)

0 0 0 Rotate priorities in auto EOI mode

clear

1 1 1 Rotate priority on specific EOI

command (resets current ISR bit)

1 1 0 Set priority (does not reset current

ISR bit)

Specific rotation of priorities

(Lowest priority ISR=L3L2L1)

0 1 0 No operation

OCW3 (Operational Command Word Three)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

D7 ESMM SMM 0 1 MODE RIR RIS

ESMM SMM Effect

0 X No effect

1 0 Reset special mask

1 1 Set special mask

Interrupt sequence (single PIC)

1. One or more of the IR lines goes high.

2. Corresponding IRR bit is set.

3. 8259 evaluates the request and sends INT to CPU.

4. CPU sends INTA-bar.

5. Highest priority ISR is set. IRR is reset.

6. 8259 releases CALL instruction on data bus.

7. CALL causes CPU to initiate two more INTA-bar's.

8. 8259 releases the subroutine address, first lowbyte then highbyte.

9. ISR bit is reset depending on mode.

5.8257 DMA CONTROLLER

Three Transaction Methods for

Peripheral IOs

• DMAC and 8257 DMAC

• 8257 Block Diagram, Pins and

Interfacing

• 8257 Programming

6.8254 Programmable Interval Timer/Counter

Features

Status read-back command

Counter latch command

Read/write least significant bit (LSB) only, most significant bit (MSB) only,

or LSB first then MSB

Six programmable counter modes

o Interrupt on terminal count

o Hardware retriggerable one-shot

o Rate generator

o Square wave mode

o Software-triggered strobe

o Hardware-triggered strobe (retriggerable)

Binary or binary coded decimal strobe

Developed in VHDL and synthesizes to approximately 5,000 gates

Functionally based on the Intel 82C54 device

Block Diagram

Figure 1 shows the block diagram for the 8254 programmable interval

timer/counter megafunction.

Figure 1. Block Diagram

Description

The 8254 programmable interval time/counter megafunction is a high-

performance function that is designed to solve the common timing control

problems in microcomputer system design.

It provides three independent 16-bit counters, and each counter may operate in a

different mode. All modes are software programmable.

The 8254 megafunction solves one of the most common problems in any

microcomputer system: the generation of accurate time delays under software

control.

Instead of setting up timing loops in software, the 8254 megafunction can be

programmed to match requirements by programming one of the counters for the

desired delay.

8253/8254 PIT - Programmable Interval Timer

Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)

Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)

Port 42h, 8253 Counter 2 Cassette and Speaker Functions

Port 43h, 8253 Mode Control Register, data format:

|7|6|5|4|3|2|1|0| Mode Control Register

| | | | | | | `---- 0=16 binary counter, 1=4 decade BCD counter

| | | | `--------- counter mode bits

| | `------------ read/write/latch format bits

`--------------- counter select bits (also 8254 read back

command)

Bits

76 Counter Select Bits

00 select counter 0

01 select counter 1

10 select counter 2

11 read back command (8254 only, illegal on 8253, see below)

Bits

54 Read/Write/Latch Format Bits

00 latch present counter value

01 read/write of MSB only

10 read/write of LSB only

11 read/write LSB, followed by write of MSB

Bits

321 Counter Mode Bits

000 mode 0, interrupt on terminal count; countdown, interrupt,

then wait for a new mode or count; loading a new count in

the

middle of a count stops the countdown

001 mode 1, programmable one-shot; countdown with optional

restart; reloading the counter will not affect the

countdown

until after the following trigger

010 mode 2, rate generator; generate one pulse after 'count'

CLK

cycles; output remains high until after the new countdown

has

begun; reloading the count mid-period does not take affect

until after the period

011 mode 3, square wave rate generator; generate one pulse

after

'count' CLK cycles; output remains high until 1/2 of the

next

countdown; it does this by decrementing by 2 until zero, at

which time it lowers the output signal, reloads the counter

and counts down again until interrupting at 0; reloading

the

count mid-period does not take affect until after the

period

100 mode 4, software triggered strobe; countdown with output

high

until counter zero; at zero output goes low for one CLK

period; countdown is triggered by loading counter;

reloading

counter takes effect on next CLK pulse

101 mode 5, hardware triggered strobe; countdown after

triggering

with output high until counter zero; at zero output goes

low

for one CLK period

Read Back Command Format (8254 only)

|7|6|5|4|3|2|1|0| Read Back Command (written to Mode Control

Reg)

| | | | | | | `--- must be zero

| | | | | | `---- select counter 0

| | | | | `----- select counter 1

| | | | `------ select counter 2

| | | `------- 0 = latch status of selected counters

| | `-------- 0 = latch count of selected counters

`----------- 11 = read back command

Read Back Command Status (8254 only, read from counter register)

|7|6|5|4|3|2|1|0| Read Back Command Status

| | | | | | | `--- 0=16 binary counter, 1=4 decade BCD counter

| | | | `-------- counter mode bits (see Mode Control Reg

above)

| | `----------- read/write/latch format (see Mode Control Reg)

| `------------ 1=null count (no count set), 0=count available

`------------- state of OUT pin (1=high, 0=low)

- the 8253 is used on the PC & XT, while the 8254 is used on the

AT+

- all counters are decrementing and fully independent

- the PIT is tied to 3 clock lines all generating 1.19318 MHz.

- the value of 1.19318MHz is derived from (4.77/4 MHz) and has

it's

roots based on NTSC frequencies

- counters are 16 bit quantities which are decremented and then

tested against zero. Valid range is (0-65535). To get a value

of 65536 clocks you must specify 0 as the default count since

65536 is a 17 bit value.

- reading by latching the count doesn't disturb the countdown

but

reading the port directly does; except when using the 8254 Read

Back Command - counter 0 is the time of day interrupt and is

generated approximately 18.2 times per sec. The value 18.2 is

derived from the frequency 1.10318/65536 (the normal default

count).

- counter 1 is normally set to 18 (dec.) and signals the 8237 to

do

a RAM refresh approximately every 15æs

- counter 2 is normally used to generate tones from the speaker

but can be used as a regular counter when used in conjunction

with the 8255

- newly loaded counters don't take effect until after a an

output

pulse or input CLK cycle depending on the mode

- the 8253 has a max input clock rate of 2.6MHz, the 8254 has

max

input clock rate of 10MHz

Programming considerations:

1. load Mode Control Register

2. let bus settle (jmp $+2)

3. write counter value

4. if counter 0 is modified, an INT 8 handler must be written

to

call the original INT 8 handler every 18.2 seconds. When

it

does call the original INT 8 handler it must NOT send and

EOI

to the 8259 for the timer interrupt, since the original

INT 8

handler will send the EOI also.

Example code:

countdown equ 8000h ; approx 36 interrupts per second

cli

mov al,00110110b ; bit 7,6 = (00) timer counter 0

; bit 5,4 = (11) write LSB then MSB

; bit 3-1 = (011) generate square wave

; bit 0 = (0) binary counter

out 43h,al ; prep PIT, counter 0, square wave&init

count

jmp $+2

mov cx,countdown ; default is 0x0000 (65536) (18.2 per sec)

; interrupts when counter decrements to 0

mov al,cl ; send LSB of timer count

out 40h,al

jmp $+2

mov al,ch ; send MSB of timer count

out 40h,al

jmp $+2

sti

7.Analog-to-digital converter An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device

which converts continuous signals to discrete digital numbers. The reverse

operation is performed by a digital-to-analog converter (DAC).

Typically, an ADC is an electronic device that converts an input analog voltage (or

current) to a digital number proportional to the magnitude of the voltage or

current. However, some non-electronic or only partially electronic devices, such as

rotary encoders, can also be considered ADCs. The digital output may use different

coding schemes, such as binary, Gray code or two's complement binary.

Resolution

The resolution of the converter indicates the number of discrete values it can

produce over the range of analog values.

The values are usually stored electronically in binary form, so the resolution is

usually expressed in bits. In consequence, the number of discrete values available,

or "levels", is usually a power of two.

For example, an ADC with a resolution of 8 bits can encode an analog input to one

in 256 different levels, since 28 = 256. The values can represent the ranges from 0 to

255 (i.e. unsigned integer) or from -128 to 127 (i.e. signed integer), depending on

the application.

Resolution can also be defined electrically, and expressed in volts. The voltage

resolution of an ADC is equal to its overall voltage measurement range divided by

the number of discrete intervals as in the formula:

Where:

Q is resolution in volts per step (volts per output code),

EFSR is the full scale voltage range = VRefHi − VRefLow,

M is the ADC's resolution in bits.

N is the number of intervals, given by the number of available levels (output

codes), which is: N = 2M

Some examples may help:

Example 1

o Full scale measurement range = 0 to 10 volts

o ADC resolution is 12 bits: 212 = 4096 quantization levels (codes)

o ADC voltage resolution is: (10V - 0V) / 4096 codes = 10V / 4096

codes 0.00244 volts/code 2.44 mV/code

Example 2

o Full scale measurement range = -10 to +10 volts

o ADC resolution is 14 bits: 214 = 16384 quantization levels (codes)

o ADC voltage resolution is: (10V - (-10V)) / 16384 codes = 20V /

16384 codes 0.00122 volts/code 1.22 mV/code

Example 3

o Full scale measurement range = 0 to 8 volts

o ADC resolution is 3 bits: 23 = 8 quantization levels (codes)

o ADC voltage resolution is: (8 V − 0 V)/8 codes = 8 V/8 codes = 1

volts/code = 1000 mV/code

In practice, the smallest output code ("0" in an unsigned system) represents a

voltage range which is 0.5X of the ADC voltage resolution (Q)(meaning half-wide

of the ADC voltage Q ) while the largest output code represents a voltage range

which is 1.5X of the ADC voltage resolution (meaning 50% wider than the ADC

voltage resolution). The other N − 2 codes are all equal in width and represent the

ADC voltage resolution (Q) calculated above. Doing this centers the code on an

input voltage that represents the M th division of the input voltage range. For

example, in Example 3, with the 3-bit ADC spanning an 8 V range, each of the N

divisions would represent 1 V, except the 1st ("0" code) which is 0.5 V wide, and

the last ("7" code) which is 1.5 V wide. Doing this the "1" code spans a voltage

range from 0.5 to 1.5 V, the "2" code spans a voltage range from 1.5 to 2.5 V, etc.

Thus, if the input signal is at 3/8ths of the full-scale voltage, then the ADC outputs

the "3" code, and will do so as long as the voltage stays within the range of 2.5/8ths

and 3.5/8ths. This practice is called "Mid-Tread" operation. This type of ADC can

be modeled mathematically as:

The exception to this convention seems to be the Microchip PIC processor, where

all M steps are equal width. This practice is called "Mid-Rise with Offset"

operation.

In practice, the useful resolution of a converter is limited by the best signal-to-

noise ratio that can be achieved for a digitized signal. An ADC can resolve a signal

to only a certain number of bits of resolution, called the "effective number of bits"

(ENOB). One effective bit of resolution changes the signal-to-noise ratio of the

digitized signal by 6 dB, if the resolution is limited by the ADC. If a preamplifier has

been used prior to A/D conversion, the noise introduced by the amplifier can be an

important contributing factor towards the overall SNR.

Response type

Linear ADCs

Most ADCs are of a type known as linear[1] The term linear as used here means that

the range of the input values that map to each output value has a linear relationship

with the output value, i.e., that the output value k is used for the range of input

values from

m(k + b)

to

m(k + 1 + b),

where m and b are constants. Here b is typically 0 or −0.5. When b = 0, the ADC is

referred to as mid-rise, and when b = −0.5 it is referred to as mid-tread.

Non-linear ADCs

If the probability density function of a signal being digitized is uniform, then the

signal-to-noise ratio relative to the quantization noise is the best possible. Because

this is often not the case, it is usual to pass the signal through its cumulative

distribution function (CDF) before the quantization. This is good because the

regions that are more important get quantized with a better resolution. In the

dequantization process, the inverse CDF is needed.

This is the same principle behind the companders used in some tape-recorders and

other communication systems, and is related to entropy maximization.

For example, a voice signal has a Laplacian distribution. This means that the region

around the lowest levels, near 0, carries more information than the regions with

higher amplitudes. Because of this, logarithmic ADCs are very common in voice

communication systems to increase the dynamic range of the representable values

while retaining fine-granular fidelity in the low-amplitude region.

An eight-bit A-law or the µ-law logarithmic ADC covers the wide dynamic range

and has a high resolution in the critical low-amplitude region, that would

otherwise require a 12-bit linear ADC.

Accuracy

An ADC has several sources of errors. Quantization error and (assuming the ADC

is intended to be linear) non-linearity is intrinsic to any analog-to-digital

conversion. There is also a so-called aperture error which is due to a clock jitter and

is revealed when digitizing a time-variant signal (not a constant value).

These errors are measured in a unit called the LSB, which is an abbreviation for

least significant bit. In the above example of an eight-bit ADC, an error of one LSB

is 1/256 of the full signal range, or about 0.4%.

Quantization error

Main article: Quantization noise

Quantization error is due to the finite resolution of the ADC, and is an unavoidable

imperfection in all types of ADC. The magnitude of the quantization error at the

sampling instant is between zero and half of one LSB.

In the general case, the original signal is much larger than one LSB. When this

happens, the quantization error is not correlated with the signal, and has a uniform

distribution. Its RMS value is the standard deviation of this distribution, given by .

In the eight-bit ADC example, this represents 0.113% of the full signal range.

At lower levels the quantizing error becomes dependent of the input signal,

resulting in distortion. This distortion is created after the anti-aliasing filter, and if

these distortions are above 1/2 the sample rate they will alias back into the audio

band. In order to make the quantizing error independent of the input signal, noise

with an amplitude of 1 quantization step is added to the signal. This slightly reduces

signal to noise ratio, but completely eliminates the distortion. It is known as dither.

Non-linearity

All ADCs suffer from non-linearity errors caused by their physical imperfections,

resulting in their output to deviate from a linear function (or some other function,

in the case of a deliberately non-linear ADC) of their input. These errors can

sometimes be mitigated by calibration, or prevented by testing.

Important parameters for linearity are integral non-linearity (INL) and differential

non-linearity (DNL). These non-linearities reduce the dynamic range of the signals

that can be digitized by the ADC, also reducing the effective resolution of the ADC

Digital-to-analog converter

In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for

converting a digital (usually binary) code to an analog signal (current, voltage or

electric charge).

An analog-to-digital converter (ADC) performs the reverse operation.

A DAC converts an abstract finite-precision number (usually a fixed-point binary

number) into a concrete physical quantity (e.g., a voltage or a pressure). In

particular, DACs are often used to convert finite-precision time series data to a

continually-varying physical signal.

A typical DAC converts the abstract numbers into a concrete sequence of impulses

that are then processed by a reconstruction filter using some form of interpolation

to fill in data between the impulses. Other DAC methods (e.g., methods based on

Delta-sigma modulation) produce a pulse-density modulated signal that can then

be filtered in a similar way to produce a smoothly-varying signal.

By the Nyquist–Shannon sampling theorem, sampled data can be reconstructed

perfectly provided that its bandwidth meets certain requirements (e.g., a baseband

signal with bandwidth less than the Nyquist frequency).

However, even with an ideal reconstruction filter, digital sampling introduces

quantization error that makes perfect reconstruction practically impossible.

Increasing the digital resolution (i.e., increasing the number of bits used in each

sample) or introducing sampling dither can reduce this error.

Instead of impulses, usually the sequence of numbers update the analogue voltage

at uniform sampling intervals.

These numbers are written to the DAC, typically with a clock signal that causes

each number to be latched in sequence, at which time the DAC output voltage

changes rapidly from the previous value to the value represented by the currently

latched number.

The effect of this is that the output voltage is held in time at the current value until

the next input number is latched resulting in a piecewise constant or 'staircase'

shaped output. This is equivalent to a zero-order hold operation and has an effect

on the frequency response of the reconstructed signal.

Piecewise constant signal typical of a zero-order (non-interpolating) DAC output.

The fact that practical DACs output a sequence of piecewise constant values or

rectangular pulses would cause multiple harmonics above the nyquist frequency.

These are typically removed with a low pass filter acting as a reconstruction filter.

However, this filter means that there is an inherent effect of the zero-order hold on

the effective frequency response of the DAC resulting in a mild roll-off of gain at

the higher frequencies (often a 3.9224 dB loss at the Nyquist frequency) and

depending on the filter, phase distortion. Not all DACs have a zero order response

SUMMARY

We have introduced the I/O device interfacing with the

microprocessor and discussed the need for interfacing an I/O

device with microprocessor.

Programmable Peripheral Interface (PPI) is used to interface the

several peripheral devices with microprocessor. 8255 is widely

used PPI.

For serial data communication Universal synchronous

Asynchronous Receiver Transmitter (USART) – 8251 has been

most widely used. Its block diagram was discussed.

Programmable Interrupt controller can be used to connect I/O

devices with 8085/8086. 8259 and 8279 blocks were discussed in

detail.

Finally we have discussed Analog to Digital Converter (ADC)

interface with 8085.

OBJECTIVE TYPE QUESTIONS

1. Access time is faster for

a) ROM b) SRAM

c) DRAM

2. In 8279 Strobed input mode, the control line goes low. The data on return lines

is strobed in the ____.

a) FIFO byte by byte b) FILO byte by byte

c) LIFO byte by byte d) LILO byte by byte.

3. ___ bit in ICW1 indicates whether the 8259A is cascade mode or not?

a) LTIM=0 b) LTIM=1

c) SNGL=0 d) SNGL=1

4. In 8255, under the I/O mode of operation we have __ modes. Under which

mode will have the following features

i) A 5 bit control port is available.

ii) Three I/O lines are available at Port C.

a) 3, Mode2 b) 2, Mode 2

c) 4, Mode 3 d) 3, Mode 2

5. In ADC 0808 if _______ pin high enables output.

a) EOC b) I/P0-I/P7

c) SOC d) OE

6. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___

line goes ____ to interrupt the CPU.

a) CS, high b) A0,

high

c) IRQ, high d) STB, high

7. In 8279 Status Word, data is read when ________ pins are low, and write to

the display RAM with ____________ are low.

a) A0, CS, RD & A

0, WR, CS. b) CS, WR, A

0 & A

0, CS, RD

c) A0, RD & WR, CS d) CS, RD & A

0, CS.

8. In 8279, the keyboard entries are debounced and stored in an _________, that

is further accessed by the CPU to read the key codes.

a) 8-bit FIFO b) 8-byte FIFO

c) 16 byte FIFO d) 16 bit FIFO

9. The 8279 normally provides a maximum of _____ seven segment display

interface with CPU.

a) 8 b) 16

c) 32 d) 18

10. For the most Static RAM the write pulse width should be at least

a) 10ns b) 60ns

c) 300ns d) 1μs

11. BURST refresh in DRAM is also called as

a) Concentrated refresh b) distributed refresh

c) Hidden refresh d) none

12. For the most Static RAM the maximum access time is about

a) 1ns b) 10ns

c) 100ns d) 1μs

13. Which of the following statements on DRAM are correct?

i) Page mode read operation is faster than RAS read.

ii) RAS input remains active during column address strobe.

iii) The row and column addresses are strobed into the internal buffers

using RAS and CAS inputs respectively.

a) i & iii b) i & ii

c) all d) iii

14. 8086 microprocessor is interfaced to 8253 a programmable interval timer.

The maximum number by which the clock frequency on one of the timers is

divided by

a) 216

b) 28

c) 210

d) 220

15. 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s

are in master slave configuration the number of interrupts available to the 8086

microprocessor is a) 8 b) 16

c) 15 d) 64

QUESTIONS

1. Name the two modes of operation of DMA controller?

2. List the operating modes of 8253 timer.

3. Give the control word format of timer?

4. What is the use of USART?

5. Compare serial and parallel communication.

6. What is the use of Keyboard and display controller?

7. What are the functions performed by 8279?

8. What is PPI?

9. Give the control word format for I/O mode of 8255?

10. Give the BSR mode format of 8255.

11. What is the need for interrupt controller?

12. What are the registers present in 8259?

13. What are the applications of 8253?

14. Define interrupts.

15. Define DMA process.

16. Give the status word format of 8257.

17. Draw the Block diagram and explain the operations of 8251 serial

communication interface.

18. Draw the Block diagram of 8279 and explain the functions of each block.

19. Draw the block diagram of programmable interrupt controller and explain its

operations.

20. Discuss in detail about the operation of timer along with its various modes.

21. Draw the Block diagram of DMA controller and explain its operations.

22.What does the CPU do when it receive an interrupt? How do you enable and

disable

interrupts in 8086.

23 Explain the command words/control words of 8259 in details.

24. With the help of block diagram explain various modes of operation of 8259 in

details.

25. Explain type 0,1,2 interrupts found interrupt vector table of 8086/8088

microprocessor.

26. Describe the use of CAS0, CAS and CAS2 lines in a system with a cascaded

8259’s.

27. What are the different modes of operation of the 8253 programmable timer?

How

does 8254 differ from 8253?

28. Which mode will you use to generate a square wave ? Give a flow chart to

generate it on 8253.

29. Explain with neat waveform the mode 0 of the 8253 timer/counter.

30. Explain with the help of block diagram, functioning of 8253 in various

programmable modes.

31. A 32-bit binary counter is to be implemented using timer/counter

i)design and explain the control word to meet above requirement

ii)Draw timing diagram of the mod(s) used.