Elevator 8085 MODEL - 8085projects.in … · Web viewThis project uses the 8085 microprocessor to...

MICROPROCESSOR LAB PROJECTEC – 316

MADE BY:-

ABHISHEK MITTAL 09/EC/13

ANIRUDH MITTAL 26/EC/13

FACULTY ADVISOR:-

PROF. DHANANJAY V. GADRE

Elevator 8085 MODEL

TABLE OF CONTENTS

1. SYNOPSIS 12. INTRODUCTION 2

2.1 Basic Block Diagram 32.2 Motivation and Justification 4

3. SCHEMATIC 64. DESCRIPTION OF THE SCHEMATIC 7

4.1 Basic Components 74.2 Decoding Logic 94.3 Memory Interfacing 94.4 Input-Output Interfacing 104.5 Frequency of Operation 11

5. BOARD LAYOUT 126. LIST OF COMPONENTS 137. THE MANUFACTURED PRINTED CIRCUIT BOARD 14

7.1 Top Layer 147.2 Bottom Layer 157.3 Soldered Board 15

8. FLOW CHART 179.MODULAR TESTING 18

9.1 SID-SOD Testing Code 189.2 Switch Interfacing and Seven Segment Display Code Testing 189.3 Motor Testing Code 199.4 Interrupt Check 22

10. GANTT CHART REVISTED AND COMPARISON WITH ACTUAL RESULTS 2311. CONCLUSION 2412. REFERENCES 25

1. SYNOPSIS

This project uses the 8085 microprocessor to implement an scale model of an elevator. The elevator is operated by interfacing a 12 volt bipolar stepper motor with the microprocessor using the L293D driver IC. The elevator is designed to run between four floors and it works on a priority request logic.

Each of the four floors has two slide switches which designate the direction in which a user on a particular floor wishes to travel in. One slide switch is for going "UP" and the other one is for going "DOWN". Once inside the elevator, a user can press a push button to input the destination floor. These inputs are accepted by the microprocessor through an input interfacing circuit made using buffers and the SOD LED is ON for the period when the door of the elevator is open on a floor. Position of the elevator is displayed on a seven segment display, which is interfaced using a latch. Once the SOD LED turns OFF, the elevator starts moving in the appropriate direction.

GENERAL TERMS/KEYWORDS:

Microprocessor, Latch, Buffer, SOD, LED, Seven Segment Display, Stepper Motor

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2. INTRODUCTION

The 8085 microprocessor was introduced by Intel in 1976 as a successor to the Intel 8080 microprocessor. The 8085 is upward compatible with its predecessor, with only 2 minor instructions added to support its interrupt and input-output features. The 8085 is a conventional Von-Neumann design. Since its advent, the 8085 microprocessor has found use in numerous applications such as early personal computers as well as in several NASA space physics missions in the 1990s.

Few of its features are:

1. The 8085 has 16 signal lines that are used as the address lines, which are divided into two segments: the higher order(A8 to A15) and lower order address lines(AD0 TO AD7).

2. 8 bit data bus3. 6 general purpose 8 bit registers : B,C,D,E,H,L and one Accumulator. The 8085 is an

accumulator based microprocessor.4. Control signals, status signals and interrupts

The 8085 is available as a 40 pin DIP IC.

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Figure 1: Pin Diagram of the 8085

In this project, an scale model of an elevator operated with a stepper motor and user interface controlled with 8085 has been made. As mentioned in the synopsis, the project works on a priority request logic. This can be explained using an example as follows:

Suppose initially the elevator is at 1st floor. A person at the 4th floor who wants to go to the 2nd floor will first call the elevator to his floor by pressing the "DOWN" switch, which is a slide switch. So the elevator will begin to move up. The elevator will stop at an intermediate floor if the request on that floor is in the same direction. Otherwise that intermediate request will be serviced later. When the elevator reaches the 4th floor, the person enters and presses the push button corresponding to the 2nd floor. Requests skipped whilst the elevator was moving up and requests made in the same direction will now be addressed and requests in the opposite direction will again be ignored for the current movement and be addressed later.

2.1) Basic Block Diagram

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Figure 2: Block Diagram for the schematic

2.2) Motivation and Justification

A number of elevator projects have been devised using the 8085 but most of them work as simple transporters. We intended to develop a code which could implement a much more realistic algorithm of elevator operation than being a crude transporter. The initial proposal was to implement the project through LEDs i.e. to use them to indicate the direction of motion of the elevator. However, Prof. Gadre suggested a unique and practical implementation of the model by suggesting to develop an actual working small size model of an elevator using a motor of our choice.

The justification of the project stems from the fact that such an elevator model using the 8085 is a first of its kind. Not only does this project involve considerable complexity in both hardware and software designing, it also demonstrates a real life application which is almost ubiquitous

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3. SCHEMATIC

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4. DESCRIPTION OF THE SCHEMATIC

4.1) Basic Components

Latch: The 74HC573 is an 8 bit D type transparent latch with three state outputs. It features a latch enable(LE) and an output enable(OE').

The 74HC573 is made up of 8 D-type flip flops with a parallel input parallel output connection, which allows output of 8 bits simultaneously on the data bus lines. Each flip flop is enabled when the LE is high and the OE' is low. It is generally used for interfacing output peripherals( LEDs, seven segment display etc.) with the microprocessor.

Buffer: The 74HC244 is an 8 bit buffer in which each of the eight output lines can have 3 possible states: logic 1, logic 0 and high impedance. It's also popularly known as a tri-state device and finds use in interfacing input peripherals with the microprocessor.

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Figure 3: Functional Diagram of the 74HC573

Figure 4: Logic Diagram of the 74HC573

Logic Gates: Logic gates are the fundamental components of most digital circuits. Basic logic gate ICs such as AND(7408), OR(7432) and NAND(7400) are usually employed in schematics for microprocessor based circuits to design the necessary addresses for the various input and output ports. This is further explained in the topic "Decoding Logic" under the section "Schematic Description of the Project".

Decoders: The decoder is a logic circuit that identifies each combination of the signals present at its input. In general, if a decoder has 'n' input lines, then the number of output lines will be '2n' . Various types of decoder circuits are available for a user; for example, 74139 (a dual 2 to 4 line decoder) and 74138( a 3 to 8 line decoder).

Power Supply: This is the most important sub-circuit which is required to run any schematic design's implementation on a printed circuit board. Pin number 40 of the 8085, namely 'Vcc', requires a steady supply of 5 volts. This can be provided either by designing a regulated power supply(linear or switched) for the circuit or by using a USB input port, which can be connected to a laptop.

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Figure 5: Connection diagram of the 74HC244

Figure 6: A functional diagram of a 2-to-4 line decoder

4.2) Decoding Logic

The very fundamental concept involved in designing the schematic of this project is assigning suitable addresses to the various input and output ports, as well as appropriate memory address ranges for both RAM and ROM. The decoding circuit is generated using basic digital circuits such as latches, buffers and logic gates. The chip enable pin for the buffers and the latches is enabled through a combination of their desired address and the necessary control signal. A block diagram for the same has been shown under the section "Input-Output Interfacing" .

In the schematic, the combination of the address pulse signal and the control signal has been achieved by passing them through a OR gate IC (7432N) , which is a 14 pin DIP package. Based on this, the following port addresses have been generated:

Table1: Port Addresses

Ports A15 A14 A13 A12 A11 A10 A9 A8 Hex AddressPORT1/2A (Floor UP switch) X X X X X 1 1 0 FEHPORT1/2B (Floor DOWN switch) X X X X X 0 1 1 FBHPORT3A (Floor Select button) X X X X X 1 0 1 FDHMOTOR X X X 1 0 X X X F7HSEVEN SEGMENT DISPLAY X X X 0 1 X X X EFH

Peripheral-Mapped I/O has been used in the schematic of the project and so the control signals used are IOR' and IOW'. The "don't-cares" have been taken as logic 1.

4.3) Memory Interfacing

Memory interfacing refers to the interfacing of RAM and EEPROM with the 8085 by allocating appropriate address ranges to both. The RAM used is 62256P, which is a 256 X 8 static ram and is available in a 28 pin DIP package. Static rams are made up of flip-flops and they store the bits as voltages. EEPROM used is AT28c256, which is available as a 28 pin DIP package.

The lower order address bus of the 8085 microprocessor is multiplexed with the 8 bit data bus. The buses are de-multiplexed using a 74HC573 Address Latch, which is enabled using the A15 address line from the microprocessor. When the latch is enabled, i.e. A15 =1 , the RAM is selected and otherwise the ROM is selected. The remaining 15 address lines are used for both RAM and ROM, thus giving a size of 32kB for each.The memory address map for the RAM and ROM are:ROM: 0000H to 7FFFHRAM: 8000H to FFFF

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4.4) Input - Output Interfacing

Decoder

Address Lines

A8 - A15

O R 12

3

Latch or Buffer

IOR' / IOW'

Data Bus

Enable

Peripheral

Address Pulse

The project consists of three input ports, which are interfaced with the microprocessors through 74HC244 tri-state buffers. The three inputs are:

Port 1/2A : This port has 3 slide switches connected to the buffer which correspond to the "MOVE UP" button on the first, second and third floor.

Port 1/2B: This port also has 3 slide switches connected to the buffer which correspond to the "MOVE DOWN" button on the second, third and fourth floor.

Port 3A: This port has 4 push buttons connected to the input buffer. Once the user is inside the elevator, he can push one of the four buttons to indicate the destination floor.

Apart from the input ports, the schematic also has two output ports: one for running the motor and the other through which the seven segment display is connected. The output peripherals are interfaced with the microprocessor by using 74573 latches.

MotorLatch: The L293D is connected to the motor latch and this IC drives the stepper motor in the appropriate direction (clockwise or anti-clockwise) , depending on the data available on the data bus. It is a quadruple current half-H driver designed to provide bidirectional drive currents of up to 600mA at voltages between 4.5V to 36V. The drivers are enabled in pairs, as indicated by its logic diagram shown below.

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Figure 7: General Interfacing Circuit

A sequence of four numbers has to be given on the data bus to drive the motor in the clockwise direction. The sequence is :

09H 05H 06H 0AHTo run the motor in the opposite direction, this sequence has to be given in the reverse order i.e. :

06H 05H 09H 0AHThis has been accomplished in the code by making a look up table for the 4 data bytes.

A ground plane has been given under the L293D IC to which its ground pins are connected. The ground plane has been provided to facilitate heat dissipation in case there is overheating. Also as an extra precaution an aluminium heat sink has been attached using a thermal adhesive on top of the motor driver IC.

SSDLatch: The seven segment display is used to display the current position of the elevator. Each pin of the seven segment display is connected to the latch through a 330Ω resistor, which acts as a current limiting resistor. Its software implementation is carried out using the look table procedure also.

4.5) Frequency of Operation

The crystal connected between pins 1 and 2, X1 and X2, is a 6 MHZ crystal which will give a maximum frequency of operation of 3MHZ.

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Figure 8: Logic Diagram of L293D motor driver. Drivers 1 and 2 are enabled by 1,2EN and drivers 3 and 4 are enabled by 3,4EN. Each output is a totem pole drive output.

5. BOARD LAYOUT

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Figure 9: Board Layout of the Schematic

6. LIST OF COMPONENTS

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QUANTITY

DEVICE PACKAGE PARTS DESCRIPTION

7 10-XX B3F-10XX FLOOR1, FLOOR2, FLOOR3,

FLOOR4, HOLD, RESET, SID

OMRON SWITCH

1 62256P DIL 28-6 RAM MEMORY 1 8085 DIL 40 8085 MICROCOMPUTER/PERIPHERAL

DEVICE2 C-EU025-

025X050C025-

025X050C19 , C20 CAPACITOR, European symbol

19 C-US025-025X050

C025-025X050

C1, C3, C4, C6, C7, C8, C9, C10, C11, C12, C13, C14, C16, C17, C18, C22, C23,

C24, C25

CAPACITOR, American symbol

4 CPOL-EUE2.5-6

E2,5-6 C2, C5, C15, C21 POLARIZED CAPACITOR, European symbol

3 LED3MM LED3MM POWER, RST-LED, SOD

LED

1 M06 06P MOTOR AMP QUICK CONNECTOR4 M10 10P PINOUT1,

PINOUT2, PINOUT3, PINOUT4

AMP QUICK CONNECTOR

1 POWER_CON NEB21R CON DC Power Connector33 R-EU_0204/7 0204/7 R1, R2, R3, R4,

R5, R6, R7, R8, R9, R10, R11,

R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32,

R33

RESISTOR, European symbol

1 XTAL/S QS Q1 CRYSTAL 2 7432N DIL14 OR,OR5 Quad 2-input OR gate 3 74573N DIL20 ADDRESSLATCH,

MOTORLATCH, SSDLATCH

8-bit D latch BUS DRIVER

2 74HC244N DIL20 PORT1/2, PORT3 Octal BUFFER and LINE DRIVER, 3-state

1 74HCT00N DIL14 NAND Quad 2-input NAND gate 1 74HCT00N DIL16 IO/MEM-

CONTROLDual 2-line to 4-line

DECODER/DEMULTIPLEXER1 AT28C256 DIL28 EEPROM IC EEPROM 256KBIT 150NS 1 HD-H101 HDSP-M POSITION LED DISPLAY1 L293D DIL16 DRIVER PUSH-PULL 4 CHANNEL DRIVER

6 SLIDESWITCH-BIG

BIGSWITCH FLOOR1UP, FLOOR2DOWN,

FLOOR2UP, FLOOR3DOWN,

FLOOR3UP, FLOOR4DOWN

SLIDESWITCH

1 USB(POWER) USB(POWER) U$2 USB

7. THE MANUFACTURED PRINTED CIRCUIT BOARD

Below are the images of both the delivered board and the board after the soldering was completed.

7.1) Top Layer

7.2) Bottom Layer

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Figure 10: Top Layer of the Board

Figure 11: Bottom Layer of the Board

7.3) Soldered Board

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Figure 12: Top and bottom layer of the Soldered Board

8. FLOW CHART

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The flow chart shown above was made on a flow chart template for word which is available at www.lucidchart.com/pages/flow-chart-template-for-word

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Figure 13: Flow Chart for the code implementation

http://www.lucidchart.com/pages/flow-chart-template-for-word

9. MODULAR TESTING

9.1) SID-SOD Testing Code

START: RIM ANI 080H JNZ OFF MVI A, 0C0H SIM JMP STARTOFF: MVI A,040H SIM JMP START

9.2) Switch Interfacing and Seven Segment Display Testing Code

START: IN 0FEH CMA ANI 00FH JZ NEXT MVI A, 0F9H OUT 0EFHNEXT: IN 0FDH CMA ANI 00FH JZ NEXTNEXT MVI A, 024H OUT 0EFHNEXTNEXT: IN 0FBH CMA ANI 00FH JZ OFF MVI A, 030H OUT 0EFHOFF: JMP START

9.3) Motor Testing Code

START3: MVI C,064HSTART: MVI A, 005H

OUT 0F7H19

Figure 14: Seven Segment Display and Switch Testing

LXI D,0007Hloop1: MVI B,0FFHloop2: DCR B

JNZ loop2DCX DMOV A,EORA DJNZ loop1

;second MVI A, 006H

OUT 0F7H LXI D,0007Hloop3: MVI B,0FFHloop4: DCR B


;thirdMVI A, 00AHOUT 0F7H



;fourthMVI A, 009HOUT 0F7H


JNZ loop8DCX DMOV A,EORA DJNZ loop7DCR CJNZ START

;DELAY20



;REVERSEMVI C,064H

START2: MVI A, 00AHOUT 0F7H



;second MVI A, 006H



;thirdMVI A, 005HOUT 0F7H



;fourthMVI A, 009H

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JNZ loop16DCX DMOV A,EORA DJNZ loop15DCR CJNZ START2

;delayLXI D,0696H

loop17: MVI B,0FFHloop18: DCR B

JNZ loop18DCX DMOV A,EORA DJNZ loop17JMP START3

9.4) Interrupt CheckLXI SP,0FFFFHMVI A, 00BHSIMEI

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Figure 15: Motor Testing set up

JMP 3000H.ORG 003CH

PUSH HPUSH DPUSH BPUSH PSWMVI A,009HOUT 0EFH

;DELAYLXI D,0696H

loop19: MVI B,0FFHloop20: DCR B

JNZ loop20DCX DMOV A,EORA DJNZ loop19MVI A,0F9HOUT 0EFHPOP PSWPOP BPOP DPOP HEIRET

.ORG 3000HSTART: IN 0FDH

CMAANI 00FHJZ STARTLXI D,0276H

again: DCX DMOV A,EORA DJNZ againIN 0FDH

CMA ANI 00FH JZ START OUT 0EFH JMP START

10. GANTT CHART REVISITED AND COMPARISION WITH ACTUAL RESULTS

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STEP EXPECTED DURATION ACTUAL DURATIONPROPOSAL OF PROJECT 5-10 JAN 2016 5-10 JAN 2016LEARNING 8085 ARCHITECTURE 10 JAN-30 MARCH 2016 10 JAN-30 MARCH 2016LEARNING PROGRAMMING CONCEPTS

20 JAN-24 MARCH 2016 20 JAN-24 MARCH 2016

EAGLE SCHEMATIC 4 FEB-22 FEB 2016 4 FEB-25 MARCH 2016EAGLE BOARD LAYOUT 22 FEB-1 MARCH 2016 22 FEB-1 APRIL 2016ORDERING THE PCB 10 MARCH-30 MARCH 2016 5 APRIL-16 APRIL 2016SOLDERING 1 APRIL - 5 APRIL 2016 21 APRIL - 23 APRILPROGRAMMING 10 MARCH - 5 APRIL 2016 1 APRIL - 30 APRIL 2016TESTING AND CORRECTION 9 APRIL - 30 APRIL 2016 1 MAY - 10 MAY 2016MECHANICAL STRUCTURE - 25 APRIL - 31 MAY 2016

11. CONCLUSION

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Figure 16: The original Gantt Chart made in the IPR report

From the outset, the project was challenging in both hardware and software aspects. It presented us with various hurdles in various stages of its design and implementation. Overcoming those hurdles helped us learn about the subject in depth as it involved considerable research and thinking. Both the schematic and the code had to be modified several times to meet the objectives stated initially. It also emphasised the importance of time management and team work in a collaborative undertaking. The whole endeavour has been a great learning experience and the final implementation of the elevator model satisfactorily fulfils the initially stated objectives.

Code for the Project : http://pastebin.com/WHEnizXe Elevator 8085 Video: http://www.youtube.com/watch?v=hyoC4JZi80g

12. REFERENCES

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http://www.youtube.com/watch?v=hyoC4JZi80g

Ramesh Gaonkar, Microprocessor Architecture, Programming and Applications with the 8085, 6th edition, Penram International Publishing(India) Pvt. Ltd., 2013, ISBN: 978-81-87972-88-4

http://www.ti.com/lit/ds/symlink/l293.pdf https://www.fairchildsemi.com/datasheets/DM/DM74ALS244A.pdf https://en.wikibooks.org/wiki/Digital_Circuits http://6502.org/users/alexis/62256.pdf http://www.nxp.com/documents/data_sheet/74HC_HCT573.pdf http://www.datasheetcatalog.com/datasheets_pdf/7/4/L/S/74LS139.shtml https://en.wikipedia.org/wiki/Intel_8085

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