Demonstration of Subthrehold Swing Smaller Than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack

Giovanni A. Salvatore, Didier Bouvet, Adrian Mihai Ionescu

Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Fédérale de Lausanne, CH-1015 Lausanne, Switzerland

Email: giovanni.salvatore@epfl.ch, didier.bouvet@epfl.ch, adrian.ionescu@epfl.ch Telephone: +41 216934607, Fax: +41 216933640

Abstract

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13mV/decade in Fe-FETs with 40nm P(VDF-TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.

I. INTRODUCTION

The subthreshold swing (SS) of a MOSFET, is defined by:

( ) 10ln)1(log)(log 10 q

kTCC

IV

IV

SSins

s

n

D

S

mS

g

d

g +=∂

∂∂∂

=∂

∂=

ψψ

(1)

where Vg is the gate voltage, ψs is the surface potential, Cs is the semiconductor capacitance, Cins is the gate insulator capacitance and ID the source-drain current, is limited by n-term (ln10xkT/q) due to diffusion of carriers from source to channel and related physics, while the ideal body factor, m, can be as low as 1, to reach the limit of 60mV/decade at room temperature. This minimum subthreshold swing, SS, puts a fundamental lower limit on the operating voltage and the power dissipation of standards FETs. Impact Ionization MOS (IMOS) [1]or Tunnel FET [2] address the possible lowering of the n-factor by new device physical mechanisms (impact ionization or tunneling) while Suspended Gate FET (SG-FET) [3] and negative ferroelectric capacitor [4] have been proposed as solutions to overcome this limit by reducing the m-factor (providing an intrinsic voltage amplification). Recently, it was theoretically demonstrated that thin ferroelectric layer can behave like a step-up voltage transformer that could amplify the gate voltage, thus leading to values of S lower than 60mV/dec [4]. It was predicted that

a ferroelectric layer can introduce a positive feedback on the charge that causes the polarization to increase without limit till the lattice gets “locked in” with a high self generated internal polarization [5]. This is modeled as a negative capacitance [4, 6] that can be stabilized by an in-series positive oxide capacitance. The positive feedback on the charge can be described according to:

)( QVCQ FGgate α+= (2) and the m-factor becomes:

( )1)()(

1)( −−= −−

GeqinsFGeqins

SG VC

VCCVm α (3)

where 1/Cins-eq=1/Cox+1/Cferro(VG), see Fig. 1.

P-Si

N+ N+SiO2

P(VDF-TrFE)Metal(Au)Gate

Source Drain

Body

Cs

Cox

Cferro Cins_eq

ψS

VG

VB

P-Si

N+ N+SiO2

P(VDF-TrFE)Metal(Au)Gate

Source Drain

Body

Cs

Cox

Cferro Cins_eq

ψS

VG

VB

Fig. 1: Investigated ferroelectric transistor, Fe-FET, and equivalent capacitive divider of gate potentials The m-term can be smaller than 1 if αF Cins>1 (significant positive feedback), which is possible if the ferroelectric shows a negative capacitance regime versus gate voltage. However, to date no one was able to experimentally validate the theory of lower than 60mV/decade swings due to negative capacitance in any ferroelectric capacitor stacks. For the first time, we experimentally demonstrate that the 60mV/dec limit can be surpassed by integrating a thin ferroelectric layer into the gate stack of MOSFETs and placing the device in optimal conditions to fulfill operation conditions formulated by Salahuddin [4] in terms of ferroelectric thickness and reduced hysteresis near zero gate voltages. These unique results are achieved with a 40 nm P(VDF-TrFE) on top of 10nm SiO2 gate stack in micrometer size MOSFETS.

II. DEVICE FABRICATION

A simple and low cost fabrication process is used to integrate the polymer in the gate stack of a standard Field Effect Transistor. The substrate is a p-doped Si wafer (Na=1015cm-3) with crystal orientation (100). Device active area and STI insulation are defined by UV-lithography. Source and drain were heavily doped (Nd=1020 cm-3) by POCl3 and a thin film (10nm) of SiO2 was thermally grown on the substrate to reduce the gate stack leakage. The 40nm P(VDF-TrFE) was spin-coated from the Methyl-Ethyl-Ketone solution, and annealed for 10 minutes at 137ºC. A 100nm layer of evaporated gold is used as metal gate contact.

LTO LTO

p-Si

1

n+

n+ LTO 2

Thermal Oxide

LTO

n+

n+

3

n+

n+ LTO

Thermal Oxide

40nm P(VDF-TrFE)

4

n+

n+ LTO

Thermal Oxide

40nm P(VDF-TrFE)

5

Au Gate

Fig. 2: Fabrication process of Fe-FET with P(VDF-TrFE)/SiO2 gate stack: 1) STI (Shallow Trench Isolation): lithography to define the active region, LTO deposition and CMP step to planarize the structure; 2) Doping: drain and source regions are doped by POCl3; 3) Gate oxide: a thin layer (10nm) of thermal SiO2 is grown; 4) PVDF-TrFE deposition: the polymer is spin-coated and baked afterwards at 137°C for 10 minutes. The final thickness is about 40nm (confirmed by AFM measurements); 5) Gate electrode: Gold (Au) is evaporated and patterned through UV lithography and wet etching.

DRAIN SOURCE

GATE

L

W

Fig. 3: Optical image of fabricated Fe-FET; different transistors are visible. The zoom shows a large Fe-FET with L=W=50μm, for which we report experimental results.

III. EXPERIMENTAL RESULTS

A. I-V Measurements

Typical drain and source current characteristics, Id-Vg and Is-Vg of a fabricated Fe-FET have been systematically measured. Fig. 4 shows the behavior of the drain and source currents of the Fe-FET when the gate voltage is swept from -

1V to 8V. The polarization of the 40nm P(VDF-TrFE) ferroelectric layer results in a shift of the threshold voltage and hence in a hysteresis in the Id-Vg curve. Fig. 4 shows the Id-Vg characteristics at small drain voltages and a typical hysteresis loop. In Fig. 5, the hysteresis dependence on the upper value of gate voltage sweep is depicted; the hysteresis is increased by increasing the upper limit of gate voltage. An abrupt off-on subthreshold transition with reduced hysteresis requires a low drain voltage and a small sweep of Vg (up to few volts). Higher Vg sweeps are useful for 1T Fe-FET memory applications (Fig. 5), [7].

0 2 4 6 810-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

Dra

in C

urre

nt, I

d [A

]

Gate Voltage, Vg [V]

Vd

Vd=5, 10, 50, 100, 200mV

Vd=2

00mV

Fig. 4: Id-Vg with drain voltage as a parameter. The gate voltage is swept from -0.5V to 8V and the transistor body is connected to ground (Vbulk=0V). The hysteresis window is reported only for Vd=200mV and is due to the polarization of the ferroelectric layer; the hysteresis is about 1V and the Ion/Ioff ratio is about 106 with typical leakage current of the order of few 10-13 to 10-12 A.

-5 0 5 10 1510-12

10-11

10-10

10-9

10-8

10-7

10-6

Dra

in c

urre

nt, I

d [A

]

Gate voltage, Vg (V) Fig. 5: Multiple Id-Vg hysteretic curves measured by sweeping gate voltage up to 7V, 8V, 9V, 10V, 12V and 15V and then down to-7V, for the fabricated Fe-FET with L=W=10μm. A larger hysteresis is obtained for larger sweep, which is useful for ferroelectric 1T-memory application. In contrast, this work focuses on the very abrupt switch behavior obtained by limiting the hysteresis and sweeping-up Vg to few volts (also, a very low drain voltage for lowest leakage floor is applied in our experiments). In most of the fabricated devices the Ioff leakage (defined as Is, Id for Vg=0V) current is less than pA. The Ioff floor can limit the experimental estimation of the physical value of the subthreshold swing at low currents, calculated as

SS(mV/decade)= ΔVg/Δlog(I). The swing of the source current, Is, which presents lower leakage floor than Id for a typical Fe-FET is numerically evaluated in Fig. 6.

0 1 2 3 410-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

Drain Current Source Current

Id, I

s [A

]

Gate Voltage, Vg [V]

0.75 1.00 1.25 1.50 1.7510-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

60m

V/de

c

SS(mV/dec)

Gate Voltage, Vg [V]

Sou

rce

Cur

rent

,Is [A

]

60mV/declimit

13m

V/de

c

40

80

120

160

200 Subthreshold Sw

ing, SS (m

V/dec)

1.16 1.18 1.20 1.22 1.24-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

SS=57mV/dec

log(

-Is)

Gate Voltage, Vg [V]

SS=1

3mV/

dec

first 5 points slope=13mV/declast 10 points slope=57mV/dec

Fig. 6: Id-Vg and Is-Vg characteristics at Vdrain=10mV, Vbulk=-500mV, Vsource=0V for a Fe-FET with L=W=50μm. a) Drain current and Source current are recorded with a very small Vg-step=5mV at room temperature to evaluate by numerical derivation of data the subthreshold swing. b) Slope analysis performed on the source current. The ‘star’ points show the slope for each measured current value. The curve exhibits a bias-dependent swing that, at low Vg, is steeper that the 60mV/dec limit (“stars” below the “60mV/dec limit” dashed line). The first 5 points of the curve have been interpolated giving a swing of 13mV/dec (‘gray’ line in the plot). c) Detailed linear fitting using 15 points of the source current curve. The interpolation of the first 5 points give a slope of 13mV/dec, while the last 10 points give a slope of 57mV/dec, both smaller than the theoretical limit of 60mv/decade at room temperature.

It is worth noting that the low source bias offers lower Ioff currents, which enables the evaluation of the subthreshold swing at lower current values, not influenced by the bias-dependent junction leakage. Otherwise Is=Id in all regimes, as expected. The SS is calculated for each point of the measured Is-Vg characteristic. The first ~10 points of the curve exhibit a slope steeper than the 60mV/dec limit (Figs. 6b and 6c). The linear interpolation, performed on the first 5 points, give a fitting swing of 13mV/dec and the last 10 a slope of 57mV/decade (Fig. 6c), which confirms the prediction that a thin ferroelectric film with low hysteresis at low fields can provide the conditions discussed in eq. (3) for a m<1. Fig. 7 confirms SS <60mV/decade in drain current measured on one of the Fe-FEts with lowest leakage current.

-0.5 0.0 0.5 1.0 1.5 2.010-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

SS (mV/dec)

Gate Voltage, Vg [V]

Dra

in C

urre

nt, I

d [A

]

60mV/dec limit

points below the limit

0

20

40

60

80

100

120 Subthreshold S

wing (m

V/dec)

Fig. 7: Drain current characteristics (circles), ID-VG, and corresponding subthreshold swing, SS, data (stars) of a Fe-FET with very low leakage, at Vd=5mV. The plot demonstrates abruptness of the off-on transition at low Vg with few of the SS points below the 60mV/decade theoretical limit.

B. C-V Measurements In order to validate the hypothesis of a negative ferroelectric

capacitance that explains such low values of SS, the CGB capacitance of the P(VDF-TrFE)/SiO2/Si gate stack has been measured by keeping the drain, source and bulk grounded.

0 1 2 3 4 5

-2.0x10-13

0.0

2.0x10-13

4.0x10-13

6.0x10-13

8.0x10-13

Gate Voltage, Vg [V]

Gat

e C

apac

itnce

, CG

B [F

]

n+

B

G

n+ n+

AuFerroSiO2

CGB<010-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

Source C

urrent, Is [A]

Fig. 8: Gate capacitance of P(VDF-TrFE)/SiO2/Si stack, CGB-Vg, characteristics at room temperature for fabricated Fe-FET. The gate voltage is swept-up in the range -1V to 5V and then back -1V and the source, drain and bulk are grounded. The measurement is performed with a HP4156C and a careful compensation for cables parasitic capacitance (this is done by lifting the probes off). The plot shows also the source current measured on the same device at Vd=4mV. This experiment confirms that the maximum subthreshold swing corresponds to the region of the negative capacitance.

b)

c)

a)

Fig.8 demonstrates for the first time that in thin ferroelectric/SiO2 dielectric stack, CGB has a MOSFET like behavior but, in the subthreshold region negative capacitances values are indeed observed. We have performed the same measurement on the gate capacitance of an identical standard MOSFET fabricated with the very same process (Fig. 9) and calculated the capacitance of the ferroelectric layer under the hypothesis that the oxide, ferroelectric and semiconductor capacitances are connected in-series.

-2 -1 0 1 2 3

4x10-12

5x10-12

6x10-12

7x10-12

8x10-12

Gate Voltage, Vg [V]

Gat

e C

apac

itanc

e, C

GB

[F]

10-7

10-6

Drain C

urrent, Id [A]

Fig. 9: Capacitance measurement similar to the one reported in Fig.8, performed on a identical reference transistor (identical fabrication process) without ferroelectric layer, only including an identical SiO2/Si gate stack. A typical MOSFET C-V behavior, with positive capacitances values, is observed, with the clear identification of depletion, weak inversion and strong inversion regions and plateau values corresponding to the Cox given by the thermal oxide.

Fig. 10 shows that our data suggests the CFERRO is responsible for the negative values of the total capacitance as well as for the small hysteresis due to the polarization of the ferroelectric layer.

0 1 2 3

0

2x10-12

4x10-12

6x10-12

8x10-12

IIII Ceq

CMOS CFERRO

Gate Voltage, Vg [V]

Ceq

, CM

OS [F

]

II -8.0x10-13

0.0

8.0x10-13

1.6x10-12

2.4x10-12

CFE

RR

O [F]

Fig. 10: Comparison of the reference MOSFET capacitance, CMOS, without ferroelectric co-polymer, and the Fe-FET capacitance, Ceq, on a identical size device. The capacitance of the ferroelectric layer, CFERRO, is numerically calculated by subtracting 1/CMOS from 1/Ceq, under the hypothesis that: 1/Ceq=1/CMOS+1/CFERRO. CMOS capacitance includes the oxide and the depletion and inversion capacitances. It is observed that Ceq becomes negative in the range 0.5<Vg<1.5, when the calculation provides negative values for CFERRO, region that corresponds in which the lowest subthreshold swing values are measured. Moreover, as expected, the small hysteresis visible in CFERRO and Ceq, is not visible in CMOS; thus this is exclusively attributed to the polarization of the ferroelectric layer.

C. I-V Temperature Dependence Measurements Complementarily, the I-Vg temperature dependence has been evaluated (Fig. 11); for temperature larger that 55°C the very low values of the SS are obscured by the increased leakage current.

0 1 2 3 410-1410-1310-1210-1110-1010-910-810-710-6

25°C 35°C 45°C 55°CS

ourc

e C

urre

nt, I

s [A

]

Gate Voltage, Vg [V] Fig. 11: Influence of temperature on the Is-Vg characteristics of the Fe-FET, measured for Vd=4mV. For temperature values larger than 55°C, the low subthreshold swing values at low VG are obscured by the increased junction leakage current, as expected. However, in the subthreshold region for T=25°C, 35°C and 45°C, the subthreshold swing, SS, has values that are below the (kT/q)ln10 limit.

IV. CONCLUSION

In this work we have experimentally demonstrated, for the first time, by integrating a ferroelectric layer into the gate stack of a standard FET, the theoretical switch slope of 60mV/dec can be surpassed. We have measured a 13mV/dec subthreshold swing at room temperature in a L=W=50μm FET device. The steep slope is due to negative ferroelectric capacitance in Fe-FETs with 40nm P(VDF-TrFE)/SiO2 gate stack.

ACKNOWLEDGEMENT

Dr. Igor Stolitchnov and Prof. Nava Setter are acknowledged for advice in the preparation of the PVDF material. We would like to thank Donato Acquaviva and Joseph Guzzardi for their technical collaboration. This work has been partially supported by the IST FP6 MINAMI integrated project and the Swiss Competence Centre for Materials Science and Technology (CCMX)

V. REFERENCES

[1] K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, IEDM Digest, pp. 289- 292, 2002.

[2] K. Boucart, A. Ionescu., IEEE Trans. Elec. Dev. 54(7), pp. 1725-1733, 2007.

[3] N. Abelé, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. M. Ionescu, IEDM Digest, 479-481, 2005

[4] S. Salahuddin, S. Datta, Nano Letters, Vol. 8, pp. 405-410, 2008 [5] R. Feynman, Lecture on Physics, Add.-Wesley, pp. 11-8, 1964. [6] A. M. Bratkovsky, A. P. Levanyuk, Appl. Phys. Lett. 89, 253108, 2006. [7] G. Salvatore et al., Prof. of ESSDERC 2008, pp. 162-165, 2008.