IEEE TRANSACTIONS ON ELECTRON DEVICES 1

Dependence of Device Structures on LatchupImmunity in a High-Voltage 40-V CMOSProcess With Drain-Extended MOSFETs

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Sheng-Fu Hsu, Member, IEEE, and Ming-Dou Ker, Senior Member, IEEE4

Abstract—The dependence of device structures on latchup im-5munity in a 0.25-µm high-voltage (HV) 40-V CMOS process6with drain-extended MOS (DEMOS) transistors has been verified7with silicon test chips and investigated with device simulation.8Layout parameters such as anode-to-cathode spacing and guard9ring width are also investigated to find their impacts on latchup10immunity. It was demonstrated that the drain-extended NMOS11with a specific isolated device structure can greatly enhance the12latchup immunity. The proposed test structures and simulation13methodologies can be applied to extract safe and compact design14rule for latchup prevention of DEMOS transistors in HV CMOS15process.16

Index Terms—Drain-extended MOS (DEMOS), high-voltage17(HV) CMOS process, latchup, silicon-controlled rectifier (SCR),18transmission line pulsing (TLP).19

I. INTRODUCTION20

H IGH-VOLTAGE(HV) drain-extended MOS (DEMOS)21

transistors are increasingly important in modern inte-22

grated circuit (IC) design because DEMOS can provide a cost-23

effective solution to integrate both low-voltage (LV) and HV24

devices into a single silicon chip [1]–[7]. DEMOS transistors25

have been widely used in HV ICs or power ICs such as driver26

circuits, telecommunication, power management switches,27

motor control systems, automotive electronics, medical appli-28

cations, etc. Compared with the vertical HV MOSFET struc-29

tures such as diffused MOSFET (DMOS) [3], [4] or vertical30

MOSFET (VMOS) [3], [4], which cannot be integrated with31

LV devices, DEMOS transistors have the primary advantage of32

easily being implemented in a standard LV CMOS process. In33

addition, DEMOS transistors can provide advantages such as34

high driving current and high junction breakdown voltage. As35

a result, DEMOS transistors can offer IC (system) designers a36

better design flexibility as well as cost-effective solution, hence37

leading DEMOS transistors to become a significant topic in38

system-on-chip design.39

Manuscript received April 13, 2006; revised November 27, 2006. This workwas supported by Vanguard International Semiconductor Corporation, Taiwan,R.O.C. The review of this paper was arranged by Editor M. A. Shibib.

S.-F. Hsu was with the Nanoelectronics and Gigascale Systems Labora-tory, Institute of Electronics, National Chiao Tung University, Hsinchu 300,Taiwan, R.O.C. He is now with Taiwan Semiconductor Manufacturing Com-pany, Hsinchu 300, Taiwan, R.O.C.

M.-D. Ker is with the Nanoelectronics and Gigascale Systems Laboratory,Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan,R.O.C. (e-mail: mdker@ieee.org).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2007.892013

When DEMOS transistors are used for products that require 40

high reliability demand such as liquid crystal display (LCD) 41

driver, automotive electronics, and medical applications, the 42

detailed understanding of their reliability issues is necessary. 43

In addition to the earlier researches of DEMOS transistors 44

under hot-carrier [5], [6] and electrostatic discharge (ESD) [7] 45

stresses, latchup characteristic in DEMOS transistors is also 46

very critical and should be investigated. When DEMOS transis- 47

tors are used in HV IC design, one tough challenge on their reli- 48

ability issues is to eliminate the possible occurrence of latchup 49

[8]–[12]. However, due to an ultrahigh circuit operating voltage 50

in HV CMOS ICs, it is rather difficult to achieve the latchup- 51

free purpose by raising the latchup holding voltage to exceed 52

a high circuit operating voltage. In addition, latchup in HV 53

CMOS ICs usually consumes much power in comparison with 54

that in LV CMOS ICs [3]. Once latchup occurs, HV CMOS 55

ICs are always inevitable to be damaged by latchup-generated 56

high power. Thus, how to improve the latchup immunity in 57

HV ICs is indeed a crucial reliability issue. Particular cares, 58

such as DEMOS device structures and their layout styles, must 59

be taken for latchup prevention. However, compared with the 60

standard LV CMOS technology where many detailed process 61

[13]–[16], layout [17], [18], and circuit [19] solutions have been 62

proposed for latchup prevention, so far, there are no related 63

researches to investigate the dependence of DEMOS device 64

structures and their layout styles on latchup immunity in HV 65

CMOS technology. 66

In this paper, HV latchup characteristics under JEDEC 67

latchup current test are investigated. Two different latchup 68

sensors, namely 1) HV silicon-controlled rectifier (SCR) and 69

2) LV SCR, are used to simulate the internal circuits for 70

different voltage applications (2.5 V for LV SCR and 40 V 71

for HV SCR) in real HV CMOS circuitry. In addition, the 72

dependence of DEMOS device structures on latchup immunity 73

is also investigated under three different HV latchup test struc- 74

tures [20]. These three latchup test structures can simulate each 75

possible case of the parasitic SCR with different DEMOS de- 76

vice structures, including isolated, nonisolated, symmetric, and 77

asymmetric device structures. In addition, layout parameters 78

such as anode-to-cathode spacing and guard ring width are also 79

investigated to find their impacts on latchup immunity. In order 80

to avoid the HV latchup test structures being damaged so easily 81

under the long-period (microseconds to milliseconds) latchup 82

overstress of the continuous-type curve tracer, the transmission 83

line pulsing (TLP) [21] generator with pulsewidth of 100 ns 84

and limited energy is used instead in this paper for latchup 85

0018-9383/$25.00 © 2007 IEEE

2 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 1. Device cross-sectional views. (a) Isolated n-DEMOS. (b) Nonisolatedn-DEMOS.

current–voltage (I–V ) measurements. All the TLP-measured86

latchup I–V characteristics on different HV latchup test struc-87

tures can be qualitatively and quantitatively verified by the 2-D88

device simulation. All the silicon test chips are fabricated in a89

0.25-µm 40-V CMOS technology.90

II. DEVICE STRUCTURES OF DEMOS TRANSISTORS91

The devices studied in this paper are implemented in a92

standard 0.25-µm 2.5-V/5-V CMOS technology. Both HV and93

LV MOSFETs are built on a high-resistance P-epitaxial (P-epi.)94

layer above the P-substrate. The device structures of DEMOS95

transistors can be classified into two major parts, namely96

1) isolated or nonisolated device structures and 2) symmetric97

or asymmetric device structures.98

A. Isolated and Nonisolated Device Structures99

The device cross-sectional views of the isolated and non-100

isolated drain-extended NMOS (n-DEMOS) are depicted in101

Fig. 1(a) and (b), respectively. An N-well region enclosing the102

N+ drain with some overlap of polygate is used as the drain drift103

region. This drain drift region (N-well) can sustain high voltage104

(+40 V) on drain terminal by increasing the drain junction105

breakdown voltage. In addition, it can lower the high electric106

field in channel region to suppress the short-channel effect [2].107

The shallow trench isolation (STI) between the gate oxide and108

N+ drain is used to lower the electric field in gate oxide far109

below the critical value of oxide breakdown (106 V · cm). Thus,110

the gate-oxide breakdown near the drain side can be efficiently111

eliminated.112

The term “isolated” means that there is an additional N+113

buried layer (NBL) beneath the N-well (P-well) region in the114

device active region. Thus, the NBL can combine its peripheral115

N-well regions to form the drain isolation region. The purpose116

of the drain isolation region is used to help isolate the device117

Fig. 2. Device cross-sectional view of the isolated p-DEMOS.

channel, source, and its body (P-well) region from the latchup- 118

induced noise current outside the active region, as shown in 119

Fig. 1(a). In contrast with the isolated n-DEMOS, there is no 120

NBL in the nonisolated n-DEMOS. Instead, the whole device is 121

fabricated on a thin P-epi. layer above the P-substrate, as shown 122

in Fig. 1(b). 123

The device cross-sectional view of the isolated drain- 124

extended PMOS (p-DEMOS) is depicted in Fig. 2. The isolation 125

region consists of the NBL and its aforementioned peripheral 126

N-well regions. If there is no isolation region in p-DEMOS, 127

leakage current path (short-circuit path) can exist when 128

p-DEMOS is turned on, as shown in Fig. 3(a). Holes can 129

flow from the P+ source (+40 V) of p-DEMOS, through the 130

turn-on channel and P-epi. layer, and finally flow into the 131

adjacent P+ pickups (0 V). Thus, the isolated device structure is 132

necessary for p-DEMOS to avoid such leakage path, as shown 133

in Fig. 3(b). Similar to n-DEMOS, a P-well region enclosing 134

the P+ drain is used as the drain drift region to sustain high 135

voltage on drain terminal. The STI between the gate oxide and 136

P+ drain is used to eliminate the gate-oxide breakdown near the 137

drain side. 138

B. Symmetric and Asymmetric Device Structures 139

The device cross-sectional views of the nonisolated asym- 140

metric and nonisolated symmetric n-DEMOS are depicted in 141

Figs. 1(b) and 4, respectively. The term “symmetric” means 142

that both drain and source N+ diffusions are enclosed with the 143

N-well regions, which are used as the drain and source drift re- 144

gions to sustain high operating voltage, as shown in Fig. 4. For 145

asymmetric n-DEMOS, however, such N-well region to sustain 146

high voltage is only implemented on the drain side, as shown 147

in Fig. 1(b). With a better design flexibility for IC designers, 148

symmetric device has the advantage of HV sustainability on 149

both drain and source sides. However, it must suffer larger 150

turn-on resistance and larger layout area than the asymmetric 151

device. 152

III. HV LATCHUP CHARACTERISTICS 153

For very large scale integration design in HV CMOS process, 154

foundries usually support latchup design rules or guidelines 155

for latchup prevention. For example, the minimum spacing be- 156

tween NMOS and PMOS (maximum spacing from the substrate 157

or well pickups to the device active region) is usually well 158

defined to prevent the occurrence of latchup for I/O (internal) 159

circuits. However, foundries usually do not support the explicit 160

HSU AND KER: DEVICE STRUCTURE DEPENDENCE ON LATCHUP IMMUNITY 3

Fig. 3. (a) p-DEMOS without the NBL. (b) p-DEMOS with the NBL. p-DEMOS with isolated device structure is necessary to avoid short-circuit leakage path.

Fig. 4. Device cross-sectional view of the nonisolated symmetric n-DEMOS.

design guidelines to prevent latchup on internal circuits due to161

the noise current injection from I/O pins. In such latchup issue,162

one dominant layout rule is the minimum spacing between the163

I/O and internal circuits. If the spacing is not long enough, the164

noise current injecting into the I/O pins can easily trigger on165

latchup in its adjacent internal circuits. However, a too large166

spacing may lead to a larger chip area and fail to achieve the167

cost-down purpose, especially in high-pin-count ICs.168

The JEDEC latchup current test [22] is widely adopted169

in IC industry to evaluate this latchup issue. In this test, a170

current pulse is injected into the I/O pins to see if latchup171

occurs in device under test (DUT). For LV CMOS circuits,172

most failure returns [18] reveal that latchup occurs in internal173

circuits rather than in I/O circuits, because the design rules174

for latchup prevention are often well defined in I/O circuits175

but not in between I/O and internal circuits. In addition, since176

the internal circuits are always highly integrated and hard to177

become latchup free (holding voltage larger than the normal178

circuit operating voltage), internal circuits are rather sensitive179

to latchup in comparison with I/O circuits. For HV CMOS180

circuits, however, few researches have been done on such 181

latchup issue. Thus, it is significant to investigate the HV 182

latchup characteristics under latchup current test. 183

In this paper, the relations between the latchup immunity of 184

internal circuits (i.e., minimum trigger current injected from 185

I/O pins to initiate latchup in internal circuits) and the layout 186

spacing from I/O cells to internal circuits are investigated in 187

HV CMOS process. Two different latchup sensors, namely 188

1) HV SCR and 2) LV SCR, are used to simulate the internal 189

circuits for different voltage applications (2.5 V/40 V) in real 190

HV CMOS circuitry, e.g., LCD driver circuits. All the test chips 191

are fabricated in a 0.25-µm 2.5-V/40-V CMOS technology. 192

A. Test Structure 193

In HV CMOS ICs, latchup can be triggered on due to the 194

inherent existence of the parasitic SCR between n-DEMOS and 195

p-DEMOS. The device cross-sectional view of the inverter 196

logic circuit, which consists of a nonisolated asymmetric 197

n-DEMOS and an isolated asymmetric p-DEMOS, is shown 198

in Fig. 5. The parasitic SCR composed of two cross-coupled 199

bipolar junction transistors (BJTs) is also depicted in Fig. 5. 200

Such an inverter circuit is the basic logic component in CMOS 201

ICs. It is well known that the parasitic SCR within it, however, 202

is the origin of latchup [13]. Once latchup is triggered on by 203

large enough substrate or well current, a positive feedback 204

mechanism will lead to a large current conducting through 205

a low-impedance path from VDD (source of p-DEMOS) to 206

ground (GND; source of n-DEMOS). As a result, HV CMOS 207

ICs will malfunction or even be burned out due to the latchup- 208

generated high power. 209

4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 5. Device cross-sectional view of the inverter logic circuit consisting of a nonisolated asymmetric n-DEMOS and an isolated asymmetric p-DEMOS.

Fig. 6. Proposed test structure to investigate the relations between latchupimmunity of internal circuits and the layout spacing from I/O cells to internalcircuits.

The proposed test structure to investigate the HV latchup210

characteristics under latchup current test is shown in Fig. 6 [18].211

This structure can be used to investigate the relations between212

latchup immunity of internal circuits and the layout spacing213

from I/O cells to internal circuits. Here, the inserted P+/N+214

guard rings have a fixed width of 5 µm. By injecting the latchup215

trigger current into the I/O pins, the internal circuits (HV or216

LV SCR) can be triggered on to a latchup state. Meanwhile,217

large current will conduct through a low-impedance path from218

VDD to GND within internal circuits, thus leading VDD of219

HV (LV) SCR to be pulled down to a low latchup holding220

voltage.221

The device cross-sectional view of the proposed test structure222

is shown in Fig. 7. The trigger current path to initiate latchup223

in HV SCR is also depicted. Each HV I/O cell is composed224

of nonisolated asymmetric n-DEMOS and isolated asymmetric225

p-DEMOS. To avoid latchup occurring in I/O circuits rather226

than in internal circuits, each HV I/O cell has a large anode-to-227

cathode spacing of 50 µm and is equipped with double guard228

rings to enhance its latchup immunity. The layout top view of 229

Fig. 7 with HV (LV) SCR internal circuits is shown in Fig. 8(a) 230

and (b). With the proposed latchup test structures, the safe and 231

compact latchup design guidelines between HV I/O and HV 232

(LV) internal circuits can be extracted. 233

B. Experimental Results 234

For internal circuits of HV and LV SCR, the relations be- 235

tween the minimum negative latchup trigger current on I/O pins 236

and the layout spacing from I/O cells to internal circuits are 237

shown in Fig. 9. For LV SCR, the minimum latchup trigger 238

current increases with spacing from I/O cells to internal circuits, 239

because a larger spacing can reduce more injection current 240

that reaches the internal circuits through recombination. The 241

spacing from I/O cells to internal circuits must be larger than 242

110 µm to pass the JEDEC latchup criterion (> ±100 mA). 243

The experimental results are consistent with those in LV CMOS 244

process [18]. 245

For HV SCR, however, the minimum latchup trigger current 246

is fixed at −150 mA and independent of the spacing from 247

I/O cells to internal circuits. The same latchup trigger current 248

dependence can be also observed under positive trigger current 249

test. Failure analyses demonstrated that latchup occurs in HV 250

I/O cells rather than in HV internal circuits (HV SCR), even for 251

a very short distance of 50 µm from the I/O cells to internal 252

circuits. In LV CMOS process, it is easy to design the latchup- 253

free I/O cells by adding double guard rings or enlarging the 254

distance between I/O PMOS and NMOS. However, it is very 255

difficult to design the latchup-free HV I/O cells because of 256

its high operating voltage. The experimental results show that 257

the HV I/O cells are dominant to the latchup immunity in HV 258

chips. It is different with the LV CMOS process where core 259

circuits are the latchup dominant factors. Although HV core 260

circuits can sustain higher injection current (< −150 mA) with- 261

out latchup occurrence than LV core circuits (< −110 mA), 262

the HV latchup immunity is limited to only −150 mA and 263

cannot be enhanced anymore by enlarging the spacing from 264

I/O to internal circuits. Thus, the dependences of HV device 265

structures on latchup immunity should be investigated to further 266

improve the latchup immunity in HV process. With the latchup- 267

robust HV device structures, the area-efficient HV I/O cells can 268

be designed without enlarging the distance between HV I/O 269

PMOS and NMOS. 270

HSU AND KER: DEVICE STRUCTURE DEPENDENCE ON LATCHUP IMMUNITY 5

Fig. 7. Device cross-sectional view of the proposed test structure. The trigger current path to initiate latchup in HV SCR is also depicted.

Fig. 8. Layout top views of test structure. (a) Internal circuits with HV SCR.(b) Internal circuits with LV SCR.

IV. DEPENDENCE OF DEMOS DEVICE STRUCTURES ON271

LATCHUP IMMUNITY272

A. Test Structure273

Three different HV SCR test structures (test structures A,274

B, and C) are used to investigate the dependence of DEMOS275

device structures on latchup immunity. These three latchup test276

structures can simulate each possible case of the parasitic SCR277

in HV CMOS ICs with different DEMOS device structures,278

including asymmetric, symmetric, nonisolated, and isolated279

device structures. Table I summarizes the device structures of280

DEMOS transistors in test structures A, B, and C. In addition,281

layout parameters such as anode-to-cathode spacing and guard282

ring width are also investigated to find their impacts on latchup283

Fig. 9. For internal circuits with HV or LV SCR, the relations between theminimum negative latchup trigger current on I/O pins and the layout spacingfrom I/O cells to internal circuits.

TABLE ISUMMARY OF THE DEVICE STRUCTURES OF DEMOS TRANSISTORS IN

LATCHUP TEST STRUCTURES A, B, AND C

immunity. All the latchup test structures are fabricated in a 284

0.25-µm 40-V CMOS process. 285

The device cross-sectional views and their layout top views 286

of test structures A, B, and C are depicted in Figs. 10–12, 287

respectively. The P+ anode (N+ cathode) is used to simulate 288

the P+ source of p-DEMOS (N+ source of n-DEMOS). Once 289

latchup occurs, huge current will conduct from the P+ anode 290

to the N+ cathode. To gain a better latchup immunity, both 291

anode and cathode in test structures A, B, and C are surrounded 292

by their base guard rings for complying with foundry’s design 293

6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 10. (a) Device cross-sectional view of test structure A. (b) Layout topview of test structure A. Test structure A is used to simulate the parasitic SCRresulting from the nonisolated asymmetric n-DEMOS and isolated asymmetricp-DEMOS.

rules, as shown in Figs. 10(b), 11(b), and 12(b). In addition,294

the spacing from anode (cathode) to its surrounding guard ring295

in each test structure is kept at its minimum allowable distance296

according to foundry’s design rules.297

Test structure A is used to simulate the parasitic SCR298

resulting from the nonisolated asymmetric n-DEMOS and299

isolated asymmetric p-DEMOS. Due to the “asymmetric”300

device structures in both p- and n-DEMOS, there is no P-well301

(N-well) region enclosing the P+ anode (N+ cathode) for302

source-extended region. In addition, due to the “isolated”303

device structure in the p-DEMOS, the P+ anode and N+304

guard rings are fabricated on the NBL above the P-substrate.305

However, because of the “nonisolated” device structure in the306

n-DEMOS, the N+ cathode and P+ guard rings are fabricated307

on the P-epi. layer instead of NBL. Test structure B is used308

to simulate the parasitic SCR resulting from the nonisolated309

symmetric n-DEMOS and isolated symmetric p-DEMOS. Due310

to the “symmetric” device structures in both p- and n-DEMOS,311

the P+ anode and N+ cathode are enclosed with the P-well and312

N-well regions, respectively, for the source-extended regions.313

Test structure C is used to simulate the parasitic SCR result-314

ing from the isolated asymmetric p-DEMOS and n-DEMOS.315

Compared with test structures A and B where the n-DEMOS316

has the “nonisolated” device structure, the n-DEMOS in test317

Fig. 11. (a) Device cross-sectional view of test structure B. (b) Layout topview of test structure B. Test structure B is used to simulate the parasitic SCRresulting from the nonisolated symmetric n-DEMOS and isolated symmetricp-DEMOS.

structure C has the “isolated” device structure. Thus, the 318

N+ cathode in test structure C is enclosed (i.e., isolated) by the 319

NBL and its peripheral N-well regions but is not only fabricated 320

on the P-epi. layer as in test structures A and B. 321

B. Experimental Results 322

To investigate the latchup characteristics of DEMOS transis- 323

tors in HV CMOS ICs, the latchup I–V curves are measured 324

in three different latchup test structures A, B, and C, with 325

various layout parameters. In these test structures, P+ anode 326

and N+ guard rings are connected to VDD, whereas N+ cathode 327

and P+ guard rings are connected to GND. By extracting the 328

two dominant parameters of the latchup robustness, namely 329

1) latchup trigger voltage and 2) latchup holding voltage, from 330

the measured latchup I–V curves, the dependence of DEMOS 331

device structures and their layout styles on latchup immunity 332

can be well evaluated. Latchup trigger voltage represents the 333

minimum applied voltage that can “trigger” the DUT into a 334

latchup state. Latchup holding voltage represents the minimum 335

applied voltage needed for the DUT to “hold” a latchup state. 336

Thus, a higher latchup trigger or holding voltage means a better 337

latchup robustness for the DUT. All the latchup measurements 338

are performed at the room temperature of 25 ◦C. 339

HSU AND KER: DEVICE STRUCTURE DEPENDENCE ON LATCHUP IMMUNITY 7

Fig. 12. (a) Device cross-sectional view of test structure C. (b) Layout top view of test structure C. Test structure C is used to simulate the parasitic SCR resultingfrom the isolated asymmetric n-DEMOS and p-DEMOS.

Compared with the LV devices, HV devices usually require a340

much larger minimum allowable spacing between the adjacent341

n-DEMOS and p-DEMOS (i.e., much larger anode-to-cathode342

spacing) because of the ultrahigh circuit operating voltage.343

According to foundry’s design rule, guard ring structures are344

also forced for each DEMOS transistor to enhance its latchup345

robustness. As a result, latchup I–V curves in HV CMOS346

ICs usually have a much higher holding voltage and holding347

current (i.e., much higher latchup holding power) than those in348

LV CMOS ICs. Due to such high latchup power in HV ICs,349

when the continuous-type curve tracer (e.g., Tektronix 370 A)350

is used to measure the latchup I–V curves in HV ICs, HV351

devices are usually damaged before the latchup I–V curves352

are certainly observed or extracted. In order to avoid the HV353

devices being damaged so easily under the long-period (mi-354

croseconds to milliseconds) latchup overstress of continuous-355

type curve tracer, the TLP generator [21] with a pulsewidth356

(rise time) of 100 ns (∼10 ns) is used instead in this paper to357

measure latchup I–V curves of HV latchup test structures. Such358

100-ns TLP generator is commonly used for ESD charac-359

terization. Compared with the general continuous-type curve360

tracer whose stress time approximates to the microsecond to361

millisecond range, the TLP generator has much shorter stress362

time of 100 ns and limited energy. Thus, by using the TLP 363

generator for latchup I–V characterizations, the HV devices 364

will not be damaged so easily under a latchup state; thus, the 365

latchup trigger and holding voltages can be certainly extracted. 366

1) Relationships Between Latchup Trigger (Holding) Volt- 367

age and Anode-to-Cathode Spacing: The relationships be- 368

tween TLP-measured latchup trigger (holding) voltage and 369

anode-to-cathode spacing for test structures A, B, and C are 370

shown in Fig. 13. Obviously, test structure C (considering the 371

parasitic SCR resulting from isolated asymmetric n-DEMOS 372

and p-DEMOS) has the best latchup immunity due to its highest 373

latchup trigger and holding voltages. For example, latchup 374

trigger voltage (holding voltage) can be as high as 97 V (48 V) 375

for test structure C, although the anode-to-cathode spacing is 376

only as short as 27.5 µm, as its TLP-measured latchup I–V 377

curve shown in Fig. 14. Because of a high latchup holding 378

voltage of 48 V, which is higher than 40 V of the normal circuit 379

operating voltage, test structure C can be latchup free. However, 380

latchup trigger voltage (holding voltage) can be only enhanced 381

up to 71 V (36 V) for test structure A and up to 70 V (37 V) 382

for test structure B, although the anode-to-cathode spacing is as 383

long as 31.6 µm, as their TLP-measured latchup I–V curves 384

shown in Figs. 15 and 16. For test structures A, B, and C, 385

8 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 13. Relationships between TLP-measured latchup trigger (holding) volt-age and anode-to-cathode spacing for test structures A, B, and C.

Fig. 14. TLP-measured latchup I–V characteristics of test structure C withanode-to-cathode spacing of 27.5 µm.

Fig. 15. TLP-measured latchup I–V characteristics of test structure A withanode-to-cathode spacing of 31.6 µm.

increasing anode-to-cathode spacing can improve the latchup386

immunity. However, it cannot help test structures A and B to387

gain a good latchup immunity as in test structure C.388

Compared with test structures A and B, which have the389

traditional four-layer p-n-p-n latchup path, test structure C has390

a six-layer p-n-p-n-p-n latchup path due to the isolation region391

in isolated n-DEMOS. This six-layer latchup path consists of392

Fig. 16. TLP-measured latchup I–V characteristics of test structure B withanode-to-cathode spacing of 31.6 µm.

Fig. 17. Relationships between TLP-measured latchup trigger (holding) volt-age and guard ring width for test structures A, B, and C with anode-to-cathodespacing (parameter X) of 19.6, 25.6, and 27.5 µm, respectively.

P+ anode, N-well, P-well, NBL, P-well, and N+ cathode, in se- 393

quence. Due to the isolation region in isolated n-DEMOS, both 394

holes and electrons need to overcome an additional NBL/P-well 395

junction barrier to initiate a positive feedback latchup event. 396

Such unique characteristics will lead to a prominent latchup 397

immunity, i.e., high latchup trigger and holding voltages, in test 398

structure C. In addition, compared with test structure A, test 399

structure B has a shorter basewidth in its parasitic vertical p-n-p 400

and lateral n-p-n BJTs because of the additional source drift 401

region (i.e., longer emitter width). A shorter basewidth will lead 402

to a higher current gain of the parasitic BJTs, hence degrading 403

the latchup robustness [13] (i.e., lower latchup trigger and 404

holding voltages) in test structure B. In test structures A and B, 405

however, such difference of the basewidth is not obvious under 406

a larger anode-to-cathode spacing. As a result, test structure A 407

has a better latchup immunity (i.e., higher latchup trigger and 408

holding voltages) than test structure B under a shorter anode- 409

to-cathode spacing of < 25.6 µm, as shown in Fig. 13. For a 410

larger anode-to-cathode spacing of > 25.6 µm, however, both 411

test structures A and B have almost the same latchup trigger and 412

holding voltages. 413

2) Relationships Between Latchup Trigger (Holding) Volt- 414

age and Guard Ring Width: Fig. 17 shows the relationships 415

HSU AND KER: DEVICE STRUCTURE DEPENDENCE ON LATCHUP IMMUNITY 9

TABLE IISUMMARY OF THE DEPENDENCE OF DEMOS DEVICE STRUCTURES ON

LATCHUP ROBUSTNESS

between TLP-measured latchup trigger (holding) voltage and416

guard ring width for test structures A, B, and C with anode-417

to-cathode spacing (parameter X) of 19.6, 25.6, and 27.5 µm,418

respectively. For test structures A and B, increasing guard419

ring width can moderately improve the latchup immunity. For420

example, when guard ring width increases from 0.8 to 3 µm,421

latchup trigger voltage (holding voltage) can be enhanced from422

73 V (26 V) to 83 V (34 V) in test structure A and from423

67 V (32 V) to 74 V (35 V) in test structure B. For test424

structure C, however, increasing guard ring width only has little425

improvement on latchup immunity. Thus, in test structure C, the426

dominant factor to gain a good latchup immunity is the isolation427

region of isolated n-DEMOS, but not the guard ring structure.428

From the comprehensive experimental results in Figs. 13429

and 17, Table II summarizes the dependence of DEMOS de-430

vice structures on latchup robustness. HV ICs with isolated431

n-DEMOS (test structure C) have much better latchup immu-432

nity than those with nonisolated n-DEMOS (test structures A433

and B). Thus, the isolated n-DEMOS in test structure C is the434

dominant factor to enhance the latchup robustness in HV ICs.435

However, symmetric or asymmetric DEMOS in test structures436

A and B has no great impact to improve the latchup immunity,437

although asymmetric DEMOS has better latchup immunity than438

symmetric DEMOS under a shorter (< 25.6 µm) anode-to-439

cathode spacing, as shown in Fig. 13. In addition, increasing440

both anode-to-cathode spacing and guard ring width can en-441

hance the latchup immunity. However, continuously increasing442

anode-to-cathode spacing or guard ring width will lead to a443

larger layout area and higher cost. More importantly, using the444

isolated n-DEMOS in HV ICs can gain much better latchup445

robustness than only increasing anode-to-cathode spacing or446

guard ring width in layout schemes. Thus, using the isolated447

n-DEMOS in HV ICs not only can gain a good latchup immu-448

nity but also can save the total chip layout area.449

V. DEVICE SIMULATION450

The experimental measured latchup characteristics of differ-451

ent HV latchup test structures can be verified with 2-D device452

simulation. The device structures used in 2-D device simulation453

for test structures A, B, and C are shown in Fig. 18(a)–(c),454

respectively. To accurately verify the experimental results, these455

device structures in device simulation have the same layout456

parameters as the silicon test chips. For example, the anode-457

Fig. 18. Device structures used in the 2-D device simulation. (a) Test structureA. (b) Test structure B. (c) Test structure C. These device structures have thesame layout parameters as the silicon test chips.

to-cathode spacing in device simulation of test structures A, 458

B, and C are 31.6, 31.6, and 27.5 µm, respectively, which 459

are the same as silicon test chips in Figs. 14–16. Guard ring 460

width in test structures A, B, and C is a fixed value of 0.8 µm 461

in device simulation. With the aid of 2-D device simulation, 462

latchup I–V curves and their 2-D current flow lines can be 463

clearly observed to determine which device structure will be 464

dominant to enhance the latchup robustness in HV ICs. 465

The simulated latchup I–V curves of test structures A, B, 466

and C are shown in Fig. 19. These simulated I–V curves are 467

performed by connecting P+ anode and N+ guard rings to VDD 468

while connecting N+ cathode and P+ guard rings to GND. The 469

simulation results in Fig. 19 are consistent with the measured 470

results in Fig. 13, where test structure C has the best latchup 471

immunity because of its highest latchup trigger and holding 472

voltages. For example, latchup trigger (holding) voltage can 473

be as high as 94 V (41 V) for test structure C, although the 474

anode-to-cathode spacing is only as short as 27.5 µm. However, 475

latchup trigger (holding) voltage can be only enhanced up to 476

72 V (27 V) for test structure A and up to 62 V (26 V) for 477

test structure B, although they have a larger anode-to-cathode 478

spacing of 31.6 µm. The simulated holding voltage of 41 V 479

(> 40 V) in test structure C is consistent with the experimental 480

10 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 19. Simulated latchup I–V characteristics for test structures A and Bwith anode-to-cathode spacing of 31.6 µm and for test structure C with anode-to-cathode spacing of 27.5 µm. All these test structures have the same guardring width of 0.8 µm.

result in Fig. 14 that test structure C can be latchup free. In481

addition, the simulation results are also consistent with the482

experimental result in Figs. 15 and 16 that both test structures A483

and B have almost the same latchup holding voltage (∼27 V).484

The only difference between the experimental and simulated485

results is that both test structures A and B have almost the same486

latchup trigger voltage (∼71 V) in the experimental result, but487

test structure A has a larger one (72 V) than test structure B488

(62 V) in device simulation.489

The simulated 2-D current flow lines under latchup condition490

for test structures A, B, and C are shown in Fig. 20(a)–(c), re-491

spectively. Clearly, concentrated current flow lines will conduct492

from P+ anode (VDD) to N+ cathode (GND) under latchup493

condition. Compared with test structures A and B, which have494

the traditional four-layer p-n-p-n latchup path, test structure C495

has a unique six-layer p-n-p-n-p-n latchup path because of the496

isolated region in n-DEMOS, as shown in Fig. 20(c). Thus, it497

will lead test structure C to have much better latchup robustness498

than test structure A or B.499

VI. DISCUSSIONS500

Both experimental results and device simulation show that501

the additional isolation region in isolated n-DEMOS is the ma-502

jor reason to make better latchup immunity in structure C. This503

phenomenon can be reasonably explained by the concept of po-504

tential energy barrier. This concept can clearly explain that such505

isolation region can generate an additional P-substrate/NBL506

(P-well/N-well) junction barrier, greatly reducing the electron507

or hole current that can initiate latchup.508

A. Reducing Hole Current to Initiate Latchup509

The device structure C and the energy band diagram along510

the A−A′ (B−B′) direction are shown in Fig. 21(a) and (b), re-511

spectively. To turn on the emitter–base junction of the parasitic512

n-p-n BJT, the hole current needs to be collected by the cathode513

Fig. 20. Simulated 2-D current flow lines under latchup condition. (a) Teststructure A. (b) Test structure B. (c) Test structure C.

(P+ well contact tied to N+ source of n-DEMOS). Thus, the 514

hole current needs to flow from the outside of n-DEMOS to 515

the cathode along the A−A′ (B−B′) direction. However, due to 516

the isolation region of isolated n-DEMOS, the majority holes 517

need to overcome an additional P-substrate/NBL (P-well/N- 518

well) junction barrier to be collected by the cathode. As a result, 519

larger hole current is necessary to turn on the parasitic n-p-n 520

BJT in the isolated n-DEMOS, leading to a better latchup 521

robustness in test structure C. 522

B. Reducing Electron Current to Initiate Latchup 523

Although the parasitic n-p-n BJT is turned on, its injec- 524

tion electrons also face the same P-substrate/NBL (P-well/N- 525

well) junction barrier due to the isolation region of isolated 526

n-DEMOS, as shown in Fig. 21(c). Such junction barrier can 527

reduce the numbers of electrons that may escape the isolation 528

region along the A−A′ (B−B′) direction. These escaping elec- 529

trons can be subsequently collected by the anode (tied to N+ 530

well contact with VDD potential) outside the isolation region, 531

forming the electron current to turn on the parasitic p-n-p 532

BJT. Thus, the electron current contributing to turning on the 533

parasitic p-n-p BJT can be reduced, leading to a better latchup 534

robustness in test structure C. 535

HSU AND KER: DEVICE STRUCTURE DEPENDENCE ON LATCHUP IMMUNITY 11

Fig. 21. (a) Device structure of test structure C. (b) Energy barrier seen by the holes along the A−A′ (B−B′) direction. (c) Energy barrier seen by the electronsalong the A−A′ (B−B′) direction.

The concept of potential energy barrier can reasonably ex-536

plain why the isolated n-DEMOS can greatly enhance the HV537

latchup immunity. In addition, combing with the experimental538

results and device simulation, the concept of potential energy539

barrier can help investigate the HV latchup characteristics more540

comprehensively.541

VII. CONCLUSION542

HV latchup characteristics are investigated in a 0.25-µm543

2.5-V/40-V CMOS process. Different with the LV CMOS544

process where core circuits are the latchup dominant factors,545

HV I/O cells are dominant to the latchup immunity in HV chips.546

Thus, HV latchup immunity cannot be improved anymore by547

enlarging the spacing from I/O to internal circuits. To further548

improve the latchup immunity in HV chips, three latchup test549

structures are used to evaluate the latchup-robust HV device550

structures. Furthermore, layout parameters such as anode-to-551

cathode spacing and guard ring width are also investigated552

to find their impacts on latchup immunity. In order to avoid553

the HV latchup test structures being damaged so easily under554

the long-period (microseconds to milliseconds) latchup over-555

stress of continuous-type curve tracer, the TLP generator with556

pulsewidth of 100 ns and limited energy is used in this paper for557

latchup I–V measurements. With the TLP-measured latchup558

I–V curves of different latchup test structures, it was demon-559

strated that HV ICs with isolated n-DEMOS (test structure C)560

can gain much better latchup immunity than those with noniso-561

lated n-DEMOS (test structures A and B). However, symmetric562

or asymmetric DEMOS has no great impact to improve the563

latchup robustness in HV ICs. The concept of potential energy564

barrier can reasonably explain why the HV ICs with isolated 565

n-DEMOS can gain the good latchup robustness. All the TLP- 566

measured latchup I–V characteristics on different HV latchup 567

test structures can be qualitatively and quantitatively verified 568

with 2-D device simulation. Both the proposed latchup test 569

structures and simulation methodologies can be further applied 570

to extract safe and compact design rule for latchup prevention 571

in HV CMOS ICs. 572

ACKNOWLEDGMENT 573

The authors would like to thank G.-L. Lin and Y.-N. Jou 574

for their valuable technical discussions, as well as the Editor 575

and his reviewers for their valuable suggestions to improve 576

this paper. 577

REFERENCES 578

[1] J. C. Mitros, C.-Y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, 579D. Mosher, and T. R. Efland, “High-voltage drain extended MOS transis- 580tors for 0.18-µm logic CMOS process,” IEEE Trans. Electron Devices, 581vol. 48, no. 8, pp. 1751–1755, Aug. 2001. 582

[2] M. Vermandel, C. D. Backere, and A. V. Calster, “A high voltage p-type 583drain extended MOS in a low voltage sub-micron CMOS technology,” in 584Proc. IEEE ESSDRC, 1998, pp. 492–495. 585

[3] H. Ballan and M. Declercq, High Voltage Devices and Circuits in Stan- 586dard CMOS Technologies. Norwell, MA: Kluwer, 1998. 587

[4] B. J. Baliga, “Trends in power semiconductor devices,” IEEE Trans. 588Electron Devices, vol. 43, no. 10, pp. 1717–1731, Oct. 1996. 589

[5] P. Moens, B. Vlachakis, F. Bauwens, and L. DeSchepper, “Spatial distri- 590bution of interface traps in DeMOS transistors,” IEEE Electron Device 591Lett., vol. 25, no. 8, pp. 577–579, Aug. 2004. 592

[6] P. Moens, F. Bauwens, M. Nelson, and M. Tack, “Electron trapping and 593interface trap generation in drain extended pMOS transistors,” in Proc. 594IRPS, 2005, pp. 555–559. 595

12 IEEE TRANSACTIONS ON ELECTRON DEVICES

[7] C. Duvvury, D. Briggs, J. Rodriguez, F. Carvajal, A. Young, D. Redwine,596and M. Smayling, “Efficient NPN operation in high voltage NMOSFET597for ESD robustness,” in IEDM Tech. Dig., 1995, pp. 345–348.598

[8] M.-D. Ker and K.-H. Lin, “The impact of low-holding-voltage issue in599high-voltage CMOS technology and the design of latchup-free power-600rail ESD clamp circuit for LCD driver ICs,” IEEE J. Solid-State Circuits,601vol. 40, no. 8, pp. 1751–1759, Aug. 2005.602

[9] ——, “Double snapback characteristics in high-voltage nMOFETs and603the impact to on-chip ESD protection design,” IEEE Electron Device Lett.,604vol. 25, no. 9, pp. 640–642, Sep. 2004.605

[10] I.-C. Lin, C.-Y. Huang, C.-J. Chao, M.-D. Ker, S.-Y. Chuan, L.-Y. Leu,606F.-C. Chiu, and J.-C. Tseng, “Anomalous latchup failure induced by on-607chip ESD protection circuit in a high-voltage CMOS IC product,” in Proc.608IPFA, 2002, pp. 75–79.609

[11] S. Gupta, J. Beckman, and S. Kosier, “Improved latch-up immunity in610junction-isolated smart power ICs with unbiased guard ring,” IEEE Elec-611tron Device Lett., vol. 22, no. 12, pp. 600–602, Dec. 2001.612

[12] Q. Huang, G. Amaratunga, E. Narayanan, and W. Milne, “Static CMOS613latch-up considerations in HVIC design,” IEEE J. Solid-State Circuits,614vol. 25, no. 2, pp. 613–616, Apr. 1990.615

[13] R. R. Troutman, Latchup in CMOS Technology: The Problem and the616Cure. New York: Kluwer, 1986.617

[14] D. B. Estreich, A. Ochoa, Jr., and R. W. Dutton, “An analysis of latch-618up prevention in CMOS IC’s using an epitaxial-buried layer process,” in619IEDM Tech. Dig., 1978, pp. 230–234.620

[15] S. Voldman, E. Gebreselasic, L. Lanzerotti, T. Larsen, N. Feilchenfeld,621S. S. Onge, A. Joseph, and J. Dunn, “The influence of a silicon dioxide-622filled trench isolation structure and implanted sub-collector on latchup623robustness,” in Proc. IRPS, 2005, pp. 112–120.624

[16] S. Voldman, E. Gebreselasic, M. Zierak, D. Hershberger, D. Collins,625N. Feilchenfeld, S. S. Onge, and J. Dunn, “Latchup in merged triple well626structure,” in Proc. IRPS, 2005, pp. 129–136.627

[17] R. R. Troutman and H. P. Zappe, “Layout and bias considerations for628preventing transiently triggered latchup in CMOS,” IEEE Trans. Electron629Devices, vol. ED-31, no. 3, pp. 315–321, Mar. 1984.630

[18] M.-D. Ker and W.-Y. Lo, “Methodology on extracting compact lay-631out rules for latchup prevention in deep-submicron bulk CMOS tech-632nology,” IEEE Trans. Semicond. Manuf., vol. 16, no. 2, pp. 319–334,633May 2003.634

[19] J.-J. Peng, M.-D. Ker, and H.-C. Jiang, “Latchup current self-stop circuit635for whole-chip latchup prevention in bulk CMOS integrated circuits,” in636Proc. IEEE ISCAS, 2002, vol. 5, pp. 537–540.637

[20] S.-F. Hsu, M.-D. Ker, G.-L. Lin, and Y.-N. Jou, “Experimental evaluation638and device simulation of device structure influences on latchup immunity639in high-voltage 40-V CMOS process,” in Proc. IRPS, 2006, pp. 140–144.640

[21] T. J. Maloney and N. Khurana, “Transmission line pulsing techniques for641circuit modeling of ESD phenomena,” in Proc. EOS/ESD Symp., 1985,642pp. 49–54.643

[22] IC Latch-up Test, EIA/JEDEC Std. no. 78A, 2006.644

Sheng-Fu Hsu (S’04–M’06) received the B.S. 645degree from the National Tsing Hua University, 646Hsinchu, Taiwan, R.O.C., in 2000 and the M.S. 647and Ph.D. degrees from the Institute of Electronics, 648National Chiao Tung University, Hsinchu, in 2002 649and 2006, respectively. 650

He is currently with Taiwan Semiconductor Man- 651ufacturing Company, Hsinchu. His current research 652interests include semiconductor device physics and 653IC reliability. 654

Ming-Dou Ker (S’92–M’94–SM’97) received the 655B.S., M.S., and Ph.D. degrees from National Chiao- 656Tung University, Hsinchu, Taiwan, R.O.C., in 1986, 6571988, and 1993, respectively. 658

In 1994, he joined the Very Large Scale In- 659tegration (VLSI) Design Department, Computer 660and Communication Research Laboratories (CCL), 661Industrial Technology Research Institute (ITRI), 662Taiwan, R.O.C., as a Circuit Design Engineer. In 6631998, he was a Department Manager with the VLSI 664Design Division, CCL/ITRI. He is currently a Full 665

Professor with the Department of Electronics Engineering, National Chiao- 666Tung University. He has published more than 270 technical papers in interna- 667tional journals and conferences in the field of reliability and quality design for 668CMOS integrated circuits. He has also proposed many inventions to improve 669the reliability and quality of integrated circuits, which have been granted with 670113 U.S. patents and 123 R.O.C. (Taiwan) patents. He has been invited to teach 671and offer consultations on reliability and quality design for integrated circuits 672by hundreds of design houses and semiconductor companies in the Science- 673Based Industrial Park, Hsinchu, Taiwan, R.O.C., Silicon Valley, San Jose, CA, 674in Singapore, and in the Mainland China. His current research interests include 675reliability and quality design for nanoelectronics and gigascale systems, high- 676speed and mixed-voltage I/O interface circuits, and on-glass circuits for system- 677on-panel applications in thin-film-transistor liquid-crystal display. 678

Dr. Ker was a recipient of the Dragon Thesis Award from Acer Foundation, 679the National Invention Award in Taiwan in 2005 for one of his patents 680on electrostatic-discharge protection design, and many research awards from 681ITRI, National Science Council, and National Chiao-Tung University. He was 682selected as one of the Ten Outstanding Young Persons in Taiwan by the Junior 683Chamber International in 2003 and as a Distinguished Lecturer in the IEEE 684CAS Society for the period 2006-2007. He has been the Foundation President 685of Taiwan ESD Association since 2001. He has also served as a member of 686the technical program committee and a session chair of numerous international 687conferences. He is currently a Associate Editor of the IEEE TRANSACTIONS 688ON VLSI SYSTEMS. 689