Ge and SiGe for High Performance MOSFETs and Integrated ...
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Ge and SiGe for High Performance MOSFETs and Integrated Optical Interconnects Krishna C. Saraswat, Chi On Chui, Tejas Krishnamohan, Ali K. Okyay, Hyoungsub Kim 1 and Paul McIntyre 1 Department of Electrical Engineering, Stanford University, Stanford, CA 94305, U.S.A. 1 Department of Materials Science and Engineering, Stanford University, Stanford, CA 94305, U.S.A. Tel: (650) 725-3612, E-mail: [email protected] 1. Introduction It is believed that the difficulty in scaling the conventional Si MOSFET makes it prudent to search for alternative device structures, new material and fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing. The saturation of Si MOSFET drain current upon dimension shrinkage limits the prospect of future scaling. Historically it has been believed that as the device dimensions are scaled down the high field carrier velocity saturation diminishes the difference in performance of MOSFETs in different materials. However, it has been recently pointed out that a fundamental scaling limit for MOSFETs is the source injection velocity into the channel limiting the drain current [1]. The lower effective mass (and lower valley degeneracy) of Ge could alleviate the problem by providing a higher source injection velocity [2], which translates into higher drive current and smaller gate delay. Scaling of VLSI circuits can pose significant problems for interconnects, especially for those responsible for long distance communication on a high performance chip. The near-infrared photodetection and compatibility with Si technology of Ge-based materials, allow simultaneous fabrication of photodetectors and Si CMOS receiver circuits in a monolithically integrated fashion. Such technology could be used for on-chip optical interconnections in global signaling and clocking [3]. Surface passivation for gate dielectric and field isolation and n-type dopant incorporation are the two classic problems that obstruct CMOS device realization in Ge. In this paper we present a rview of the rcent activity in this area and application to MOSFETs and photodetectors. 2. High-k dielectrics for Ge passivation The poor quality Ge native dielectrics for gate insulator and field isolation have been one of the classic problems that obstruct VLSI CMOS device realization in Ge. Efforts to use materials like SiO 2 on a thin Si cap, Ge 3 N 4 , GeO x N y , etc. have been only marginally successful. Inspired by the recent successes of the high-k dielectrics on Si, we investigated the possibility of applying these materials to Ge. Volatility of Ge surface oxides or sub-oxides makes surface cleaning easier for high-k gate dielectric stack free of the performance limiting, lower-k, interfacial GeO x layer. We have demonstrated two different techniques to passivate Ge with hi-k dielectrics. In the first technique HfO 2 and ZrO 2 were deposited in a cold-wall high vacuum atomic- layer deposition (ALD) system at 300°C, using alternating surface-saturating reactions of metal tetrachloride and H 2 O precursors [4,5]. To study the effect of different surface preparations prior to high-k ALD, gate leakage currents, EOTs and hysteresis from the corresponding MOSCAPs were measured [5]. Among them cyclic rinsing between HF and H 2 O (CHF) for cleaning Ge and rapid thermal nitridation (RTN) in NH 3 gave the best results. The optimum dielectric stack (Fig. 1) could be attained by RTN of CHF Ge at 600ºC followed by hi-κ ALD. Excellent C-V curves were obtained from MOSCAPs on both Ge substrate types (Fig. 1) with low leakage. The RTN technique was also employed to passivate the Ge surface prior to the deposition of SiO 2 for field isolation. In the second technique gate dielectric was formed by UHV sputtering of ~22-30 Å Zr films on the Ge surface followed by in-situ UV ozone oxidation at room temperature. Ge/ZrO 2 interface was found to be free of any significant interfacial Ge oxide with excellent C-V characteristics with EOT in the range of 6-10 Å [6]. Variants of the high-k on Ge concept have been subsequently demonstrated in Ge MOSFETs by other groups [7,8] showing similar results. 4 nm HfO 2 Ge GeO x N y -1 0 1 0.0 0.5 1.0 1.5 2.0 Pt/HfO 2 /GeO x N y /p-Ge EOT = 20.3 Å Gate Bias (V) Gate Capacitance (µF/cm 2 ) Fig. 1. HRTEM (left) and MOS C-V characteristics (right) of ALD HfO 2 on thin Ge oxynitride (GeO x N y ) formed by RTN in NH 3 of CHF cleaned Ge surface [5]. 3. Dopant Diffusion in Ge p - and n - type dopant incorporation in Ge by was studied [5,6,9] using two techniques: ion implantation and diffusion from doped SiO 2 . We demonstrated symmetrically high levels of activation on both p- and n-type dopants in Ge, at concentrations applicable to advanced CMOS (Fig. 2). The results indicate that ion implanted junctions result in slow p- type but fast n-type dopant diffusion. To obtain shallow n-type profiles solid source diffusion from phosphorus-doped SiO 2 (PSG) was studied as an alternative (Fig. 2). 1.00E+15 1.00E+16 1.00E+17 1.00E+18 1.00E+19 1.00E+20 0 100 200 300 400 500 600 Concentration (cm -3 ) 10 20 10 18 10 15 Depth (nm) P As Sb P Sb As 675 °C 5 secs 650 °C 60 secs 10 19 10 17 10 16 1.00E+15 1.00E+16 1.00E+17 1.00E+18 1.00E+19 1.00E+20 0 100 200 300 400 500 600 Concentration (cm -3 ) 10 20 10 18 10 15 Depth (nm) P As Sb P Sb As 675 °C 5 secs 650 °C 60 secs 10 19 10 17 10 16 1.00E+17 1.00E+18 1.00E+19 1.00E+20 0 0.5 1 1.5 2 Depth ( μ m) Carrier Concentration (cm -3 ) 10 20 10 19 10 18 10 17 RTA at 850°C in N 2 300 s 20 s 60 s Fig. 2. SRP profiles of various n-type dopants in Ge (left) after RTA treatments (675 °C /5 secs and 650 °C/60 secs) [9]. Implantations of various species at a fixed dose of 4×10 15 cm -2 were carried out at energies corresponding to a similar projected range, (right) after 850ºC diffusion from PSG [5]. 4. Ge MOSFETs Using ultrathin ZrO 2 gate dielectric, Ge p-MOSFETs were fabricated (Fig. 3) using a low thermal budget (< 400°C) Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004, - 718 - A-8-1 (Invited) pp. 718-719
Transcript of Ge and SiGe for High Performance MOSFETs and Integrated ...
Ge and SiGe for High Performance MOSFETs and Integrated Optical Interconnects
Krishna C. Saraswat, Chi On Chui, Tejas Krishnamohan, Ali K. Okyay, Hyoungsub Kim1 and Paul McIntyre1
Department of Electrical Engineering, Stanford University, Stanford, CA 94305, U.S.A.1Department of Materials Science and Engineering, Stanford University, Stanford, CA 94305, U.S.A.
Tel: (650) 725-3612, E-mail: [email protected]
1. IntroductionIt is believed that the difficulty in scaling the
conventional Si MOSFET makes it prudent to search foralternative device structures, new material and fabricationtechnology solutions that are generally compatible withcurrent and forecasted installed Si manufacturing. Thesaturation of Si MOSFET drain current upon dimensionshrinkage limits the prospect of future scaling. Historically ithas been believed that as the device dimensions are scaleddown the high field carrier velocity saturation diminishes thedifference in performance of MOSFETs in different materials.However, it has been recently pointed out that a fundamentalscaling limit for MOSFETs is the source injection velocityinto the channel limiting the drain current [1]. The lowereffective mass (and lower valley degeneracy) of Ge couldalleviate the problem by providing a higher source injectionvelocity [2], which translates into higher drive current andsmaller gate delay.
Scaling of VLSI circuits can pose significant problemsfor interconnects, especially for those responsible for longdistance communication on a high performance chip. Thenear-infrared photodetection and compatibility with Sitechnology of Ge-based materials, allow simultaneousfabrication of photodetectors and Si CMOS receiver circuits ina monolithically integrated fashion. Such technology could beused for on-chip optical interconnections in global signalingand clocking [3].
Surface passivation for gate dielectric and field isolationand n-type dopant incorporation are the two classic problemsthat obstruct CMOS device realization in Ge. In this paper wepresent a rview of the rcent activity in this area andapplication to MOSFETs and photodetectors.
2. High-k dielectrics for Ge passivationThe poor quality Ge native dielectrics for gate insulator
and field isolation have been one of the classic problems thatobstruct VLSI CMOS device realization in Ge. Efforts to usematerials like SiO2 on a thin Si cap, Ge3N4, GeOxNy, etc. havebeen only marginally successful. Inspired by the recentsuccesses of the high-k dielectrics on Si, we investigated thepossibility of applying these materials to Ge. Volatility of Gesurface oxides or sub-oxides makes surface cleaning easier forhigh-k gate dielectric stack free of the performance limiting,lower-k, interfacial GeOx layer.
We have demonstrated two different techniques topassivate Ge with hi-k dielectrics. In the first technique HfO2and ZrO2 were deposited in a cold-wall high vacuum atomic-layer deposition (ALD) system at 300°C, using alternatingsurface-saturating reactions of metal tetrachloride and H2Oprecursors [4,5]. To study the effect of different surfacepreparations prior to high-k ALD, gate leakage currents, EOTsand hysteresis from the corresponding MOSCAPs weremeasured [5]. Among them cyclic rinsing between HF andH2O (CHF) for cleaning Ge and rapid thermal nitridation(RTN) in NH3 gave the best results. The optimum dielectricstack (Fig. 1) could be attained by RTN of CHF Ge at 600ºC
followed by hi-κ ALD. Excellent C-V curves were obtainedfrom MOSCAPs on both Ge substrate types (Fig. 1) with lowleakage. The RTN technique was also employed to passivatethe Ge surface prior to the deposition of SiO2 for fieldisolation. In the second technique gate dielectric was formedby UHV sputtering of ~22-30 Å Zr films on the Ge surfacefollowed by in-situ UV ozone oxidation at room temperature.Ge/ZrO2 interface was found to be free of any significantinterfacial Ge oxide with excellent C-V characteristics withEOT in the range of 6-10 Å [6]. Variants of the high-k on Geconcept have been subsequently demonstrated in GeMOSFETs by other groups [7,8] showing similar results.
4 nm
HfO2
Ge
GeOxNy
-1 0 1
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Gate Bias (V)
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e C
apac
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m2 )
Fig. 1. HRTEM (left) and MOS C-V characteristics (right) of ALDHfO2 on thin Ge oxynitride (GeOxNy) formed by RTN in NH3 ofCHF cleaned Ge surface [5].
3. Dopant Diffusion in Gep- and n- type dopant incorporation in Ge by was
studied [5,6,9] using two techniques: ion implantation anddiffusion from doped SiO2. We demonstrated symmetricallyhigh levels of activation on both p- and n-type dopants in Ge,at concentrations applicable to advanced CMOS (Fig. 2). Theresults indicate that ion implanted junctions result in slow p-type but fast n-type dopant diffusion. To obtain shallow n-typeprofiles solid source diffusion from phosphorus-doped SiO2(PSG) was studied as an alternative (Fig. 2).
1.00E+15
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Fig. 2. SRP profiles of various n-type dopants in Ge (left) after RTAtreatments (675 °C /5 secs and 650 °C/60 secs) [9]. Implantations ofvarious species at a fixed dose of 4×1015 cm-2 were carried out atenergies corresponding to a similar projected range, (right) after850ºC diffusion from PSG [5].
4. Ge MOSFETsUsing ultrathin ZrO2 gate dielectric, Ge p-MOSFETs
were fabricated (Fig. 3) using a low thermal budget (< 400°C)
Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004,
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A-8-1 (Invited)pp. 718-719
process [6]. Conventional self-aligned process requires hightemperatures for dopant activation, imposing a thermalstability requirement on the high-k gate stack. Wedemonstrated for the first time Ge n-MOSFETs with bothHfO2 and ZrO2 and metal gates using a simple self-alignedgate-last process. In this process shallow junctions wereobtained utilizing dopant diffusion from P-doped oxide [5]. N-channel Ge MOSFETs with conventional field isolation werefabricated using a self-aligned gate-last novel process withALD high-k gate dielectrics and metal gates and optimumsource/drain shallow junctions by diffusion from doped oxides[5]. Depletion mode p-channel Ge MOSFETs with highmobility have also been demonstrated in Ge nanowires [10].
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Fig. 3. Mobility of (left) bulk Ge p-MOSFETs [6] and (right) Genanowire p-MOSFETs [10] with ZrO2 gate dielectric
5. Strained Si and Ge Heterostructure Double Gate FETsIn order to enhance performance and continue scaling
MOSFETs to the sub-20nm regime, novel, high-mobilitymaterials like strained-Si and Ge (or SixGe1-x) are activelybeing researched for incorporation into the channel. However,due to the aggressive scaling requirements of ultra-thin bodies,high E-fields in the channel and introduction of high-kdielectrics, the channel mobility is severely degraded. Wehave developed un-doped, Center Channel (CC) NMOS andPMOS FETs (Fig. 4) that incorporate novel transportprinciples, which fully exploit the advantage of high mobilitymaterials. 1-D Poisson Schrodinger simulations verify thatcarriers are quantum mechanically confined to a very low E-field region in the center of the DG structure, leading to veryhigh channel mobility. Full-Band Monte Carlo simulationsshow a ~50% increase in drive currents and ~2X increase inswitching speeds at lower capacitance compared toconventional Si DGFETs (Fig. 5) [11]. The cut-off frequenciesfor the devices are in the terahertz regime, making the devicealso well suited for analog applications.
6. Ge Optical DetectorsMetal-semiconductor-metal (MSM) photodetectors, are
attractive for their high sensitivity-bandwidth product and lowcapacitance. The near-infrared photodetection andcompatibility with Si technology of Ge-based materials, willgallow simultaneous fabrication of photodetectors and CMOSreceiver circuits in a monolithic integration fashion. Suchtechnology could be used for on-chip optical interconnectionsin global signaling or clocking to eliminate many problemsassociated with large multi-GHz chips like reducing timingskew, power and area for clock distribution. However,relatively large IDARK in Ge photodetectors poses a seriousproblem. We have demonstrated that application ofasymmetric workfunction electrodes can significantlysuppress IDARK by tailoring the barrier heights (Fig. 6) [12].
Gate
Strained SiSix Ge1-x
Six Ge1-xSource Drain
NMOS
Strained SixGe1-x
Silicon
Silicon
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PMOS
Gate
Fig. 4 Device structure and the band diagram illustrating theoperation of the heterostructure center channel MOSFETs [11]
Fig. 5 Simulated drive currents and cut-off frequency for theconventional Si double gate and center channel doped andundoped heterostructure NFETs. [11]
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Ti-Ge-Ti (light) Ti-Ge-Ti (dark)Ni-Ge-Ni (light) Ni-Ge-Ni (dark)Ti-Ge-Ni (light) Ti-Ge-Ni (dark)
Iphoto ( = 1480 nm)
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Fig. 6. (Left) Energy band diagram of an a s y m m e t r i cworkfunction MSM photodetector, and (right) experimentalphotoresponse and dark current of symmetric and asymmetric MSM-photodetectors [12].
7. ConclusionsHigh mobility MOSFETs have been demonstrated in
bulk Ge and in nanowires with high-k gate dielectrics andmetal gates. High performance Metal-Ge-metal photodetectorswith asymmetric workfunction electrodes to suppress IDARKhave been demonstrated.Acknowledgements: This work was supported by DARPA,MARCO, and NSF. We would like to acknowledge Umicore forsupplying the Ge wafers.References[1] M. Lundstrom, IEEE EDL, vol. 18, p. 361, 1997.[2] S.-I. Takagi, VLSI Symp. Tech. Dig., p. 115, 2003.[3] H. Cho, et al., Proc. IEEE IITC, June 2004, San Francisco.[4] C. O. Chui et al., IEEE Electron Dev. Lett., p. 274, May 2004.[5] C. O. Chui et al., IEEE IEDM Tech. Dig., p. 437, 2003.[6] C. O. Chui et al., IEEE IEDM Tech. Dig., p. 437, 2002.[7] C. H. Huang, et al., VLSI Symp. Tech. Dig., p. 119, 2003.[8] A. Ritenour, et al., IEEE IEDM Tech. Digest, p. 433, 2003.[9] C. O. Chui, et al., Appl. Phys. Lett., vol. 83, 2003.[10] D. Wang, et. al, Appl. Phys. Lett., 22 Sept. 2003, p. 2432.[11]T. Krishnamohan, et al., IEEE SISPAD, Sept. 2004.[12] Ali K. Okyay, et al., CLEO June 2003.
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