i

Ge/SiGe Quantum Well Waveguide Modulator

for Optical Interconnect Systems

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Shen Ren

March 2011

This dissertation is online at: http://purl.stanford.edu/js140qf4168

© 2011 by Ren Shen. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

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I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

David Miller, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

James Harris, Co-Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Krishna Saraswat

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

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It is not the possession of truth, but the success which attends the seeking

after it, that enriches the seeker and brings happiness to him.

Max Plank (1858-1947)

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Abstract

Thanks to the development of silicon VLSI technology over the past several decades,

we can now integrate far more transistors onto a single chip than ever before.

However, this also imposes more stringent requirements, in terms of bandwidth,

density, and power consumption, on the interconnect systems that link transistors. The

interconnect system is currently one of the major hurdles for the further advancement

of the electronic technology. Optical interconnect is considered a promising solution

to overcome the interconnect bottleneck. The quantum-confined Stark effect in

Ge/SiGe quantum well system paves the way to realize efficient optical modulation on

Si in a fully CMOS compatible fashion. In this dissertation, we investigate the

integration of Ge/SiGe quantum well waveguide modulators with silicon-on-insulator

waveguides.

For the first time, we demonstrate the selective epitaxial growth of Ge/SiGe quantum

well structures on patterned Si substrates. The selective epitaxy exhibits perfect

selectivity and minimal pattern sensitivity. Compared to their counterparts made using

bulk epitaxy, the p-i-n diodes from selective epitaxy demonstrate very low reverse

leakage current and high reverse breakdown voltage. Strong quantum-confined Stark

effect (QCSE) is, for the first time, demonstrated in this material system in the

telecommunication C-band at room temperature. A 3 dB optical modulation

bandwidth of 2.8 THz is measured, covering more than half of the C-band. We

propose, analyze, and experimentally demonstrate a novel approach to realize butt

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coupling between a SOI waveguide and a selectively grown Ge/SiGe quantum well

waveguide modulator using a thin dielectric spacer. Through numerical simulation, we

show that the insertion loss penalty for a thin 20 nm thick spacer can be as low as 0.13

dB. Such a quantum well waveguide modulator with a footprint of 8 μm2 has also

been fabricated, demonstrating 3.2 dB modulation contrast with merely 1V swing at a

speed of 16 Gpbs.

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Acknowledgements

First and foremost, I would like to thank my Ph.D. advisor Prof. David A. B. Miller

for all his guidance, inspiration, encouragement, and support over the past six years. I

consider it my great privilege to be his student and work under his supervision. He is

an amazingly smart and charismatic leader with sharp insights and deep understanding

in physics and engineering. I learned substantially from him, not only on how to tackle

tricky problems, but also many other aspects in life. I truly consider him my lifelong

role model.

Secondly, I would like to thank my associate advisor Prof. James S. Harris. He opened

up my eyes to the amazing field of solid-state photonic devices, and has had a very

strong influence in shaping up my Ph.D. research. I also learned the great optimism

from him, without which I might never be able to reach this point in my life.

I would like to thank Prof. Theodore I. Kamins. I worked very closely with Ted over

the past several years and greatly benefited from his expertise in material science and

semiconductor physics. His great scientific curiosity, perseverance, and integrity set a

very high standard for me to learn from. Our bi-week QD meeting has been very

fruitful and filled with excitements.

I would like to thank Prof. Krishna C. Saraswat for severing on my oral committee and

reading this dissertation. He is an expert in advanced CMOS, especially those related

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to Ge. I learned semiconductor processing from his course. I also collaborated with

him and his students on a Ge photodetector project.

I also want to thank Prof. Mark Brongersma for chairing my oral defense.

Yu-Hsuan Kuo, Jon Roth, Onur Fidaner, and Yangsi Ge taught me a lot of hands-on

experimental techniques during my earlier years as a graduate student. I would also

like to thank all other team members of the SiGe project: Rebecca, Stephanie, Liz,

Emel, Ross, Yiwen, Yijie, and Ed.

I would like to thank the generous support of a Stanford Graduate Fellowship and all

the funding agencies. Under the UNIC program, I got the chance to work closely with

the SUN team and KOTURA team. The KOTURA team provided me with the SOI

waveguide platform. Special thanks go to Po, Shirong, Roshi, Dazeng, Hong, and

Mehdi. I also enjoyed lots of technical discussions with Jack, Ashok, Ron, Fafa, and

Ying.

Most of the fabrication work is done at SNF. I would like to thank all the SNF staff for

their help. Special thanks go to Maurice for maintaining the EPI machines, and James

Conway for supporting the e-beam lab. I also benefited from discussions with Ed

Mejers, Mary Tang, and Paul Rissman. I would like to thank Eric Perozziello, Jim

McVittie, Jim Kruger, and Usha Raghuram for sharing knowledge and experience on

processing. I would also like to thank the ASML team at Stanford: Ping, Linda, and

Vinny for the great support and technical assistance.

Tim Brand at the Ginzton crystal shop did most of the polishing work for my projects.

Thanks so much for all your amazing work, especially for working extra hours with

me when my deadline was coming close. Tom Carver did numerous metal

evaporations for me. I also want to thank Larry Randall for his artistic machining.

The Stanford library is arguably the treasure that I will miss the most in the future.

Over the years, I got lots of supports from the Stanford library, and more importantly,

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our friendly librarians. In particular, I want to thank Stella Ota and Sarah Lester for

their generous and kind help.

I want to thank past/current Miller group members: Ray, Henry, Yang, Luke, Ekin,

Salman, Onur, Jon, Rebecca, Stephanie, Liz, Emel, Ross, Krishna, Takuo, and Pierre. I

am blessed to be within such a vibrant research group with tons of fun. Ingrid, our

secretary, manages our group and makes it running smoothly.

I want to thank all my friends at Stanford and in the Bay area. My graduate life

wouldn’t be as colorful and enjoyable without you. I am fortunate to have several

close friends, Mahdieh, Paul Lim, Xiaobo, Fernando, Shyam, Gunhan, Hyun-Yong,

and many others. We shared our successes and failures, ups and downs, joys and tears,

during our graduate career. I hope that our friendship will keep developing in later

stages of our life.

I would like to express my greatest appreciation to my parents for bringing me to this

wonderful world and granting me the freedom to pursue my dream. Their

unconditioned love and support is the most valuable asset in my life, in addition to

Yummy’s persistent support.

In the end, I want to take this opportunity to remember my late grandmother, Yu

Zhang. Being an elementary school teacher, she placed education as the most

important thing for all my family members. While being frugal to herself, she paid the

tuitions for all the grandsons in the family for over 20 years. I still remembered the

days when my cousins and I tried our best to get a full marks in class to claim the

monetary rewards from her. I still remembered the proud smile when she talked about

her grandsons. It is her strong belief and kind encouragement that keeps me motivated

and struggling to become a better human being.

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Dedicated to my dear parents Chuan Wang and Weimin Ren and to my grandmother

Yu Zhang.

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Contents

Abstract .................................................................................................................. vii

Acknowledgements ................................................................................................ ix

Contents ................................................................................................................ xiv

Introduction ............................................................................................................. 1

1.1 Interconnect systems and optical interconnects........................................... 1

1.2 Interconnect bottleneck and on-chip optical interconnects ......................... 3

1.3 Devices and their requirements ................................................................... 6

1.4 Silicon Photonics ......................................................................................... 8

1.5 Organization ................................................................................................ 9

References ....................................................................................................... 10

Backgrounds .......................................................................................................... 13

2.1 Band structure of Si and Ge and its implications ...................................... 13

2.1.1 Band Structure and optical properties of Si and Ge .......... 13

2.1.2 Device Components in Si Photonics Platform .................. 15

2.2 Quantum wells and QCSE ......................................................................... 16

2.3 Properties of Ge/SiGe quantum well system ............................................. 18

2.3.1 Band Alignment and Simulation Methods ........................ 18

2.3.2 QCSE in Ge/SiGe QW System .......................................... 20

Chapter 1

Chapter 2

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2.4 Optical Waveguides ................................................................................... 22

2.4.1 EA Modulator Configurations: Surface Normal and

Waveguide ..................................................................................... 22

2.4.2 SOI Waveguides ................................................................ 24

2.5 Summary .................................................................................................... 26

References ....................................................................................................... 26

Growth of Ge/SiGe Quantum Wells ...................................................................... 31

3.1 Introduction ............................................................................................... 31

3.2 Bulk Growth of Ge/SiGe QWs .................................................................. 31

3.2.1 RPCVD growth of Ge QW ................................................ 32

3.2.2 Characterization Techniques ............................................. 33

3.2.3 Thin Buffer Exploration .................................................... 36

3.3 Selective Growth of Ge/SiGe QWs ........................................................... 39

3.3.1 Introduction and motivation .............................................. 39

3.3.2 Experimental Details ......................................................... 40

3.3.3 Growth Dependence on Pattern ......................................... 44

3.3.4 Growth Dependence on Temperature ................................ 47

3.4 Conclusions ............................................................................................... 48

References ....................................................................................................... 49

Thin Dielectric Spacer for Monolithic Integration ................................................ 53

4.1 Introduction ............................................................................................... 53

4.2 Integration Schemes and Motivations for Dielectric Spacers ................... 53

4.2.1 Integration Schemes .......................................................... 53

4.2.2 Motivations for Dielectric Spacer ..................................... 54

4.3 Numerical Analysis ................................................................................... 59

4.3.1 Transfer Matrix Method Analysis ..................................... 59

4.3.2 FDTD analysis ................................................................... 63

4.4 Spacer Fabrication Process ........................................................................ 65

Chapter 3

Chapter 4

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4.5 Discussions and Conclusions .................................................................... 70

References ....................................................................................................... 71

Ge/SiGe Quantum Well Waveguide Modulator Integrated with SOI

Waveguides ..................................................................................................... 75

5.1 Introduction ............................................................................................... 75

5.2 Device Design ........................................................................................... 76

5.2.1 Idealized Device Performance Predictions ........................ 76

5.2.2 Actual Device Design ........................................................ 79

5.2.3 Vertical Mode Mismatch ................................................... 82

5.3 Device Fabrication ..................................................................................... 84

5.4 Experimental Results ................................................................................. 93

5.4.1. Surface Normal Modulator ................................................ 93

5.4.2. Waveguide Modulator ....................................................... 96

5.5 Ge/SiGe Quantum Wells on the 3 μm SOI Waveguide Platform ............. 98

5.6 Conclusions ............................................................................................. 103

References ..................................................................................................... 103

Summary and Future Work ................................................................................. 106

6.1 Summary .................................................................................................. 106

6.2 Possible Future Work .............................................................................. 108

6.2.1 Material Aspects .............................................................. 108

6.2.2 Device Integration Aspects .............................................. 109

Thin Spacer Fabrication Process ......................................................................... 110

Chapter 5

Chapter 6 .................................................................... 106

Appendix I ...................................................................110

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List of Tables

Chapter 1

Table 1.1 Energy requirements for optical interconnects ....................................... 8

Chapter 3

Table 3.1 Summary of the faceting planes at different temperatures ................... 48

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List of Figures

Chapter 1

Figure 1.1 The interconnect hierarchy at different length scales, and the

adoption from electrical interconnect to optical interconnect systems.

Adapted from [3] ............................................................................................... 2

Figure 1.2 Current on-chip electrical interconnect system. (a). Schematic

representation for the interconnect module (taken from [5]). (b). Cross

sectional scanning electron microscopy (SEM) image of the Intel 45nm

technology process (taken from [6]). ................................................................. 4

Figure 1.3 Comparison of delays due to gate and interconnects at different

technology nodes (Adapted from [6]) ............................................................... 5

Chapter 2

Figure 2.1 Band structure for GaAs (a), Si (b), and Ge (c). Adapted after [1]. .... 14

Figure 2.2 Electron and hole energy levels and wavefunctions in the quantum

well system with Type I alignment without and with applied electric field ... 17

Figure 2.3 Absorption spectra for InGaAs/InP quantum well showing QCSE

(taken from [17]). ............................................................................................ 18

Figure 2.4 Band alignment for the Ge/Si1-xGex quantum well system

(published in [20]). .......................................................................................... 20

Figure 2.5 Absorption spectra for RPCVD grown Ge/SiGe quantum wells

(published in [18] ............................................................................................ 21

Figure 2.6 Two configurations for the optical modulator: surface normal based

(a) and the waveguide based (b). ..................................................................... 23

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Figure 2.7 Schematics for rib waveguide (a) and wire waveguide (b). ................ 24

Chapter 3

Figure 3.1 (a). Schematic of the growth epitaxy: vertical p-i-n structure. (b).

Strain in the quantum well region (published in [1]). ..................................... 33

Figure 3.2 TEM image of Ge/Si0.1Ge0.9 quantum wells ........................................ 33

Figure 3.3 SIMS measurements for a grown sample with 10 Ge quantum wells

(measurement done at Evans Analytical Group). ............................................ 35

Figure 3.4 Photocurrent spectra for a 10 pairs of Ge/SiGe on 150 nm relaxed

Si0.1Ge0.9 buffer. ............................................................................................... 37

Figure 3.5 Cross section (a) and plane view (b) SEM images of the quantum

well epitaxy grown with 150nm relaxed buffer. ............................................. 38

Figure 3.6 Cross section (a) and plane view (b) SEM images of the quantum

well epitaxy grown with 50nm relaxed buffer. ............................................... 39

Figure 3.7 Process flow for the template preparation for selective growth .......... 41

Figure 3.8 Schematic of the grown sample with relevant crystal planes. ............ 41

Figure 3.9 Cross section SEM for the selectively grown epitaxy with 10 pairs

of Ge/SiGe quantum wells: (a). at positions far away from the growth

window/mask boundary; (b). at the growth window/mask boundary ............. 43

Figure 3.10 Gas dynamics close to the surface of a patterned substrate

(courtesy of T. I. Kamins) ............................................................................... 44

Figure 3.11 Cross section SEM images of the grown selective epitaxy in

various window sizes: (a). 10 μm, scale bar: 2 μm; (b). 5 μm, scale bar: 2

μm; (c). 2 μm, scale bar: 1 μm; (d). 1 μm, scale bar: 500 nm. ........................ 45

Figure 3.12 Cross section SEM images of the grown selective epitaxy with

different oxide coverage percentage for 5 μm wide trenches. ......................... 46

Figure 3.13 Cross section SEM images of the grown selective epitaxy with

different oxide coverage percentage for 1 μm wide trenches. ......................... 47

Figure 3.14 Selective growth at different temperatures........................................ 48

Chapter 4

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Figure 4.1 The selective growth with a silicon recess, and without the spacer.

(a). Growth template (black dashed arrows indicate the directions of the

selective growth); (b). The grown film of relatively unpredictable shape,

shown also with the consequences of in-situ doping. ...................................... 55

Figure 4.2 The selective growth with a silicon recess, and the dielectric spacer.

(a). Growth template; (b). The grown epitaxy. ................................................ 57

Figure 4.3 The selective growth with the dielectric spacer and BOX removed.

(a). Growth template; (b). The grown epitaxy of a p-i-n SiGe diode with Ge

quantum wells in the intrinsic region. ............................................................. 58

Figure 4.4 Schematic of the problem setup: propagation through two SOI

waveguide sections with a SiO2 spacer in between. ........................................ 59

Figure 4.5 Modes in the optical waveguide: the ray-optics picture ...................... 61

Figure 4.6 Simplified 1D model for a plane wave component with incidence

angle θ.............................................................................................................. 61

Figure 4.7 Reflection coefficient evaluated for various angles at different

spacer thicknesses. ........................................................................................... 62

Figure 4.8 Transmitted, scattered, and reflected optical power percentage for

different spacer thicknesses. Inset: mode profile of the fundamental quasi-

TE mode for a 500nm wide and 300nm thick SOI waveguide. ...................... 64

Figure 4.9 Electrical field distribution for different spacer thicknesses in the

cross section plane along the dashed line in Figure 4.4 .................................. 65

Figure 4.10 Process flow for the thin spacer fabrication ...................................... 67

Figure 4.11 Cross section image of a Si trench after depositing a 40 nm SiO2

layer. ................................................................................................................ 68

Figure 4.12 End point detection for the nitride dry etch, stopping at the

underlying oxide. ............................................................................................. 69

Figure 4.13 Cross section SEM image, showing a 22nm SiO2 spacer on a

sidewall with 80o slope. .................................................................................. 70

Chapter 5

Figure 5.1 Schematic for overall device concept. ................................................ 76

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Figure 5.2 Absorption coefficient ratio with a 1 V swing .................................... 77

Figure 5.3 (a) Epitaxy design for waveguide modulator to match the SOI

waveguide. (b). Schematic of the SOI waveguide and the active section

after the CMP. ................................................................................................. 81

Figure 5.4 Final device schematic ........................................................................ 82

Figure 5.5 3D FDTD simulation: electrical field component at the central

plane of the SOI waveguide ............................................................................ 84

Figure 5.6 Starting SOI substrate: 1 μm thick BOX and 310nm thick top Si.

(a). Isometric view; (b). Cross section view .................................................... 85

Figure 5.7 Define SOI shallow ridge waveguide: (a). Isometric view; (b).

Cross section view along the dashed cut plane................................................ 85

Figure 5.8 Deposit 1.5 μm thick PECVD SiO2 on the surface : (a). Isometric

view; (b). Cross section view along the dashed cut plane ............................... 86

Figure 5.9 2nd

lithography to define the growth window and etch down to

handle substrate: (a). Isometric view; (b). Cross section view along the

dashed cut plane .............................................................................................. 87

Figure 5.10: 20nm LPCVD SiO2 deposition: (a). Isometric view; (b). Cross

section view along the dashed cut plane .......................................................... 87

Figure 5.11: 50nm LPCVD Si3N4 deposition: (a). Isometric view; (b). Cross

section view along the dashed cut plane .......................................................... 87

Figure 5.12: Highly anisotropic Si3N4 dry etching: (a). Isometric view; (b).

Cross section view along the dashed cut plane................................................ 88

Figure 5.13: HF wet etching: (a). Isometric view; (b). Cross section view

along the dashed cut plane ............................................................................... 88

Figure 5.14: Selective Si3N4 wet etching: (a). Isometric view; (b). Cross

section view along the dashed cut plane .......................................................... 88

Figure 5.15: Selective epitaxial growth of the Ge/SiGe quantum wells: (a).

Isometric view; (b). Cross section view along the dashed cut plane ............... 89

Figure 5.16: Planarizing CMP step: (a). Isometric view; (b). Cross section

view along the dashed cut plane ...................................................................... 89

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Figure 5.17: Deep ridge etching to define waveguide in active section: (a).

Isometric view; (b). Cross section view along the dashed cut plane ............... 90

Figure 5.18: 50 nm LTO deposition: (a). Isometric view; (b). Cross section

view along the dashed cut plane ...................................................................... 91

Figure 5.19: Final device: (a). Isometric view; (b). Cross section view along

the dashed cut plane ......................................................................................... 91

Figure 5.20 Cross section SEM of the finished device at the boundary between

the SOI waveguide and the Ge/SiGe waveguide modulator ........................... 92

Figure 5.21 Optical microscope image of a finished device with a 5 μm long, 3

μm wide active section. ................................................................................... 92

Figure 5.22 Dark current-voltage characteristic for a 150 μm by 150 μm

square mesa diode fabricated from a 200 μm by 200 μm growth window

opening. ........................................................................................................... 94

Figure 5.23 Photocurrent spectra of the same diode under different bias

voltages. ........................................................................................................... 95

Figure 5.24 Photocurrent ratio of the same diode under different bias voltages.

The green box indicates the telecommunication C-band (1530 nm~1565

nm). .................................................................................................................. 95

Figure 5.25 Schematics of waveguide measurement setup for high speed

testing. ............................................................................................................. 96

Figure 5.26 Waveguide measurement setup. (a). Zoomed-in image of the

experimental setup. (b). Image from top-view camera during testing............. 97

Figure 5.27 High speed oscilloscope trace showing the transmission of the

waveguide modulator under high speed electrical signal. (a). Original

oscilloscope trace; (b). Zoomed-in replot of the same data. ............................ 98

Figure 5.28 3 μm wide large cross section rib waveguide (taken from ref [15]). 99

Figure 5.29 Fundamental mode profile of the 3 μm rib waveguide. Color plot

shows the power flow in the propagation direction; contour plot shows the

electric field in the x-direction. ..................................................................... 100

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Figure 5.30 Electric field component in the x-direction along the central cut

line (the white dashed line in Figure 5.29). .................................................. 100

Figure 5.31 Integration of Ge QW through growth from handle substrate ........ 101

Figure 5.32 Integration of Ge QW through Si recess ......................................... 101

Figure 5.33 Optical distribution of the fundamental mode within the

waveguide ...................................................................................................... 102

Chapter 6

Figure 6.1 Resonator based Ge/SiGe quantum well waveguide modulator: (a).

grating based; (b). 1-D photonic crystal based. ............................................. 109

Appendix I ................................................................ 110

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Chapter 1

Introduction

1.1 Interconnect systems and optical interconnects

Interconnect systems generally refer to communication links between multiple parties

at different physical locations. The most widely known interconnect system is the

telecommunication system, which carries most of the phone, data, and internet traffic

over distances of several to thousands of kilometer. At shorter and shorter distances,

there are interconnects that link different high performance computers (HPC) in a data

center (tens of meters long), different circuit boards within a computer (inter-board

links, typically several of meters long), different chips on a circuit board (inter-chip

links, hundreds of millimeters long), different CPU cores within a chip (several

millimeters long), and transistors within a CPU core (hundreds of microns long). The

last two links combined are also referred as on-chip interconnects. Based on

application, the interconnect systems can also be divided into telecom systems and

datacom systems. The demands for higher speed, larger capacity, and lower cost

interconnect systems have sustained technological innovations and growth for quite a

long time, yet the need for shorter distance interconnects has been greater. For telecom

systems, this demand comes from the ever-increasing subscribers and emerging

network applications, such as video-on-demand and telemedicine [1]. For datacom

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systems, the demand is predominantly driven by the ever-lasting advancement of the

integrated circuit (IC) technology, i.e. the well-known “Moore’s Law” [2].

Figure 1.1 The interconnect hierarchy at different length scales, and the

adoption from electrical interconnect to optical interconnect systems. Adapted

from [3]

The signal that carries the information in the interconnect systems can be electrical or

optical. Interconnect systems can also categorized into electrical interconnects and

optical interconnects. The electrical interconnect systems date back to the invention of

electrical telegraphy in 19th

century; while the optical interconnects can date back even

further. More than two thousand years ago in the Zhou Dynasty, the ancient Chinese

people already utilized smoke generated from fire to signal the invasion of enemies to

places several miles away. This is a rudimentary form of optical communication. With

the Nobel-winning invention of very low-loss optical fiber, it started to replace the

electrical cables in the long-haul telecommunication systems in the late 1980s. To

date, optics has been ubiquitously adopted in long-distance interconnect systems, and

progressively replacing electrical cables in interconnect systems of shorter distances.

Figure 1.1 shows a history and roadmap for the takeover of electrical interconnects by

optical interconnect systems [3]. Since the late 1990s, computer servers in large scale

3

data centers have already been connected by optical fibers. It is predicted that starting

from 2015 we will start to see optics being deployed to inside CPUs.

1.2 Interconnect bottleneck and on-chip optical

interconnects

Since the birth of the IC technology, there has been an exponential growth in its

complexity and capabilities. This is made possible by the scaling down of the

minimum feature size and the scaling up of the maximum chip size, both of which are

subject to the constraint of reasonable yield [2, 4]. According to the “universal

scaling” rule, with a scaling factor of α (α<1), the density of the transistors scales up

by 1/α2, while the switching delay of a transistor scales down by α. Furthermore, the

power consumption pre transistor also scales down by a factor of α. All of these above

consequences are desirable and lead to the performance improvements. However,

scaling also impacts the on-chip interconnects. As more and more transistors are

packed into a given area on a computer chip, the on-chip interconnect system is also

getting more and more complicated. Figure 1.2 illustrates the electrical interconnect

system for the 45 nm technology node, where 9 metal layers are used [6]. For the

communication between two close-by transistors, very short links are needed. These

short links are realized by the metal layers close to the transistor level and referred to

as local interconnects, as shown in Figure 1.2 (a). Global interconnects refer to the

longer communication links for transistors that are far apart from each other, which

are carried by the metal layers far away from the transistor plane. In between the local

interconnects and global interconnects are intermediate interconnects, also known as

the semi-global interconnects.

4

Figure 1.2 Current on-chip electrical interconnect system. (a). Schematic

representation for the interconnect module (taken from [5]). (b). Cross sectional

scanning electron microscopy (SEM) image of the Intel 45nm technology

process (taken from [6]).

Not only are the on-chip interconnects more complicated for later technology nodes,

they also become the main bottleneck for the further advancement of the IC

technology. As first argued by J. W. Goodman et al back in 1984 [7], if all three

dimensions of the interconnecting wires scale down by α, the RC time constant and

the interconnect delay will remain unchanged. Given the fact that size of chips and the

distance over which interconnect systems need to cover will most likely remain

unchanged, the interconnect delay will then increase as transistors continue to scales

down. Figure 1.3 gives a comparison of the relative delay of gate, local interconnect,

and global interconnect [8]. Both gate delay and local interconnect delay scale reduce

for smaller technology nodes. On the other hand, the relative delay due to global

interconnects increases as transistors scale down. This problem can be partially

alleviated by using repeaters to divide long distance interconnect links with the

penalty of a significant increase in power consumption. The discrepancy between the

gate delay and global interconnect delay also imposes further complexities in the chip

architectures for design engineers [9].

5

In addition to delay, the channel bandwidth of the existing interconnect is also a

performance bottleneck. The bit rate of an electrical wire is proportional its cross

section divided by its length square, and hence is determined by the aspect ratio of the

wire [10]. While transistors operate at a faster speed in later technology nodes, the

bandwidth of the interconnect remains roughly constant. In the current technology

node, there is already a severe scarcity in channel bandwidth for global interconnects.

Furthermore, an even more important aspect for the IC technology is power

consumption. Power consumption and the associated problem of heat dissipation have

been the main constraints for high performance microprocessors. For the 180nm

technology node, 46% of the chip power is consumed by the signaling interconnects.

And if we combine the signaling interconnects with clocking distribution, more than

80% is consumed [11]. It is expected that an even higher percentage of the chip power

will be consumed by interconnect in later technology nodes.

Figure 1.3 Comparison of delays due to gate and interconnects at different

technology nodes (Adapted from [6])

6

The International Technology Roadmap for Semiconductors (ITRS) has identified

several alternatives to overcome this interconnect bottleneck, such as replacing the

existing copper wires with carbon nanotubes, graphene nanoribbons, superconducting

wires, or optical waveguides [5]. Here we are interested in the last approach, i.e. on-

chip optical interconnects.

With the huge success of optics in long distance communication systems, we are

confident that it can play a role to break the interconnect bottleneck and substantially

advance the IC technology. Optical interconnect has many obvious advantages

compared to electrical interconnect [10]. While electrical signals in practice in the RC

lines on chips can only propagate at a small fraction of the speed of light, optical

signals propagate at very close to the speed of light. This can substantially reduce the

global interconnect delay and latency. Moreover, at the optical frequency (200 THz

for 1.5 μm wavelength), the available bandwidth is significantly larger than that of

electrical interconnects. This makes it possible to deploy wavelength division

multiplexing (WDM), which can greatly increase the interconnect bandwidth and

density. Furthermore, better signal integrity and timing precision can be achieved. On

the other hand, replacing electrical interconnect with optical interconnect does not

necessarily reduce the power consumption and lower the cost. These two aspects

eventually determine the success of on-chip optical interconnects.

1.3 Devices and their requirements

Similar to all other optical interconnect systems, on-chip optical interconnect involves

the generation, modulation, propagation, and detection of photons. It is comprised of

four building blocks: optical source, modulator, waveguide, and photodetector. The

optical source can be a laser or light emitting diode. The optical beam is emitted by the

optical source, either on-chip or off-chip, and modulated by the optical modulator

which is driven by the electrical output from a transistor. Then the modulated optical

beam will be propagated through the waveguide, and eventually reach the

7

photodetector, where it will be converted back to an electrical signal and will drive the

destination transistor.

Among these four building blocks, the optical source, modulator, and photodetector

actively consume power, while the optical waveguide does not. For optics to take over

on-chip interconnect, the energy consumption by these devices has to be very low.

Reference [12] extensively reviewed the energy consumption for existing electrical

interconnects, and proposed the energy consumption requirements for both the overall

system and individual device components for future optical interconnects. We

summarize the conclusions in Table 1.1. For optical interconnect that connect chips to

other off-chip components, the devices cannot consume more than 20 fJ/bit, while less

than 10 fJ/bit energy consumption is required for components in on-chip global

interconnects. These energy requirements have significant impacts on the choice of

system architecture and device component design. Developing devices that meet these

aggressive energy requirements will be crucial to the implementation of optical

interconnect to and on computer chips. At the same time, the technologies developed

along the way are also applicable to longer-distance optical interconnects, and will

reduce the cost and energy consumption for longer-distance optical interconnect

systems.

8

Table 1.1 Energy requirements for optical interconnects

Applications

Energy Requirement

Off-chip

Interconnects

On-chip global

Interconnects

Total System (existing electrical) 2 – 30 pJ/bit 400 fJ/bit – 6 pJ/bit

Total System (optical interconnect) 1 pJ/bit – 100fJ/bit 200 – 20 fJ/bit

Total System (2022) < 50 fJ/bit < 10 fJ/bit

Component Requirements (optical) 10 – 20 fJ/bit 2 – 10 fJ/bit

1.4 Silicon Photonics

Another technological challenge for optical interconnects is cost. With the exiting IC

technology, the cost for an electrical interconnect is extremely low. It would be

difficult for optics to take over the on-chip interconnect system, if such adoption

dramatically increased the cost. Moreover, with the massive investment in the very

large scale integration (VLSI) of Si, it is highly desirable that the optical interconnect

system utilize the existing infrastructure and technology. Hence there is a very strong

motivation to build this optical interconnect system using the materials and processing

techniques that are already widely used in CMOS foundries. For this reason, the Si

photonics platform has been strongly advocated and extensively investigated [13-16].

Various device components based on Si or Si compatible material, such as Ge, have

been demonstrated. In this thesis, we investigate a Ge quantum well (QW) waveguide

modulator that is integrated with the Si-on-insulator (SOI) waveguide platform and

compatible with the CMOS technology.

9

1.5 Organization

The rest of the thesis is organized as follows.

In Chapter 2, we will give some background knowledge of this work. The band

structure of Si and Ge will be reviewed, and its implications for device components in

Si photonics will be discussed. Quantum well structures and the quantum-confined

Stark effect in Ge QWs will be introduced. Properties of Si based optical waveguides

will also be discussed.

In Chapter 3, we focus on the growth of Ge QWs on Si substrates using reduced

pressure chemical vapor deposition. In particular, a special growth technique, selective

epitaxial growth, was extensively studied and will be described.

In Chapter 4, a thin dielectric spacer for integrating Ge QWs on the SOI waveguide

platform will be introduced. We study the impact of this spacer layer through

numerical simulation. Furthermore, a robust fabrication process is proposed and

demonstrated to realize sub-25nm thin spacer layers uniformly and controllably.

In Chapter 5, a Ge QW waveguide modulator that is integrated with the SOI

waveguides is demonstrated. Device design, fabrication processes, as well as

experimental measurement results will be discussed.

In Chapter 6, we summarize this thesis work, draw some conclusions and point out

some future research directions.

10

References

1. D. A. Perednia and A. Allen, “Telemedicine technology and Clinical

Applications,” J. Am. Med. Assoc, 273, 483-488 (1995)

2. G. E. Moore, “Cramming more components onto integrated circuits,”

Electronics, 38, 114-117 (1965).

3. A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter,

"Exploitation of optical interconnects in future server architectures," IBM J.

Res. Dev. 49, 755-775 (2005).

4. Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices,” 2nd ed.

Cambridge University Press, 2009.

5. The International Technology Roadmap for Semiconductors, 2009 edition.

6. P. Moon, et al, “Process and electrical results for the on-die interconnect stack

for Intel’s 45nm process generation,” Intel Technology Journal 12, (2008)

7. J. W. Goodman, F. J. Leonberger, S. Y. Kung and R. A. Athale "Optical

interconnections for VLSI systems", Proc. IEEE. 72, 850-866 (1984).

8. The International Technology Roadmap for Semiconductors, 2005 edition.

9. R. Ho, K. W. Mai, and M. A. Horowitz, “The future of wires,” Proc. IEEE 89,

490-504 (2001).

10. D. A. B. Miller, "Rationale and challenges for optical interconnects to

electronic chips," Proc. IEEE 88, 728-749 (2000).

11. G. Chandra, P. Kapur, and K. C. Saraswat, “Scaling trends for the on chip

power dissipation,” in Proc. IEEE Interconnect Technology Conf., 170–172

(2002).

12. D. A. B. Miller, "Device requirements for optical interconnects to silicon

chips," Proc. IEEE 97, 1166-1185 (2009).

13. R. Soref, "The past, present, and future of silicon photonics," IEEE J. Sel. Top.

Quantum Electron 12, 1678-1687 (2006).

14. L. C. Kimerling, et al., "Electronic-photonic integrated circuits on the CMOS

platform," Proc. SPIE 6125, 612502-1-612502-10 (2006).

11

15. M. Lipson, "Guiding, modulating, and emitting light on Silicon-challenges and

opportunities," J. Lightwave Technol. 23, 4222-4238 (2005).

16. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G.

Li, I. Shubin, and J. E. Cunningham, "Computer systems based on silicon

photonic interconnects," Proc. IEEE 97, 1337-1361 (2009).

13

Chapter 2

Backgrounds

This chapter reviews the technical background for this thesis. In particular, we discuss

the band structures of Si and Ge. The band structure of a material determines its

optoelectronic properties, and hence its functionality in photonic systems. Then the

quantum well system and the quantum-confined Stark effect in quantum well systems

will be addressed. Finally, we will give a brief overview of Si based optical

waveguides.

2.1 Band structure of Si and Ge and its implications

2.1.1 Band Structure and optical properties of Si and Ge

Based on the location of conduction band minima and valence band maxima in k-

space, semiconductors can be divided into two categories: direct gap semiconductors

and indirect gap semiconductors. For direct gap semiconductors, such as GaAs, both

the conduction band minimum and the valence band maximum occur at the zone

center, k=0, as shown in Figure 2.1 (a). For indirect gap semiconductors, such as Si

and Ge, the conduction band minima occur off the zone center, along the <1 0 0> and

<1 1 1> direction, respectively.

14

The band structure of a semiconductor material determines its optical properties. First

of all, the band gap energy determines the photon energy above which the material

absorbs. For example, the band gap of Si is 1.1 eV, corresponding to a wavelength of

1.13 μm. Hence it absorbs photons with wavelengths shorter than 1.13 μm. This is the

physical basis for Si based photodetectors and charge coupled devices (CCD). On the

other hand, in the widely used telecommunication band (around 1.55 μm), Si is

transparent, hence is the ideal material for passive devices, such as waveguides. Ge,

with a band gap of 0.66eV, absorbs strongly in the telecommunication band, and is a

good material for photon detection around 1.55 μm wavelength.

Secondly, inter-band transitions between the conduction band minima and valence

band maxima in direct gap semiconductors do not have to involve phonons. This

makes direct-gap semiconductors efficient light emitters. For this reason, III-V

semiconductors, especially GaAs and InP, have been widely used for lasers and light

emitting diodes. On the other hand, indirect semiconductors, such as Si and Ge, are

not good at light emission since the inter-band transition involves the participation of

phonons. The conduction band minima in the indirect gap semiconductor serve as a

carrier sink, and make it difficult and inefficient for such materials to lase.

Figure 2.1 Band structure for GaAs (a), Si (b), and Ge (c). Adapted after [1].

15

2.1.2 Device Components in Si Photonics Platform

As we discussed in Chapter 1, low cost optical interconnect relies on the Si photonics

platform to leverage the existing technology and investment in VLSI technology. A

commonly preferred wavelength of operation is the telecommunication band near 1.55

μm. Not only does the optical fiber exhibit extremely low loss in this wavelength

range, but also the erbium doped fiber amplifier (EDFA) happens to operate at this

wavelength range. On the 1.55 μm Si photonics platform, SOI waveguides exhibit

very low loss, and can be used for passive signal routing [2]. Silicon photodetectors,

either based on surface states or bulk defects, have been demonstrated, but with

relatively low efficiency and responsivity at 1.55 μm [3, 4]. Ge, already widely used in

advanced CMOS technology, absorbs strongly in the 1.55 μm range. Heterogeneous

integrated Ge photodetectors on the Si substrate have been extensively investigated

and are considered the ideal component for photo detection in the Si photonic platform

[5, 6, 7].

Because of the indirect nature of Si, realizing Si based lasers has been a very

challenging task. Although there have been many attempts towards such a device [8,

9, 10, 11], practical large-scale implementation remains elusive in the near future. So

most likely, the optical interconnect will use an off-chip light source. This approach is

actually preferred over integrating light source on chip due to heat dissipation

concerns. The electrical interconnect draws its electricity from off-chip anyway, so the

idea of off-chip power sources is not itself unusual.

To transform the electrical signal from the output of a transistor to an optical signal, an

optical modulator is required. There are two basic types of optical modulators, the

electro-refractive modulators and the electro-absorption modulators. Si electro-

refractive modulators rely on injecting or depleting the carriers inside Si to induce a

refractive index change, which is a relatively weak physical mechanism. To

accumulate a large change, devices in this category have to be very large in size or

built into a high-Q resonator [12, 13]. The footprint of large devices makes them

16

unattractive for on-chip optical interconnect applications. High-Q resonator devices,

on the other hand, can be very small, but are very sensitive to temperature and

fabrication variation, and hence require precise temperature tuning and stabilization.

Electro-absorption modulators rely on the electric-field induced absorption coefficient

change. The underlying physical mechanism is the Franz-Keldysh effect (FKE) in

bulk semiconductors or the quantum-confined Stark effect (QCSE) in semiconductor

quantum wells, both of which are very strong physical mechanisms. The most efficient

modulation occurs close to the absorption edge. So Ge is the material of choice for

electro-absorption modulators on Si. Since the physical mechanism is very strong,

high-Q resonators are not needed. So devices in this category can have a larger

bandwidth and lower temperature sensitivity. A Ge FKE modulator has already been

demonstrated [14], showing low energy, large bandwidth, and small device footprint.

Compared to the FKE, the QCSE induced absorption change can be even stronger

with a given applied electrical field. In the next section, we will look into the quantum

well system and the QCSE in detail.

2.2 Quantum wells and QCSE

The quantum well system is comprised of precisely controlled alternating

semiconductor layers, typically several nanometers thick. Electrons and holes in the

quantum well system experience “particle-in-a box” like confinement. Thanks to the

development of advanced growth techniques, especially molecular beam epitaxy

(MBE), quantum well systems have been widely deployed in advanced optoelectronic

devices, ranging from devices with better performance, such as low threshold lasers

and electro-absorption modulators, to devices that cannot be realized in bulk

semiconductors, such as quantum cascade lasers.

In particular, we are interested a special type of quantum well system where both the

conduction minima and the valence maxima occur within the same layer, i.e. type I

alignment. The best known of such systems is the GaAs/AlGaAs quantum well

17

system. In such a system, the AlGaAs layer is the barrier, and has lower valence band

edge and higher conduction band edge than the GaAs layer. Hence the electrons and

holes are both confined in the GaAs “quantum well” layer. Earlier work demonstrated

that the absorption in such a quantum well system can be efficiently modified by

varying the electrical field across the quantum wells, i.e., the quantum-confined Stark

effect [15, 16, 17]. Figure 2.2 illustrates the electron and hole states in a quantum well

system with Type I alignment. Both electron and hole are confined within the quantum

well with discretized energy levels. With applied electric field, the potential profile of

the system gets tilted, resulting in a shift in the energy levels and modification of the

associated wavefunctions. Due to the shift in the energy levels, the absorption of the

system takes place at a lower energy, or longer wavelength. Modifications of the

wavefunctions and hence the wavefunction overlaps between the electron and hole

states change the absorption strength at a given wavelength.

Figure 2.2 Electron and hole energy levels and wavefunctions in the quantum

well system with Type I alignment without and with applied electric field

Figure 2.3 shows the absorption spectra in the InGaAs/InP quantum well system at

different bias voltages. Very strong absorption change, due to the QCSE, can be

observed. QCSE based electroabsorption modulators are now widely deployed in the

long-haul telecommunication systems. However, most of these devices are based on

III-V direct gap semiconductor systems, such as GaAs/AlGaAs and InGaAs/InP,

which are not compatible with the CMOS technology. Back in 2005, we demonstrated,

18

for the first time, QCSE in Ge/SiGe quantum wells on Si substrate [18]. This opens up

a pathway towards making efficient, CMOS compatible, QCSE modulators. In the

next section, we will discuss the properties of this new quantum well system.

Figure 2.3 Absorption spectra for InGaAs/InP quantum well showing QCSE

(taken from [17]).

2.3 Properties of Ge/SiGe quantum well system

2.3.1 Band Alignment and Simulation Methods

There is a subtle difference in band structure between Si and Ge. Although Ge is an

indirect gap semiconductor, the direct gap at the zone center is only 0.14eV higher

than the indirect gap, as shown in Figure 2.1(c). The corresponding band gap energy

difference is 3.3eV. So in some sense, Ge is more “direct semiconductor”-like than Si.

A Ge/SiGe quantum well system is composed of thin layers of Ge and Si1-xGex alloy.

The lattice constants for Si and Ge are 5.43 Å and 5.66 Å, respectively. With a lattice

mismatch of more than 4%, integrating these two materials heterogeneously together

19

is very challenging. The critical thickness for growing Ge directly on Si without defect

formation is smaller than 10nm [19]. To reduce the defects in the quantum well layers,

we designed the epiaxial structure such that the overall system is lattice matched to the

Si1-yGey relaxed buffer. The relationship between the Ge concentration in the barrier

and the buffer, denoted by x and y, respectively, and the layer thicknesses can be

expressed as in Equation (2.1).

xy

y

l

l

b

w

1 (2.1)

The band alignment of such a system is shown in Figure 2.4. The quantum

confinement is provided by the direct band gap in the Ge layer. Since the entire

quantum well system is strain balanced, the Ge quantum wells and the Si1-xGex

barriers are under compressive and tensile strain, respectively. So the heavy hole and

the light hole valence bands are no longer degenerate at the zone center. The dashed

lines in the Figure 2.4 indicate the band edges of the light hole bands. The valence

band offsets between strained Si1-xGex and relaxed Si1-yGey can be calculated by

Equation (2.2) and (2.3) [20]. With these two equations, we can further deduce the

valence band offsets between the well and the barrier.

, 0.74 0.07hhE x y y x y

(2.2)

2 3 2 3

2 3

2 3 2 3

2

, 0.3 0.289 0.142 0.683 2.58 3.21 1.24

0.354 3.77 8.79 2.460.435 0.704 2.439 1.295

1 2.7 28.1

lhE x y y y y y y y x

y y yy y y x x

y y

(2.3)

Furthermore, the conduction band offset can be calculated as follows.

hhvc ExE ,, )8.0175.4( . (2.5)

20

Various simulation techniques have been applied to this quantum well system,

including the tunneling resonance method [20, 21], the k.p method [22], the

variational method [23], and the tight binding method [24, 25].

Figure 2.4 Band alignment for the Ge/Si1-xGex quantum well system (published

in [20]).

2.3.2 QCSE in Ge/SiGe QW System

On the experimental side, two approaches to growing this quantum well system have

been successfully demonstrated, the reduced pressure chemical vapor deposition

(RPCVD) [18, 20] and the low-energy plasma enhanced chemical vapor deposition

(LEPECVD) [25, 26]. The QCSE has been observed in structures grown from both

approaches. Figure 2.5 shows the absorption spectra from our RPCVD grown samples

[18]. Compared with Figure 2.3, we can see that the change of the absorption

coefficient is comparable to that in the InGaAs/InP quantum well system. Unlike the

InGaAs/InP system, the QCSE in Ge/SiGe system has an indirect absorption edge

21

below the direct absorption edge due to the indirect gap nature of this material system.

This undesirable indirect absorption introduces additional loss in the “On” state and

increases the insertion loss of the optical modulator.

Figure 2.5 Absorption spectra for RPCVD grown Ge/SiGe quantum wells

(published in [18]

The temperature sensitivity of the QCSE in Ge/SiGe, or any quantum well system, is

fundamentally determined by the temperature dependence of the bandgap energy. As

we showed in [20], the absorption edge shifts toward longer wavelength with

increasing temperature at a rate of ~0.83 nm/oC (equivalently ~0.47meV/

oC). Due to

the quantum confinement, the absorption edge of the Ge/SiGe quantum well occurs

around 1450nm at room temperature, as shown in Figure 2.5. By increasing the

temperature to 90oC, the exciton peak can be shifted to wavelengths above 1.5 μm

without significant broadening. On the one hand, the temperature sensitivity of the

QCSE in Ge/SiGe quantum well system is not as large as that of ring resonator based

modulators. Devices based on this physical mechanism do not require precise

temperature tuning and stabilization. On the other hand, the moderate temperature

sensitivity that does exist in this material system gives us some extra flexibility in

designing and tuning the wavelength of operation of the device.

Unlike the FKE in bulk semiconductors, the absorption in quantum wells is

polarization dependent [27]. For optical electric field that is in the quantum well plane

22

(TE polarization), both the heavy hole and light hole to conduction band transitions

are allowed, while for optical electric field that is perpendicular to the quantum well

plane, i.e. parallel to the growth direction (TM polarization), only light hole to

conduction band transitions are allowed. For the Ge/SiGe quantum well system in

particular, the quantum confinement in the light hole valence band is weaker, as

shown by the dashed lines in Figure. 2.4. This polarization dependent absorption has

been observed and analyzed in [25, 28]. This polarization dependence has some

implications for the design of waveguide based optical modulators.

2.4 Optical Waveguides

2.4.1 EA Modulator Configurations: Surface Normal and

Waveguide

There are two configurations for an EA modulator, the surface normal modulator, and

the waveguide modulator. The schematics for both are illustrated in Figure. 2.6. In the

surface normal configuration, the light enters and exits the quantum well region

perpendicular to the substrate. Light enters and exits parallel to the substrate in the

waveguide based configuration. A figure of merit for an optical modulator is the

extinction ratio, which is defined as the ratio of the output optical power in the on state

and that in the off state. For a non-resonating EA modulator, the extinction ratio is

determined by the propagation length of the optical beam in the quantum well region

and the change in absorption coefficient between the on state and the off state, as

shown in Equation 2.5. For a given quantum well material system, the amount of

absorption change Δα under a given electric field swing is fixed. To increase the

extinction ratio of a modulator, the propagation length L needs to be increased. In the

surface normal configuration, the propagation length L is directly linked to the

epitaxial thickness of the quantum well d, while the two are completely independent of

each other in the waveguide configuration. This means that waveguide based QCSE

modulators can have a large contrast ratio with a very thin epitaxial structure of a

23

small number of quantum wells. Furthermore, by simply varying the device length

lithographically, we can make, out of exactly the same epitaxial structure, devices with

different extinction ratio and capacitance. The decoupling between the epitaxy

thickness and the propagation length in waveguide based modulators gives additional

flexibility and freedom in device design.

LeI

IER

L

off

on onoff

34.4)lg(10lg10)(

(2.5)

Figure 2.6 Two configurations for the optical modulator: surface normal based

(a) and the waveguide based (b).

There are two downsides for the waveguide based modulator. First of all, the

absorption of the quantum well structure is highly polarization dependent. For the

surface normal configuration, the electric field remains in the quantum well plane, i.e.

the TE polarization, while for the waveguide configuration, both TE and TM

polarizations are possible. The TM light will not be efficiently modulated due to the

weak confinement in the light hole band. Secondly, due to the unwanted indirect

absorption, the insertion loss also increases as the device length increases. For

example, for an absorption coefficient of 100 cm-1

, the optical power gets attenuated

by 10 dB though a propagation of 230 μm. Arguably, this is not only a disadvantage

for waveguide based modulators, since the same problem also exists for surface

24

normal based devices. And, moreover, given the strong absorption change from the

QCSE, long propagation distances in the quantum well region are not needed anyway.

2.4.2 SOI Waveguides

While strong QCSE in Ge/SiGe quantum wells makes this material very attractive for

EA optical modulation, it is too lossy for signal routing for distances longer than 100

μm. On the other hand, the lengths of global interconnects are on the scale of several

mm, if not longer. Fortunately, Si based waveguides have very low loss for

wavelengths above 1.3 μm, and can be used as the passive waveguide for signal

routing. Si-based waveguides were first initiated by R. A. Soref [29]. Thanks to the

availability of high quality SOI substrates [30], there has been a lot of work on SOI

waveguides. This is also the foundation for Si based optical ring resonators.

Figure 2.7 Schematics for rib waveguide (a) and wire waveguide (b).

There are two types of waveguides, the rib waveguide and the wire waveguide, both of

which are shown in Figure 2.7. Soref’s early work was on large cross-section rib

waveguides. By properly choosing the three parameters, the waveguide width w, rib

height tr and slab height ts, the rib waveguide can be single-moded while having a

cross section of several μm2[31]. This type of waveguide is very easy to fabricate and

couples easily to optical fibers. The optical confinement in the rib waveguide is

provided by the perturbation of the refractive index due to the presence of the rib. It is

a lightly confined system. The optical mode in rib waveguide resides mainly within

the Si region with limited overlap with the Si/Air interface. For this reason, the rib

25

waveguide is less sensitive to surface roughness and has lower loss than the wire

waveguide. The propagation loss in large cross section rib waveguides can be well

below 0.1 dB/cm for TE polarization [32, 33].

The optical confinement in the wire waveguide, on the other hand, is provided directly

by the Si/Air or Si/SiO2 interfaces, both of which have very high refractive index

contrast. To support a single mode, both the waveguide width w and the thickness t

have to be of the order of several hundred nanometers [34]. With such a small cross-

section, optical fields in the fundamental mode have a substantial overlap with the

surfaces. Thus, single mode wire waveguides are difficult to fabricate, sensitive to

sidewall roughness, and tricky to couple to optical fibers. However, they can be

densely packed, which may be essential for high density optical interconnect systems.

Typical propagation loss for this type of waveguide is ~2-3 dB/cm [2, 35].

In addition to low loss propagation, another important requirement for passive optical

waveguides is low loss bending. Guiding light to take turns is an essential

functionality for on-chip optical waveguides. Low bending loss and small bending

radius are preferred. In this respect, the wire waveguides excel in performance due to

the strong optical confinement. In single wire waveguides, the total bending loss for a

90o turn is negligible for bending radius larger than 5 μm [34]. For large cross section

waveguides, since the optical confinement is weak, a very large bending radius is

required, typically several millimeters, to obtain a relatively low bending loss [32, 36].

There is an engineering tradeoff: for low propagation loss, large cross section rib

waveguides with loose optical confinement are preferred, while wire waveguides are

favored for tight bending radius. As a compromise, small cross section rib waveguides

have been investigated lately [37, 38]. The height of this rib waveguide is similar to

wire waveguides, typically several hundred nanometers, while its width is similar to

that of large cross section rib waveguide. It can provide a decent bending radius (of

the order of 100 μm), while having a lower propagation loss than the wire waveguide

26

(for example 0.27 dB/cm as in [38]). In chapter 5, we use this type of waveguide to be

integrated with our Ge quantum well waveguide modulator.

2.5 Summary

In this chapter, we reviewed the technical background for this thesis. First, the band

structures of Si and Ge and their implications for the device components in the Si

photonics platform were discussed. Then we focused on the quantum well system and,

in particular, the QCSE in quantum well systems. Physical properties of Ge/SiGe

quantum well system were reviewed. In the end, different types of waveguides and

their characteristics, including profile, propagation loss, and bending radius, were

discussed.

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quantum-well structures on silicon,” Nature 437, 1334-1336 (2005).

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29

Si for optical modulators,” IEEE J. Sel. Top. Quantum Electron. 12, 1503-1513

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30. G. Celler and M. Wolf, “Smart CutTM

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Opt. Express 18, 14474-14479 (2010)

31

Chapter 3

Growth of Ge/SiGe Quantum

Wells

3.1 Introduction

This chapter focuses on the growth of Ge/SiGe quantum well system using RPCVD.

In the first half of the chapter, the growth of Ge/SiGe quantum wells on bulk Si

substrates will be addressed. Then in the second half, we focus on the selective

epitaxial growth of this material system on patterned Si substrates with SiO2 as the

mask.

3.2 Bulk Growth of Ge/SiGe QWs

In this section, I will briefly discuss our growth technique for Ge/SiGe quantum wells

on bulk Si substrates. First the growth structure and the growth conditions are

discussed. Some basic characterization techniques are reviewed. Then I discuss one of

our recent experiments attempting to reduce the relaxed buffer thickness. For those

who want to know more, our growth techniques, especially the thickness calibration,

dopant control, concentration calibration, and surface roughness reduction, have been

discussed in greater detail in two earlier theses [1, 2].

32

3.2.1 RPCVD growth of Ge QW

The epitaxial structure that we are interested in is a vertical p-i-n Si0.1Ge0.9 diode with

Ge/Si0.15Ge0.85 quantum wells in the intrinsic region. A schematic of the structure is

shown in Figure 3.1(a). The growth is carried out using a 4 inch cold wall Applied

Material CenturaTM

RP-CVD system at the Stanford Nanofabrication Facility. Silane

(SiH4), germane (GeH4), diborane (B2H6), and arsine (AsH3) are used as the reactant

gases, and hydrogen (H2) is used as the carrier gas. The chamber pressure is kept at 40

Torr (5332 Pa) during the entire growth.

As we discussed in Chapter 2, there is a 4% lattice mismatch between Si and Ge. To

grow the entire structure on top of the Si substrate, a relaxed Si0.1Ge0.9 buffer is

needed. To maintain 1D (i.e., layered) growth and avoid islanding, the growth

temperature is kept at 400oC. To fully relax the buffer layer, reduce the surface

roughness, and decrease the threading-defect density, several 800oC anneals lasting 20

min each are inserted during the buffer growth, similar to the multiple-hydrogen

anneal method [3]. Reducing the surface roughness for the buffer is crucial since any

roughness in this layer will translate to that of the quantum wells and increase the

inhomogeneous broadening of the exciton peaks in the absorption spectra.

33

Figure 3.1 (a). Schematic of the growth epitaxy: vertical p-i-n structure. (b).

Strain in the quantum well region (published in [1]).

The Ge/SiGe quantum wells are grown in the intrinsic region sandwiched between two

thin spacer regions to prevent dopant from migrating into the quantum well region.

The well thickness, barrier thickness, barrier Ge concentration, and buffer Ge

concentration are designed according to Equation 2.1 such that there is no net strain

for the epitaxy above the relaxed buffer. This also means that the Ge quantum well

and the SiGe barrier are under compressive and tensile strain, respectively, as

illustrated in Figure 3.1(b). Figure 3.2 is a cross section transmission electron

microscope (TEM) image of a grown sample. The heterostructure is planar and

uniform, indicating low surface roughness of the underlying buffer and good epitaxial

quality. Furthermore, very sharp boundaries between the Ge quantum well and the

SiGe barrier are achieved. The bottom p- and top n-regions are doped with boron (B)

and arsenic (As), respectively, to make electrical contacts.

Figure 3.2 TEM image of Ge/Si0.1Ge0.9 quantum wells

3.2.2 Characterization Techniques

34

Material characterization techniques that are relevant to study this quantum well

material system are scanning electron microscopy (SEM), transmission electron

microscopy (TEM), atomic force microscopy (AFM), secondary ion mass

spectrometry (SIMS), and X-ray diffraction (XRD).

The cross sectional SEM image can measure the overall structure thickness.

Furthermore, high resolution cross sectional SEM can provide us with a rough

estimate of the thicknesses of the individual quantum wells and barriers. Cross section

TEM can accurately measure the exact thicknesses of the quantum wells and the

barriers, although it takes a much longer time to prepare a sample for TEM compared

to that for SEM. TEM is also capable of measuring the threading dislocation density in

the film, which cannot be done by SEM. The AFM accurately measures the surface

roughness of the grown sample, and is useful for characterizing the buffer template as

well as the entire epitaxy. SIMS can reveal both the thickness and the concentration

information of each individual layer. A SIMS measurement for one of our grown

samples is shown in Figure 3.3. The concentrations of Ge and Si, as well as that of

dopants/impurities, can be measured directly using this technique. The oscillations in

the Ge and Si traces correspond to the grown quantum wells and barriers. XRD

provides a measure of the lattice constant of the substrate, lattice relaxed buffer, and

the degree of compressive and tensile strain in the quantum wells and barriers.

35

Figure 3.3 SIMS measurements for a grown sample with 10 Ge quantum wells

(measurement done at Evans Analytical Group).

In addition to the material characterization techniques, electrical measurements and

photocurrent measurements can provide further information. After the material

growth, p-i-n diodes can be fabricated from the grown epitaxy. This makes it possible

to carry out dark Current-Voltage (I-V) characteristic measurements, Capacitance-

Voltage (C-V) measurements, and photocurrent spectra measurements.

The dark I-V characteristic makes sure that diode rectifying behavior is obtained.

Furthermore, by comparing the magnitude of the reverse leakage current density of

different epitaxies at a given field, the relative threading dislocation density and hence

the quality of the epitaxy can be deduced [4]. C-V measurements can deduce the

unintentional background doping concentrations in the intrinsic region, which may be

well below the SIMS detection limits [5]. And, more importantly, since we are

36

interested in making optical modulators using this material system, the photocurrent

spectra measurements tell us within which wavelength range the extinction ratio is the

largest, and how large an extinction ratio is achieved. In this measurement, the device

is biased under reverse bias, while the output of a tunable laser is incident from the top

surface of the sample. The photocurrent in the diode is collected by a pre-amplifier

followed by a lock-in amplifier while the wavelength of the laser is scanned. Figure

2.5 shows one of our original photocurrent spectra collected in this material system.

3.2.3 Thin Buffer Exploration

There are two approaches to obtain a relaxed buffer on a Si substrate. One is the

graded buffer approach, where the Ge composition of the grown layer varies gradually

from zero to the desired final composition. Ge/SiGe quantum wells grown by

LEPECVD typically use this approach. To reach to the high Ge concentration SiGe

alloy, several tens of microns are needed. For example, in ref [6], the total buffer

thickness is 15 μm. By using a direct relaxed buffer approach, our buffer layer

thickness can be drastically reduced to several hundred of nanometers (typically

thicknesses are around 500 nm). However, compared to the thickness of the electronic

device layer and that of single mode SOI waveguides, this is still too thick. A thick

buffer takes a longer time to grow and, more importantly, is difficult to integrate with

other devices. On the other hand, reducing the buffer thickness increases the threading

dislocation density and degrades the overall epitaxy quality. Here, we want to

investigate how thin our relaxed buffer can be without significantly degrading the

device performance.

We carried out a sequence of growths while progressively reducing the buffer

thickness. The deposition time of the buffer varies according to the designed buffer

thickness, while all the other growth parameters are kept the same. Three 800oC 20

min anneals, are inserted into the buffer growth. For example, for a 180nm thick

Si0.1Ge0.9 buffer, the three anneals are carried out respectively after 60 nm, 120 nm,

and 180 nm buffer deposition. 10 pairs of Ge quantum wells are grown for each

37

sample. The thickness of the quantum wells and barriers are 12nm and 20 nm,

respectively. After the growth, the samples are cleaved for cross section and plane

view SEM inspection. P-i-n diodes are also fabricated to measure the photocurrent

spectra of the grown epitaxy.

Figure 3.4 Photocurrent spectra for a 10 pairs of Ge/SiGe on 150 nm relaxed

Si0.1Ge0.9 buffer.

The thinnest buffer that exhibits clear QCSE is 150 nm, the photocurrent spectra of

which are shown in Figure 3.4. Clear QCSE induced absorption change can be

identified. The cross section SEM and plane-view SEM of this sample are shown in

Figure 3.5. In Figure 3.5(a), we can see that the epitaxy, especially the quantum well

region, is reasonably planar. In the plane view image, some square surface pits can

already be identified. We believe that this is related to the increased threading

dislocation density.

This result also shows that the QCSE in Ge/SiGe quantum wells is not only a strong

physical mechanism, but also a robust one. Even with high threading dislocation

density and degraded epitaxial quality, strong absorption change, much stronger than

that due to the FKE in bulk Ge, can be obtained. However, we need to point out that

the exciton features in Figure 3.4 are not as clear as those in similar quantum wells

38

grown on 500 nm relaxed buffers. This can be easily seen by comparing Figure 3.4

with Figure 2.5. This may due to increased surface roughness and defect density.

Figure 3.5 Cross section (a) and plane view (b) SEM images of the quantum

well epitaxy grown with 150nm relaxed buffer.

For samples that are grown with a 50 nm thick buffer, the surface looks very rough to

the naked eye, and more surface pits show up in plane view SEM, as shown in Figure

3.6(b). In fact, the grown structure is not planar anymore. We cannot identify any

quantum well features in the cross section SEM, as shown in Figure 3.6(a). We tried

to fabricate a diode out of this epitaxy, but no rectifying behavior could be observed in

the dark I-V characteristic.

39

Figure 3.6 Cross section (a) and plane view (b) SEM images of the quantum

well epitaxy grown with 50nm relaxed buffer.

There is an obvious tradeoff between the relaxed buffer thickness and epitaxial

material quality. Reducing the relaxed buffer thickness increases the surface roughness

and defect density in the film. With our growth conditions, the thinnest relaxed buffer

with good QCSE absorption change is between 150 nm and 50 nm.

3.3 Selective Growth of Ge/SiGe QWs

3.3.1 Introduction and motivation

40

Before this work, all the previous work on Ge/SiGe quantum well systems was done

using planar epitaxial growth on unpatterned Si substrates. On the other hand, there

has been much work on selective epitaxial growth of pure Ge for nanoelectronic [7]

and photonic applications [8, 9]. Selective epitaxy deposits material at and only at

specified growth windows inside a dielectric mask. This can lead to great integration

flexibility and better process control, both of which are important for monolithically

integrating multiple devices with different epitaxy designs and hence functionalities

on the same substrate.

Moreover, selective epitaxial growth can improve the material quality of the grown

epitaxy. The presence of the dielectric mask around the reduced growth areas

terminates the propagation of misfit dislocations, reduces the possibility of dislocation

interactions/multiplications, and hence decreases the threading dislocation density [10,

11]. Furthermore, if the growth film has a thickness larger than the width of the

growth window (i.e. aspect ratio>1), all the threading dislocations terminate at the

dielectric mask. Heteroeptiaxial film with very low defect density can be achieved,

which is known as “epitaxial necking” or “aspect ratio trapping” [12, 13].

3.3.2 Experimental Details

We start with a 100mm-diameter, (100)-oriented silicon substrate lightly doped with

boron (10~20 Ω-cm), and thermally grow a 1.5μm thick SiO2 layer at 1100oC. Part of

this oxide will act as the growth mask for later epitaxial growth. Various windows

with different widths along the [110] direction are patterned using I-line optical

lithography. Reactive ion etching is used to etch the majority of the oxide thickness

(1.45μm). Then a 20:1 buffered oxide wet etch (BOE) is used to remove the remaining

50nm oxide in the growth window. The combination of dry etch and wet etch helps to

avoid any potential plasma damage to the underlying crystalline Si in the growth

window and is crucial for the quality of the subsequent epitaxial materials [14]. The

process flow for substrate preparation is shown in Figure 3.7. The patterned substrate

then goes through an “HF-last” RCA clean, and is immediately loaded into an Applied

41

Materials CenturaTM

RP-CVD system. The growth conditions and parameters are

similar to those of the bulk growth. The schematic of the grown sample, together with

the relevant crystal planes are shown in Figure 3.8.

Figure 3.7 Process flow for the template preparation for selective growth

Figure 3.8 Schematic of the grown sample with relevant crystal planes.

After the growth, cross section SEM is used to investigate the selectivity, film

thickness and faceting of the epitaxy. As shown in Figure 3.9(a), a planar

heterostructure with very sharp boundaries between the Ge quantum wells and the

Si0.15Ge0.85 barriers is grown at locations away from the growth window boundary

42

[15]. The total thickness of the epitaxial layer is 1.15μm. Faceted growth occurs in the

growth window next to the oxide mask, as shown in Figure 3.9(b). The faceted region

extends about 700nm from the mask edge. No nucleation occurs on top of the oxide

mask, as indicated in Figure 3.9(b). Optical microscope inspection also confirms that

no deposition takes place on the mask, demonstrating perfect selectivity between the

growth window and the oxide mask. Furthermore, just away from the faceted region,

planar quantum-well structures, of the same thickness as in the region far away from

the boundary, are grown.

43

Figure 3.9 Cross section SEM for the selectively grown epitaxy with 10 pairs of

Ge/SiGe quantum wells: (a). at positions far away from the growth

window/mask boundary; (b). at the growth window/mask boundary

44

3.3.3 Growth Dependence on Pattern

For selective growth, an important consideration is the sensitivity of the growth to the

size, shape and spacing of the growth holes in the mask. Adatoms of the reactant

species can diffuse from the masked area into the growth window, resulting in

different growth rates for different growth window sizes (i.e. the “local loading

effect”) [16]. Figure 3.10 illustrates the gas dynamics close to the surface of the

patterned substrates.

Figure 3.10 Gas dynamics close to the surface of a patterned substrate (courtesy

of T. I. Kamins)

For quantum well structures, the thickness of each layer, especially those of the

quantum wells and the barriers, determines the wavelength of operation for the QCSE

modulator, and hence is of critical importance. Figure 3.11 examines the epitaxy

grown in isolated trenches of various widths. The flat regions of the grown epitaxy in

wide trenches are of the same thickness, within SEM measurement accuracy.

Moreover, the two faceted regions at the boundaries are of exactly the same width and

have the same angle with respect to the substrate independent of trench width beyond

2μm. For trenches that are narrower than 1μm, the two faceted regions join at the top,

and the grown film is thinner.

45

Figure 3.11 Cross section SEM images of the grown selective epitaxy in various

window sizes: (a). 10 μm, scale bar: 2 μm; (b). 5 μm, scale bar: 2 μm; (c). 2 μm,

scale bar: 1 μm; (d). 1 μm, scale bar: 500 nm.

Furthermore, we investigated the thickness dependence of the grown film on the mask

coverage percentage, which is shown in Figure 3.12 and Figure 3.13. In this case, the

window size is kept constant (5 μm in Figure 3.12, and 1 μm in Figure 3.13), while

the mask oxide width between adjacent growth windows is varied from very large

down to 500 nm. Again, the grown film thickness does not depend on the mask

coverage percentage, within the measurement accuracy. In other words, under our

growth conditions, the selective growth shows no observable loading effect.

46

Figure 3.12 Cross section SEM images of the grown selective epitaxy with

different oxide coverage percentage for 5 μm wide trenches.

47

Figure 3.13 Cross section SEM images of the grown selective epitaxy with

different oxide coverage percentage for 1 μm wide trenches.

3.3.4 Growth Dependence on Temperature

As we show in Figure 3.9(b), facets are grown at the boundary between the mask and

the growth window. In general, faceting occurs when the grown epitaxy is allowed to

reach its free energy minimum (thermodynamic equilibrium), or when growth in

certain crystal orientations is constrained (kinetics limited) [17]. For our growth

conditions, in particular, the kinetics limited faceting dominates. The facet angles and

the epitaxy crystal shape are determined by the relative growth rates of various crystal

planes [18]. For selective epitaxy of bulk Ge, the facet region can be removed by using

a chemical mechanical polishing (CMP) step after the growth [7, 19]. After the CMP

step, the planarized epitaxy performs the same as if no faceting had occurred. This is

not the case for our selective epitaxy of quantum well heterostructures. As shown in

Figure 3.9(b) and Figure 3.13(a), the quantum wells are tilted in the faceted region.

The thicknesses of the quantum wells and barriers in the faceted region are smaller

than that in the flat region. So even if a CMP step is carried out to planarize the grown

epitaxy, the faceting region still impacts the device performance, at least to some

degree.

Figure 3.14 shows the growth facets at 380oC, 400

oC and 420

oC. Various angles show

up at different growth temperatures, corresponding to different crystalline planes,

which are summarized in Table 3.1.

48

Figure 3.14 Selective growth at different temperatures

Table 3.1 Summary of the faceting planes at different temperatures

Temperature Dominant Facets

380oC <211>

400oC <111>, <311>

420oC <111>, <211>

In principle, with the prior knowledge of the growth rate of different crystal planes,

the grown crystal shape can be predicted through Wulff construction. We believe that

the different faceting behavior at different temperatures results from the variation of

the relative growth rates for various crystal planes. However, due to the complexity of

the heterostructures, we do not attempt to predict or explain the faceting behavior of

the grown epitaxy at different temperatures. Rather, from a device design perspective,

we are interested in the width of the faceting region, and the dependence of this width

on growth temperature fluctuations. From our experiments, we find that even though

different facets show up within a ±20 oC variation around 400

oC, the faceting regions

are of similar width. For our grown 1.15 μm epitaxy, the faceting region is less than 1

μm wide.

In the end, we want to note that recent results from IMEC show that the faceting

region in Ge selective epitaxy can be avoided completely by growing at very low

temperature [20]. It would be interesting if we could use similar techniques to achieve

facet-free heterostructure Ge/SiGe quantum wells.

3.4 Conclusions

49

In this chapter, we discussed the growth aspect of Ge/SiGe quantum wells on Si

substrates using RP-CVD. The growth conditions and various material

characterization techniques are first addressed. Then a thin buffer quantum well

growth experiment is discussed. With a reduced relaxed buffer of only 150 nm,

photocurrent spectra exhibit clear QCSE features, while the exciton peaks are smeared

out due to some degradation of material quality. Finally, we discussed our

investigation on selective epitaxial growth of this material system on patterned

substrates. Experimental results show that complete selectivity can be achieved with

thermal SiO2 as the masking material. The selective growth shows minimal pattern

dependence. Faceted growth takes place at the boundary between the growth window

and the oxide mask. We also investigated the faceting behavior at different

temperatures around 400oC.

References

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5. R. K. Schaevitz, J. E. Roth, S. Ren, O. Fidaner, and D. A. B. Miller, “Material

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13. J. S. Park, J. Bai, M. Curtin, B. Adekore, M. Carroll, and A. Lochtefeld,

“Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates

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53

Chapter 4

Thin Dielectric Spacer for

Monolithic Integration

4.1 Introduction

In this chapter, we discuss a novel thin dielectric spacer for monolithically integrating

Ge/SiGe quantum wells with SOI waveguides through direct butt coupling. First, the

necessity of such a spacer is discussed. Then, numerical calculations are carried out to

understand the impact of this spacer on the overall device performance. Finally, a

dual-layer fabrication process is proposed and demonstrated to build this thin spacer

layer with precise thickness control.

4.2 Integration Schemes and Motivations for

Dielectric Spacers

4.2.1 Integration Schemes

As discussed in Chapter 2, waveguides based on Ge/SiGe quantum wells are too lossy

for long distance propagation. So, it is necessary to integrate Ge/SiGe waveguide

modulators with low-loss waveguides, such as SOI passive waveguides. Similar

54

integration is desirable for waveguide-based Ge photodetectors. In the following

discussion, we will be considering both Ge/SiGe and Ge structures when referring to

the Ge active section unless explicitly specified.

The incorporation of the active section into an SOI waveguide can be realized through

the selective epitaxial growth from an underlying crystalline Si template. The coupling

between the active section and the passive waveguide can be realized by two different

approaches. In the first approach, a Ge layer is grown directly on top of the top

crystalline Si layer of the SOI substrate [1, 2]. In this scheme, coupling is realized

through evanescent coupling using adiabatic tapers. For waveguide photodetectors,

only one taper is needed, while two tapers, one at the entrance port and one at the exit

port, are required for waveguide modulators. These adiabatic tapers are at least several

microns long. Consequently, devices in this category have a large footprint.

Furthermore, if the taper is realized in the Ge active section, the devices also have a

large capacitance. In the second approach, a recess is defined in the top Si layer of the

SOI substrate, a Ge is selectively grown starting from the remaining crystalline Si

inside the recess [3, 4]. The Ge active section and the SOI waveguide are at the same

vertical level. In this scheme, the coupling between the two is realized through direct

butt coupling. The devices in this category can be very compact and wavelength

insensitive since adiabatic tapering is not needed. The sacrifices here are additional

insertion loss and back reflection due to the refractive index mismatch. For short

distance inter- and intra-chip interconnect applications, where small device footprint is

necessary and some insertion loss can be tolerated, this second approach with the

direct-butt coupling is preferred over the evanescent coupling approach. We choose to

integrate Ge/SiGe quantum wells with SOI waveguides using direct butt coupling.

4.2.2 Motivations for Dielectric Spacer

The simplest selective epitaxial growth scheme for the second approach is illustrated

in Figure 4.1(a). As indicated by the black arrows in the figure, the epitaxial growth

will occur from the exposed crystalline Si, both vertically from the bottom of the

55

recess and laterally from the exposed Si facets. More seriously, if the two exposed

vertical facet are of (100) growth planes, the lateral and vertical growth will be of

exactly the same growth rate.

This lateral growth is unwanted, and imposes two serious limitations. First of all,

depending on the relative growth rate of the vertical and lateral growth, the grown

epitaxy will be irregular and difficult to predict. At the location where the vertical

growth adjoins with the lateral growth, misfit dislocations and/or voids can take place,

resulting in poor epitaxy quality and device performance [5]. This also makes it

impossible to grow planar heterostructures, such as Ge/SiGe quantum wells. Even for

bulk Ge growth, a chemical-mechanical polishing (CMP) step is required after the

selective epitaxy to planarize the structure.

Figure 4.1 The selective growth with a silicon recess, and without the spacer.

(a). Growth template (black dashed arrows indicate the directions of the

selective growth); (b). The grown film of relatively unpredictable shape, shown

also with the consequences of in-situ doping.

56

Secondly, for many applications, such as photodetectors and EA modulators, a vertical

p-i-n structure is needed. If in-situ doping is carried out during the selective epitaxy

step, the lateral growth of the doped layer will electrically short the intrinsic region.

Figure 4.1(b) illustrates the case if in-situ doping were carried out during the selective

epitaxy. The common work-around is to dope the starting thin Si template through ion

implantation followed by rapid thermal anneal (RTA) instead [1, 2, 3, 4]. However,

ion-implantation can generate crystalline defects in the growth template, which will

degrade the quality of the subsequent growth. High temperature anneal (RTA)

imposes additional thermal budget restrictions on the CMOS circuitry, if the CMOS

circuitry is to be integrated together with the optical interconnects. Furthermore, recent

work [6] shows that higher activated doping level and sharper transition boundary

between the doped and intrinsic regions can be achieved in in-situ doped Ge, both of

which are of great importance for high speed devices.

To avoid the unwanted lateral growth and potential problems for in-situ doping of

structures, we propose inserting a dielectric insulating spacer layer at the sidewall of

the growth window. The most commonly used insulating dielectric in the CMOS

technology platform is SiO2. Figure 4.2(a) illustrates the growth template with the

spacers on both sides of the exposed crystalline Si facet. With the spacer in place, the

lateral growth will not initiate, and hence is inhibited. This makes it possible to

achieve in-situ doping for bulk Ge active sections, as in Fig. 4.2(d), and more

importantly, to grow planar Ge/SiGe quantum well structures in the active section.

Note that faceted growth may occur at the boundary of the growth window depending

on the growth conditions, as shown in Chapter 3. But this faceting region is narrow in

width, and can be controlled.

57

Figure 4.2 The selective growth with a silicon recess, and the dielectric spacer.

(a). Growth template; (b). The grown epitaxy.

One subtle difference between growing pure Ge and Ge/SiGe quantum wells is that

the active Ge/SiGe quantum wells need to be grown on a relaxed buffer of several

hundred nanometers thickness so that there is no net built-in strain. In Chapter 3, we

showed that at least a 150 nm relaxed buffer is needed. On the other hand, the top Si

layer for most SOI waveguides is only around 300 nm thick. To accommodate this

relaxed buffer, the buried oxide (BOX) layer in the growth window (typically 1 μm or

more in thickness to prevent substrate coupling) can be removed before the selective

growth, as shown in Figure 4.3(a). The growth will then start from the top surface of

the handle Si substrate of the SOI wafer. There is an additional benefit of using this

approach. While the majority of the BOX can be removed by reactive ion etch (RIE)

to maintain a vertical sidewall, wet hydrofluoric acid (HF) can be used to remove the

bottom oxide right above the handle substrate. This avoids any dry-etching induced

damage, preserves the crystal quality of underlying the crystalline silicon, and hence

improves the epitaxy quality of the grown film. Some Si or low percentage SiGe alloy

58

can be selectively grown to fill up part of the BOX region, and can act as the bottom

cladding in the active section.

Figure 4.3 The selective growth with the dielectric spacer and BOX removed.

(a). Growth template; (b). The grown epitaxy of a p-i-n SiGe diode with Ge

quantum wells in the intrinsic region.

In the end, we want to note that, on the surface, the dielectric spacer that we are

proposing here looks somewhat similar to the spacer that is already widely used in

advanced CMOS platforms to achieve elevated self-aligned source/drain [7] and

FinFET structures [8, 9]. However, the purpose of the spacer here is quite different

from those used in the CMOS platform. The fabrication requirements for the two

spacers are also drastically different. The CMOS spacers are standalone structures, the

main purpose of which is to achieve a self-aligned structure with feature sizes that

cannot be easily defined lithographically. The device area of interest consists of fine

structures that are defined right beneath the spacer. The dielectric spacers in this

thesis, on the other hand, are deposited on the sides of SOI waveguide facets. Their

main purpose is to eliminate the lateral growth during the selective epitaxy. The

device area of interest here is inside the growth window next to the dielectric spacers,

where the subsequent selective epitaxy takes place.

59

4.3 Numerical Analysis

There is a large difference in refractive index between Si (3.52) and SiO2 (1.455)

around 1.55 μm. The introduction such a SiO2 spacer layer into the structure will

inevitably cause some insertion loss penalty. In this section, we study this insertion

loss in detail. To evaluate the insertion loss due to the spacer only, i.e. not that from

the index/mode mismatch between the SOI waveguide and the active section, we first

evaluate the coupling from SOI waveguide to spacer, and then back to the SOI

waveguide, as illustrated in Fig. 4.4. First, we give a 1-D analytical model using the

transfer matrix method in the ray-optics picture to gain some physical intuition. Then

the full-wave 3-dimensional finite-difference time-domain method (3D-FDTD) is used

to quantify the insertion loss numerically.

-

Figure 4.4 Schematic of the problem setup: propagation through two SOI

waveguide sections with a SiO2 spacer in between.

4.3.1 Transfer Matrix Method Analysis

In the ray-optics picture, modes in optical waveguide can be considered as the

superposition of plane waves at various different incidence angles. Each plane wave

component with wavevector (kx, ky, kz) can be expressed as Equation (4.1).

(4.1)

60

Under the paraxial approximation [10], we have,

(4.2)

(4.3)

(4.4)

(4.5)

(4.6)

The waveguide mode, , can be decomposed into plane wave components

through Fourier transformation, as shown in Equation (4.7).

(4.7)

The special frequency distribution can be evaluated using the inverse

Fourier transform:

(4.8)

61

Each plane wave component experiences total internal reflection (TIR), when hitting

the boundaries between the core and the claddings of the waveguide. The ray picture

of the waveguide modes is illustrated in Figure 4.5.

Figure 4.5 Modes in the optical waveguide: the ray-optics picture

Figure 4.6 Simplified 1D model for a plane wave component with incidence

angle θ.

Neglecting the Goos–Hänchen shift, the propagation of each plane wave component

can be treated as that in a uniform medium with a refractive index of the waveguide

core. For each plane wave component, as shown in Figure 4.6, the problem of

transmission through the SiO2 spacer can be treated by the well-known transfer matrix

method [11]. In particular, for the simple 3-layer problem, the reflection coefficient

can be evaluated analytically as:

(4.9)

62

where kz0, kz1, kz2 are the z-components of the wavevector in Si, SiO2, and Si,

respectively; and d is the thickness of the SiO2 spacer layer, as indicated in Figure 4.6.

We evaluate the behavior at λ=1.55 μm. Using Equation (4.9), the reflection

coefficient for different incidence angles has been plotted with different spacer layer

thicknesses in Figure 4.7. For thicknesses below 200 nm, the reflection coefficient

increases monotonically with increasing incidence angle and increasing spacer layer

thickness. We should note that the TIR angle between Si and SiO2 is . So

relevant plane wave incidence angles are: . For spacer layer

below 20 nm, the reflection coefficient in this angular range is less than 0.3,

corresponding to less than 10% reflected optical power. For ,

frustrated total internal reflection takes place for thicknesses less than 200 nm, while

TIR occurs for thicknesses larger than 500nm. For thick spacers, there exist reflection

dips due to interference, but this is only for a very narrow incidence angle range.

Figure 4.7 Reflection coefficient evaluated for various angles at different spacer

thicknesses.

63

The analysis indicates that for a very thin spacer layer, very low reflection occurs for

all angles, even beyond the TIR angle. Each plane wave component of the waveguide

mode experiences a small reflection at the Si-SiO2 interface. Since the waveguide

mode can be reconstructed by combining these plane wave components using

Equation (4.7), we expect the waveguide mode also experiences small reflection with

the presence of very thin SiO2 spacers.

4.3.2 FDTD analysis

Of course, the above 2D slab mode analysis within the ray optics picture is somewhat

naïve. Though it can simulate the behavior of a beam the size of the original

waveguide mode as it interacts with a slab approximating the (vertical) dielectric

spacer layer, it does not include the actual physical effects of reflections at the

horizontal waveguide core/cladding layer boundaries (as opposed to the vertical

boundaries at the spacer layer surfaces).To quantitatively evaluate the insertion loss in

a tightly confined SOI wire waveguide, the full-wave 3-D FDTD method is used [8].

In the analysis, we choose to use the widely used single-mode SOI wire waveguide

with a 500 nm width and a 300 nm height. We assume that the entire space is filled

with SiO2, with a Si core in the middle. This corresponds to the case when thick BOX

and upper oxide cladding are used. The fundamental mode for such a waveguide at

1.55 μm is quasi-TE polarized, with major electrical field component parallel to the

substrate. The inset of Figure 4.8 shows the mode profile of this mode.

64

Figure 4.8 Transmitted, scattered, and reflected optical power percentage for

different spacer thicknesses. Inset: mode profile of the fundamental quasi-TE

mode for a 500nm wide and 300nm thick SOI waveguide.

This fundamental mode is launched from the entrance SOI waveguide (left hand side

in Figure 4.9(a)-(d)), transmitted through the SiO2 spacer, and then into the exit SOI

waveguide (right hand side in Figure 4.9(a)-(d)). The grid size in the propagation

direction is chosen to be 1 nm, fine enough for the thinnest spacer of 10nm.

Transmitted, scattered, and reflected optical power are calculated numerically and

normalized to the incident optical power. The computed results are shown in Figure

4.8. The corresponding electrical field distributions in the middle plane cross section

of the SOI waveguide for different spacer thicknesses are shown in Figure 4.9(a)-(d).

65

Figure 4.9 Electrical field distribution for different spacer thicknesses in the

cross section plane along the dashed line in Figure 4.4

We can see that the transmission for a 20nm spacer is more than 97%, equivalent to an

insertion loss of 0.13dB. More than 90% of optical power can be transmitted for

spacers thinner than 50nm (less than 0.46dB insertion loss). This high transmitted

optical power corresponds to an almost perfect transmission, as shown in Figure

4.10(a) and Figure 4.10(b). As the spacer thickness increases, the scattered power and

reflected optical power increase, while the transmitted optical power decreases. This

can also be seen in Figure 4.10(c) and Figure 4.10(d), where the transmission is

seriously disturbed, and a significant amount of the optical power is reflected back

into the entrance waveguide or scattered into the substrate or waveguide cladding.

In summary, our analytical transfer matrix method agrees qualitatively with the full

wave 3D-FDTD analysis. A thinner spacer layer is desired to reduce the reflection and

the insertion loss. For spacers less than 20nm, the insertion loss penalty can be lower

than 0.13dB.

4.4 Spacer Fabrication Process

66

As shown in the previous section, the thickness of the spacer layer is a critical

parameter. First of all, the thinner the spacer layer is, the lower the insertion loss.

Secondly, any variations in the spacer thickness directly translate to variations of the

insertion loss of the devices. So, reliably and uniformly fabricating this very thin

spacer is crucial. Since epitaxial growth will be carried out after the spacer fabrication,

the very thin spacer has to be formed on and only on the vertical facet sidewall, but

not on top of the growth window. Furthermore, it is highly desirable that no additional

damage be done to the growth window due to the fabrication of the spacer.

One straightforward way to fabricate the spacer is to deposit conformal SiO2 on the

surface of the patterned substrate and dry etch the oxide anisotropically so that it is

cleared on top of the growth window, but remains on the sidewall. This process,

however, is not optimal for two reasons. First of all, to remove the oxide completely

inside the growth window over the entire wafer, some over-etch is needed. This over-

etch will introduce damage and degrade the crystalline quality of the growth window.

Secondly, non-uniformity and loading effects in the dry etching step will cause

variations of the spacer thickness. To achieve uniform spacer thickness across the

wafer therefore requires fine tuning of the dry etching process and the growth window

pattern of the patterned substrate, both of which are tricky and undesirable.

In this section, we will demonstrate a robust fabrication process to realize a very thin

sub-30 nm thick SiO2 spacer with precise thickness and uniformity control. The key

components of this process are a sacrificial Si3N4 layer and highly anisotropic nitride

dry etching.

67

Figure 4.10 Process flow for the thin spacer fabrication

Figure 4.10 illustrates the detailed process flow for thin spacer fabrication. Starting

with a SOI substrate we first etch the top Si layer and the majority of the BOX, using

reactive ion etching (RIE). Then HF wet etch is used to remove the final thin BOX,

reaching the handle Si substrate. A conformal SiO2 layer is then deposited by low-

pressure chemical vapor deposition (LPCVD) and densified. The thickness of this

SiO2 layer can be accurately controlled by the deposition time. It will determine the

final thickness of the SiO2 sidewall spacer. Figure 4.11 is a cross section SEM image

of a Si trench after depositing a 40 nm SiO2 layer, showing good conformal coverage

over the steps.

68

Figure 4.11 Cross section image of a Si trench after depositing a 40 nm SiO2

layer.

Following that, a conformal stoichiometric silicon nitride (Si3N4) layer is deposited,

also by LPCVD. A highly anisotropic RIE is used to etch the nitride on the top surface

of the growth window, stopping on the underlying deposited SiO2. Due to the etching

anisotropy, a Si3N4 spacer will result on the sidewall. In practice, this etching step can

be accurately controlled by using an end point detector, so that it can be stopped right

after the underlying deposited SiO2 is exposed to the etching plasma. Some over-etch

can be afforded as long as no underlying Si is exposed. Figure 4.12 illustrates an

example of the end point detector response during a nitride dry etching step. As the

SiO2 becomes exposed to the etching plasma, the end point signal significantly

decreases. The process can be stopped after the signal reaches the flat region. A HF

wet etch then removes the deposited SiO2 inside the growth window only. The Si3N4

spacer protects the SiO2 on the sidewall facet from etching during this step. Finally, a

selective wet etch, hot phosphoric acid, is used to remove the Si3N4 spacer. The entire

fabrication process is described in Appendix I in full detail.

69

Figure 4.12 End point detection for the nitride dry etch, stopping at the

underlying oxide.

Thanks to the sacrificial Si3N4, the spacer thickness can be precisely controlled. And,

more importantly, very good uniformity can be achieved across the entire wafer

without the necessity of fine tuning the dry etching process. Moreover, we designed

the process such that no direct etching plasma hits the surface of the crystalline Si in

the growth window, hence avoiding any additional damage due to the fabrication of

this spacer. Note that, in the process flow, we choose to remove the BOX layer. For

applications where a Si recess in the top Si layer is used, only steps d-g in Figure 4.10

are needed. Using this process, we fabricated a 22 nm SiO2 spacer on a sloped Si

sidewall of approximately 80o, as shown in Figure 4.13. This also shows that a perfect

90o sidewall facet is not essential to this fabrication process.

70

Figure 4.13 Cross section SEM image, showing a 22nm SiO2 spacer on a

sidewall with 80o slope.

4.5 Discussions and Conclusions

Our motivation for the spacer is for the monolithic integration of p-i-n bulk Ge or

Ge/SiGe quantum wells active sections with the SOI waveguide platform. However,

the use of this spacer is, by no means, limited to these applications. Monolithic

integration in III-V material systems has, for a long time, attracted substantial research

interest. Various approaches, such as selective epitaxial growth/regrowth, offset

quantum well growth, and quantum well intermixing, have been successfully

demonstrated [13]. This thin spacer with selective epitaxial growth adds yet another

trick to the existing toolkit. For example, this thin spacer layer can replace proton

implantation to provide the electrical isolation and current confinement for III-V edge

emitting lasers coupled to passive waveguides. Although our numerical analysis is

done for the coupling between two SOI wire waveguides with a SiO2 spacer in

between, we expect similar conclusions in other types of waveguide systems.

Furthermore, in our fabrication approach, we chose SiO2 as the spacer material, and

Si3N4 as the sacrificial material, since these two materials are the most commonly used

71

dielectrics in the CMOS platform. This dual-layer spacer fabrication approach is quite

general, and should also apply to other dielectric materials. For example, Ge

oxynitrides, or Ge oxide might be preferred as the spacer material to provide better

passivation for the subsequently grown Ge epitaxy [14, 15]. Moreover, the recent

progress on atomic layer deposition techniques for dielectric materials can lead to

even more precise control of the spacer thickness.

In conclusion, we discussed various approaches to integrate p-i-n bulk Ge or Ge/SiGe

quantum wells active sections with the SOI waveguide. We proposed an insulating

dielectric spacer to be inserted at the sidewall facet of the SOI waveguide to prevent

unwanted lateral growth. Through numerical calculation, we show that the additional

insertion loss penalty can be as low as 0.13dB for spacers thinner than 20nm. A robust

fabrication process using a sacrificial nitride layer is proposed and demonstrated to

realize such thin spacer layers with precise thickness control and excellent uniformity.

References

1. N. Feng, P. Dong, D. Zheng, S. Liao, H. Liang, R. Shafiiha, D. Feng, G. Li, J.

E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, "Vertical p-i-n

germanium photodetector with high external responsivity integrated with large

core Si waveguides," Opt. Express 18, 96-101 (2010).

2. J. Liu, M. Beals, A. Pomerene, S. Bernardis, R. Sun, J. Cheng, L. C. Kimerling,

and J. Michel, "Waveguide-integrated, ultralow-energy GeSi electro-

absorption modulators," Nat Photon 2, 433-437 (2008).

3. D. Feng, S. Liao, P. Dong, N. Feng, H. Liang, D. Zheng, C. Kung, J. Fong, R.

Shafiiha, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, "High-speed

72

Ge photodetector monolithically integrated with large cross-section silicon-on-

insulator waveguide," Appl. Phys. Lett. 95, 261105 (2009).

4. L. Vivien, J. Osmond, J. Fedeli, D. Marris-Morini, P. Crozat, J. Damlencourt, E.

Cassan, Y. Lecunff, and S. Laval, "42 GHz p.i.n Germanium photodetector

integrated in a silicon-on-insulator waveguide," Opt. Express 17, 6252-6257

(2009).

5. H. Yu, S. Cheng, J. Park, A. Okyay, M. Onbasli, B. Ercan, Y. Nishi, and S.

Saraswat, “High quality single-crystal germanium-on-insulator on bulk Si

substrates based on multistep lateral over-growth with hydrogen annealing,”

Appl. Phys. Lett. 97, 063503 (2010).

6. H. Yu, S. Cheng, P. Griffin, Y. Nishi, and K. C. Saraswat, "Germanium in situ

doped epitaxial growth on Si for high-performance n+/p-junction diode," IEEE

Electr. Device L. 30, 1002-1004 (2009).

7. J. R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson,

“A self-aligned elevated source/drain MOSFET,” IEEE Electr. Device L. 11,

365-367 (1990).

8. Y. Choi, T. King, and C. Hu, “Nanoscale CMOS spacer FinFET for the terabit

era,” IEEE Electr. L. 23, 25-27 (2002).

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scalable, vertical double-gate MOSFET using novel processes,” IEEE T.

Electron. Dev. 55, 632-639 (2008).

10. A. E. Siegman, Lasers (University Science Books, 1986)

11. H. A. Haus, Waves and Fields in Optoelectronics (Prentice Hall, New Jersey,

1983).

73

12. A. Taflove and S. C. Hagness, Computational Electrodynamics: The Finite

Difference Domain Method, (Artech, Boston, 1995)

13. E. Skogen, J. Raring, G. Morrison, C. Wang, V. Lal, M. Masanovic, and L.

Coldren, "Monolithically integrated active components: a quantum-well

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(2005).

14. C. O. Chui, F. Ito, and K. C. Saraswat, "Nanoscale germanium MOS

Dielectrics-part I: germanium oxynitrides," IEEE T. Electron. Dev. 53, 1501-

1508 (2006).

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75

Chapter 5

Ge/SiGe Quantum Well

Waveguide Modulator

Integrated with SOI

Waveguides

5.1 Introduction

Recently, CMOS compatible Ge photodetectors integrated with SOI waveguides have

been extensively investigated by several groups, demonstrating high quantum

efficiency, low drive voltage, high frequency operation, and/or avalanche gain [1, 2, 3,

4, 5]. A Franz-Keldysh effect based bulk GeSi modulator, built on the same SOI

waveguide platform, has also been demonstrated [6]. Integrating QCSE based

Ge/SiGe quantum well waveguide modulator with SOI waveguides can further

improve the modulator device performance.

In the previous two chapters, we explored the selective epitaxial growth of Ge/SiGe

quantum wells and studied a dielectric spacer to integrate them with the SOI

waveguides. In this section, we present such a device: a Ge/SiGe quantum well

waveguide modulator integrated with small cross section SOI rib waveguides. First, I

76

will discuss the potential performance of waveguide modulators in this category, and

some considerations of the device design. Then the fabrication process of this device

will be discussed. Experimental results will be discussed afterwards. We will conclude

this chapter by proposing and analyzing a similar Ge quantum well QCSE waveguide

modulator integrated with large cross section SOI waveguides.

5.2 Device Design

As stated in Chapter 4, we choose to integrate the Ge/SiGe quantum wells with the

SOI waveguides through direct butt coupling. The overall device concept is illustrated

in Figure 5.1. SOI based waveguides are used for routing optical signals on chip,

while the Ge/SiGe quantum well active section is used to transform the electrical

signal into optical signal.

Figure 5.1 Schematic for overall device concept.

5.2.1 Idealized Device Performance Predictions

In this section, we want to do some back-of-envelope calculations to evaluate the

potential performance of this integrated Ge/SiGe quantum well waveguide modulator.

77

As a starting point, we start with the absorption spectra in Ref [7], where we, for the

first time, observed the QCSE in Ge quantum wells. From the absorption spectra, we

can deduce the absorption coefficient ratio under a 1 V signal swing, which is plotted

in Figure 5.2. We can see that the largest absorption coefficient ratio is 2.50,

occurring for 4 V/3 V at 1462 nm wavelength. The corresponding absorption

coefficients are 1010 cm-1

and 2520 cm-1

, for 3 V and 4V respectively. The 3V bias is

the normally transmitting state, while the 4V bias is the normally absorbing state.

Figure 5.2 Absorption coefficient ratio with a 1 V swing

Assuming unity overlap between the optical beam and the quantum well region and

substituting these absorption coefficient values into Equation (2.5), we can calculate

the needed propagation length for a 3 dB extinction ratio.

(5.1)

78

Only a 4.58 μm long section is needed for a 3 dB extinction ratio. The associated loss

in the “transmitting” state can then be calculated as

(5.2)

The total insertion loss of this device should also include that due to the dielectric

spacers. Assuming 20 nm thick spacers are used, the additional insertion loss due to

the two spacers is 0.26 dB. So the total insertion loss for this quantum well

waveguide modulator is 2.27 dB.

In practice, an extinction ratio higher than 3 dB may be desired. Also, keeping in

mind that our selective epitaxial growth has two faceted regions at the growth

window boundary, a slightly longer active section may be needed. For the sake of

estimation here, we assume that the Ge/SiGe waveguide modulator is 10 μm long.

Furthermore, since the typical single mode SOI waveguides are 500 nm wide and

300nm thick, we assume that the active section is also 500nm wide. And the

intrinsic region of the active section is 250nm thick. The total device footprint is

only 5 μm2. We can estimate the intrinsic capacitance of the active section using a

simple parallel plate model, as shown in Equation (5.3). Note that the relative

permittivity of Si0.1Ge0.9 is used in the calculation.

(5.3)

Furthermore, in Ref [7], the total thickness of the intrinsic region is 476 nm, almost

twice as thick as our proposed structure. So a 0.5 V swing in the proposed device

generates an equivalent electrical field change as a 1 V swing in Ref [7]. With this

0.5 V swing, the energy consumption can be calculated using Equation (5.4).

79

(5.4)

And finally, if the device contacts are terminated with a 50 Ω resistance, the RC

limited bandwidth can be deduced as

(5.5)

To summarize, with Ge/SiGe quantum wells, at least in this simple idealized device,

we can easily achieve a 3 dB contrast ratio with only 4.58 μm long device with an

insertion loss penalty of 2.27 dB. With a 10 μm long device, the intrinsic capacitance

can be as small as 3.2 fF, and the energy consumption is only 0.8 fJ/bit. To put things

into perspective, these figures of merits are at least an order of magnitude better than

the counterparts in the existing on-chip electrical interconnect system. Moreover, this

device also satisfies the most stringent requirements for on-chip optical interconnect

systems [8].

Of course, the above calculations are undoubtedly idealized. For example, in the

capacitance calculation, a simple parallel plate capacitance model is used. For devices

with such a small dimension, fringing fields cannot be neglected. And more

importantly, the parasitic capacitances from the doped layers, contacts etc. also

contribute to the total device capacitance. Nevertheless, the above analysis does show

the great performance potential of such a QCSE based Ge/SiGe quantum well

waveguide modulator. Because of the very small device footprint, low capacitance,

sub-femto joule per bit energy consumption, and high-speed operation can be

achieved, all without having to include resonators. This serves as our main motivation

to realize this device.

5.2.2 Actual Device Design

80

As a proof-of-principle demonstration, our actual device has some modifications from

the idealized device. In this section, we want to discuss some practical aspects of

device design and tradeoffs in our actual fabricated device.

Instead of wire waveguides, we use a single mode small cross section SOI rib

waveguide, which is developed by our collaborators at KOTURA [9]. As discussed in

Chapter 2, this type of waveguide has lower propagation loss than the commonly used

single mode SOI wire waveguide. The top Si layer and the BOX cladding of the

waveguide are 310 nm and 1 μm thick, respectively. Different from Ref [9], we

choose the rib width to be 800 nm. The waveguides are tapered up at the input/output

ports to improve the coupling efficiency with the optical fiber. Adiabatic tapers are

also implemented in the waveguide to accommodate different active section widths.

1.5 μm SiO2 is deposited using plasma enhanced chemical vapor deposition (PECVD)

as the top cladding. The waveguide only supports the fundamental quasi-TE mode, the

propagation loss of which is around 0.9 dB/cm in the entire C-band.

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Figure 5.3 (a) Epitaxy design for waveguide modulator to match the SOI

waveguide. (b). Schematic of the SOI waveguide and the active section after the

CMP.

For direct butt coupling, it is important to design the epitaxy such that the Ge/SiGe

quantum wells in the active section are placed to have good overlap with the mode of

the passive SOI waveguide. This ensures that the optical field passes through the

quantum wells and gets modulated. The major component of the electric field is

polarized parallel to the quantum well since only the fundamental quasi-TE mode is

supported by the SOI waveguide. The epitaxial design is shown in Figure 5.3(a). The

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top As doped Si0.1Ge0.9 is purposefully grown much thicker such the faceting region is

pushed out from the propagation region. After the selective epitaxy, a chemical

mechanical polishing (CMP) step can be carried out to planarize the entire wafer. The

1.5 μm thick oxide cladding on top of the SOI waveguide is designed with this

polishing step in mind. The SOI section and the quantum well sections after the CMP

are illustrated in Figure 5.3(b).

We should note that the growth windows are much wider than the actual designed

width of the active section. After the selective growth, a subsequent lithography/etch

step defines the waveguides in the active section and stops within the bottom B doped

Si0.1Ge0.9 layer. Hence only the two facets along the waveguide propagation direction

are present in the final device. The final device schematic is illustrated in Figure 5.4.

Figure 5.4 Final device schematic

5.2.3 Vertical Mode Mismatch

As illustrated in Figure 5.3, we choose to fill most of the BOX region inside the

growth window with relaxed Si0.1Ge0.9. Under the effective medium approximation,

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the entire epitaxial structure is grown above the handle substrate and has the same

refractive index. The only index contrast in the vertical direction in the active section

is that between the Si handle substrate and the growth epitaxy. In other words, the

optical mode in the active section is not matched to that in the SOI waveguide, in the

vertical direction. This is definitely undesirable from the device performance point of

view. We decided to use this approach for two considerations. First of all, we have

not, in our group, developed an optimized process for the selective epitaxial growth of

Si in holes. If selective Si were grown first to fill the majority of the BOX, better mode

matching would be achieved. However this layer of selectively grown Si has to be

very smooth, planar, and of high crystalline quality, since it would serve as the growth

template for later quantum well growth. On the other hand, selective epitaxial growth

of Si has been widely investigated for a very long time [10, 11]. There is not much

scientific novelty in extensively optimizing the selective epitaxial growth of Si on Si

substrates. Secondly, as discussed earlier, a CMP step is needed to planarize the

surface. Ideally, we want the CMP step to get rid of all the oxide and overgrown

Si0.1Ge0.9 and stop right above the top surface of the Si. However, our CMP capability

is limited and careful calibration is almost impossible given the fact that each selective

epitaxy takes a very long time. If the CMP stops 500 nm above the Si layer, then the

active section will not be able to match the SOI waveguide mode anyway.

Again, the above two constraints - the local unavailability of a process for selective

growing planar smooth high quality Si and our limited CMP capability, are

undesirable and degrade the device performance. However, we believe that both of

these are well within the capability of advanced semiconductor processing technology,

and hence can be solved technically. As our first proof-of-principle device, we choose

to live with these limitations for the moment.

To understand the impact of this mode mismatch, we have carried out 3D FDTD

numerical simulations. In the simulation, the active section is assumed to be 5 μm long

Si0.1Ge0.9 with a refractive index of 4.27. As a worst case scenario, we assume that the

CMP step only removes 500 nm of the oxide. So, the top surface of the active section

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is 1 μm higher than that of the SOI waveguide. The simulation result is shown in

Figure 5.5, where the electrical field component in the cross section along the central

plane of the SOI waveguide is plotted.

Figure 5.5 3D FDTD simulation: electrical field component at the central plane

of the SOI waveguide

From Figure 5.5, we can see that the incident waveguide mode from the input SOI rib

waveguide starts to diverge upon entering the active section. When the diverged beam

hits the exit boundary, only a fraction of the optical power gets coupled into the output

SOI rib waveguide; the rest is transmitted into the cladding or reflected back into the

active section. The field pattern inside the active section is very complicated. A weak

resonator cavity is formed inside the active section. From the simulation, we can

deduce the insertion loss of this section numerically. At 1.55 μm, the additional

insertion loss is around 12 dB.

5.3 Device Fabrication

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In this section, we discuss the fabrication process of this quantum well waveguide

modulator. The entire fabrication process consists of five layers of lithography, one

selective epitaxial growth step, five dry etching steps, and one CMP step. Our

collaborators at KOTURA fabricate the SOI waveguides. The rest of the fabrication is

carried out in the Stanford Nanofabrication Facility.

First, we start with a 6 inch SOITEC SOI substrate with 1 μm thick BOX and 310nm

thick top Si, as shown in Figure 5.6. The first layer lithography defines the SOI

waveguide. Si dry etching is used to partially remove the top Si to define the rib,

leaving a smooth sidewall to reduce the waveguide propagation loss due to surface

scattering. The ASML alignment marks are also printed and etched in each individual

die during this step.

Figure 5.6 Starting SOI substrate: 1 μm thick BOX and 310nm thick top Si. (a).

Isometric view; (b). Cross section view

Figure 5.7 Define SOI shallow ridge waveguide: (a). Isometric view; (b). Cross

section view along the dashed cut plane

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Figure 5.8 Deposit 1.5 μm thick PECVD SiO2 on the surface : (a). Isometric

view; (b). Cross section view along the dashed cut plane

The 1.5 μm thick PECVD SiO2 is deposited on top of the Si surface, as shown in

Figure. 5.8. This PECVD oxide serves four purposes: waveguide cladding, surface

protection/passivation, epitaxial growth mask, and CMP polishing buffer. After this

step, the 6 inch wafer is converted into a 4 inch wafer using laser cutting. Before the

laser cutting, a 3 μm photoresist is coated on the wafer to protect the surface.

After the wafer size reduction, the second lithography step is carried out, using ASML

PAS 5500 I-line stepper, to define the growth windows. The stepper can print features

as small as 400 nm with alignment accuracy better than 50nm, which is good enough

for the fabrication requirements of our device. The width of the growth window is

fixed to be 10 μm wide. Its length along the waveguide direction varies from 5 μm to

400 μm. Then the top cladding oxide, top Si layer, and BOX inside the growth

window are removed by three dry etching steps and one wet etching steps. Following

this, the spacer fabrication process, which was outlined in Chapter 4 and Appendix I,

is carried out to deposit a 20 nm SiO2 layer at the sidewall of the growth window.

These steps are illustrated in Figure 5.9-5.14.

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Figure 5.9 2nd

lithography to define the growth window and etch down to

handle substrate: (a). Isometric view; (b). Cross section view along the dashed

cut plane

Figure 5.10: 20nm LPCVD SiO2 deposition: (a). Isometric view; (b). Cross

section view along the dashed cut plane

Figure 5.11: 50nm LPCVD Si3N4 deposition: (a). Isometric view; (b). Cross

section view along the dashed cut plane

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Figure 5.12: Highly anisotropic Si3N4 dry etching: (a). Isometric view; (b).

Cross section view along the dashed cut plane

Figure 5.13: HF wet etching: (a). Isometric view; (b). Cross section view along

the dashed cut plane

Figure 5.14: Selective Si3N4 wet etching: (a). Isometric view; (b). Cross section

view along the dashed cut plane

With the dielectric thin spacer on the sidewall of the growth window, we selectively

grow Ge/SiGe quantum wells inside the growth window. The growth conditions have

been outlined in Chapter 3. Facets occur at the boundaries of the growth window, as

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indicated in Figure 5.15. Following the selective epitaxy, the 4 inch wafer is diced up

into dies. We decided to carry out the all the subsequent processing in pieces due to

the relatively low yield of our CMP process. Individual die is polished to remove the

overgrown Si0.1Ge0.9. Part of the cladding SiO2 is also removed during this CMP step.

Since we are not able to accurately stop the polishing process right above Si surface,

under-polishing with some cladding SiO2 remaining is preferred over over-polishing.

Too much polishing would damage the Si layer of the SOI waveguide, which would

be much more detrimental to the device performance. After the polishing, the sample

surface is smooth and flat without any facets, as shown in Figure 5.16.

Figure 5.15: Selective epitaxial growth of the Ge/SiGe quantum wells: (a).

Isometric view; (b). Cross section view along the dashed cut plane

Figure 5.16: Planarizing CMP step: (a). Isometric view; (b). Cross section view

along the dashed cut plane

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Figure 5.17: Deep ridge etching to define waveguide in active section: (a).

Isometric view; (b). Cross section view along the dashed cut plane

The third layer of lithography defines the waveguide modulator in the active section.

The width of the waveguide modulator varies from 800 nm to 5 μm. For active

sections wider than 800 nm, linear adiabatic tapers were implemented in the SOI

waveguide section during the first lithography to adiabatically increase the SOI

waveguide width from the original 800 nm to that of the active section. This step and

all the following lithography steps are done piece by piece, using the same ASML

stepper. During the piece exposure, the die to be processed is fixed to a carrier wafer

that has preprinted registration grids. Alignment marks inside each individual die are

used to carry out the overlay alignment. Fabrication results show that our piece

lithography process can deliver similar resolution and overlay accuracy as the wafer-

size lithography [12]. A dry etching step then etches the SiGe section, and stops within

the bottom B doped SiGe contact layer. During this etching step, the tilted quantum

well sections at the faceting boundary perpendicular to the waveguide propagation

direction are also removed, as show schematically in Figure 5.17.

Then a 50 nm thick low temperature SiO2 (LTO) is deposited at 400oC over the entire

surface of the sample (shown in Figure 5.18) to provide sidewall passivation of the

etched SiGe and electrical isolation between the subsequent metal pad and the

semiconductor. The fourth lithography step, together with a subsequent HF wet etch

step, defines and opens up the contact vias to the top and bottom doped Si0.1Ge0.9

layers. The smallest contact vias are 500 nm by 500 nm, the smallest feature size in

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the entire process. The fifth lithography step defines the contact metal pads. Ground-

signal-ground (GSG) probe pads with 100 μm finger spacing are printed. Finally, 10

nm Ti and 200 nm Al are deposited as the contact metal using e-beam evaporation and

lift-off. Figure 5.19 shows the schematic of the final device. After the fabrications, the

facets of the chip are polished to a mirror finish to increase the coupling efficiency.

Figure 5.18: 50 nm LTO deposition: (a). Isometric view; (b). Cross section view

along the dashed cut plane

Figure 5.19: Final device: (a). Isometric view; (b). Cross section view along the

dashed cut plane

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Figure 5.20 Cross section SEM of the finished device at the boundary between

the SOI waveguide and the Ge/SiGe waveguide modulator

Figure 5.21 Optical microscope image of a finished device with a 5 μm long, 3

μm wide active section.

Figure 5.20 is a cross section SEM image of the finished device at the boundary

between the SOI waveguide and the Ge/SiGe quantum well waveguide modulator.

Planar quantum wells can be easily identified on the right hand side, at the same

vertical level as the core of the SOI waveguide. Figure 5.21 shows the optical

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microscope image of a finished device with a 5 μm long, 3 μm wide active section.

The linear tapers in the SOI waveguide section can also be identified.

5.4 Experimental Results

In this section, we discuss our experimental results of this integrated device. First, the

surface normal modulator that is fabricated together with the waveguide modulator on

the same chip will be discussed. Then the high-speed modulation results for the

waveguide modulator integrated with SOI waveguides will be presented.

5.4.1. Surface Normal Modulator

On the same SOI chip with the integrated waveguide modulators, surface normal

modulators are also fabricated. These surface normal structures are large square mesa

structures typically several hundred microns by several hundred microns wide, and

used primarily as testing devices to understand the quality of the material and the

wavelength of operation of the waveguide modulator. The photocurrent spectra of the

grown epitaxy are much easier to collect with the surface normal structures since no

waveguide alignment is required. Furthermore, in the waveguide based modulator,

multiple Fabry-Perot resonances occur, making photocurrent spectra difficult to

interpret.

Figure 5.22 is the current-voltage characteristic under dark conditions for a 150 μm

by 150 μm square mesa diode fabricated from a 200 μm by 200 μm square growth

window. Compared to diodes fabricated from bulk epitaxy, the diodes constructed

from selective epitaxy show lower reverse leakage current density (2.2 mA/cm2

at -1

V) and higher breakdown voltage (up to 8 V). This suggests that the selective epitaxy

has a lower threading dislocation density, and hence is of better quality [13].

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Figure 5.22 Dark current-voltage characteristic for a 150 μm by 150 μm square

mesa diode fabricated from a 200 μm by 200 μm growth window opening.

Figure 5.23 shows the photocurrent spectra of the diode under different bias voltages.

Large changes in the photocurrent spectrum are observed, corresponding to the well-

known QCSE induced change in optical absorption. Very sharp exciton peaks can be

identified in the spectra, indicating minimal inhomogeneous broadening caused by

nonuniformities of the grown quantum well thicknesses. This is yet further evidence of

the uniformity and quality of the selective epitaxy. In the photocurrent spectroscopy

measurement, the magnitude of reverse leakage current and the breakdown voltage

imposes some practical limits on how high an electric field can be applied to the

quantum wells. Large reverse leakage current also directly translates to high static

power consumption. Because we are able to apply to up to 8 V DC bias

(corresponding to approximately 20 V/μm), the absorption edge is shifted into the

telecommunication C-band (1530 nm-1565 nm) without heating above room

temperature for the first time in the Ge quantum well material system.

Figure 5.24 shows the photocurrent ratio for a 1 V signal swing at different bias

voltages, which is deduced from Figure 5.23. The largest photocurrent ratio is 2.84,

occuring right at 1500 nm for a voltage swing between 6.5 V and 5.5 V. With a 7.5 V

DC bias and 1 V swing, the photocurrent ratio is larger than 2 from 1526 nm to 1548

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nm, corresponding to a 3dB optical bandwidth of 2.8 THz, covering more than half of

the telecommunication C-band (1530 nm~1565 nm).

Figure 5.23 Photocurrent spectra of the same diode under different bias

voltages.

Figure 5.24 Photocurrent ratio of the same diode under different bias voltages.

The green box indicates the telecommunication C-band (1530 nm~1565 nm).

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5.4.2. Waveguide Modulator

The waveguide testing setup is shown in Figure 5.25. The coupling to and from the

waveguide chip is realized through tapered fiber, which gives a spot diameter of 2±0.5

μm with a working distance of 12±2 μm [14]. Both input and output tapered fibers sit

on 3-axis stages with piezoactuators. The sample under test sits on a 4 axis manual

stage with micromanipulators. The polarization of the input optical beam is set by a

polarization controller. An ACP probe with a GSG configuration and a 3 dB electrical

bandwidth of 40 GHz is used to making electrical contacts to the optical modulator.

Figure 5.26(a) is zoomed-in picture of the actual setup. What are not shown in Figure

5.25 are the top view and side view cameras for waveguide alignment. Figure 5.26(b)

is the image taken from the top view camera during device testing, showing the SOI

waveguide, active Ge quantum well modulator section, and the high speed probe.

Figure 5.25 Schematics of waveguide measurement setup for high speed testing.

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Figure 5.26 Waveguide measurement setup. (a). Zoomed-in image of the

experimental setup. (b). Image from top-view camera during testing.

In the high-speed measurement, the electrical signal with a 3.5 GHz modulation

frequency from a HP 8133A pulse generator is combined with a DC voltage bias using

a bias-T, and applied to the waveguide modulator through RF cable. The transmission

through the entire waveguide chip is collected by the output tapered fiber and

measured by an Agilent 86100A Infiniium digital communication analyzer. Figure

5.27 shows the measured optical output of a Ge quantum well waveguide modulator

with an 800 nm wide and 10 μm long active section. The device is DC-biased at 4V,

while a 1V voltage swing is applied to the device. The CW output of the tunable laser

is fixed at 1460nm. From the zoomed-in plot of Figure 5.27 (b), we can see that more

than 3 dB extinction ratio has been achieved.

Finally, we should note that due to the compromises in the device design, the

waveguide links with modulator active sections measure ~15 dB additional insertion

loss. With an output power of several mW, only a few μW optical power gets

transmitted. This makes the eye-diagram difficult to obtain. However, from Figure

5.27, we can deduce the rise and fall time, both of which are around 40 ps. Hence this

device should be able to operate up to ~ 8 GHz, or equivalently 16 Gbps.

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Figure 5.27 High speed oscilloscope trace showing the transmission of the

waveguide modulator under high speed electrical signal. (a). Original

oscilloscope trace; (b). Zoomed-in replot of the same data.

5.5 Ge/SiGe Quantum Wells on the 3 μm SOI

Waveguide Platform

In the previous section, we demonstrated a proof of principle waveguide modulator

device with only 8 μm2 footprint. It can deliver a 3 dB contrast ratio with only 1 V

voltage swing at 16 Gbps speed. However, the insertion loss is too high for any

practical optical interconnect applications, especially long-distance optical

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interconnects. In Section 5.2, we outlined some possible improvement approaches,

including selective Si growth to fill the BOX and more accurate CMP polishing. In

this section, we focus on another approach to reduce this insertion loss. In particular,

we will look into the 3 μm large cross section SOI rib waveguide platform, and

analyze how the Ge/SiGe quantum well waveguide modulator can be integrated into

this platform and bring improvements for off-chip optical interconnect applications.

Figure 5.28 3 μm wide large cross section rib waveguide (taken from ref [15]).

The waveguide geometry that we will focus on is shown in Figure 5.28 [15], which

has been developed into a mature platform. In this platform, it is easy to couple

from/to optical fiber, and the guides have very low propagation loss, hence giving an

ideal platform for off-chip interconnect applications. This waveguide is single-moded,

and only supports the fundamental quasi-TE mode. Based on the geometries in Ref

[15], we calculated the mode profile of this waveguide, which is shown in Figure

5.29. We can see that most of the optical power resides inside Si and has little overlap

with the rib sidewall. This is the main reason why the propagation loss in this type of

waveguide can be extremely low. In Figure 5.30, we plot the major component of the

electric field for the fundamental mode in the central plane along the y-direction. As

we can see, little electric field penetrates into the underlying BOX. So only a very thin

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BOX layer is needed for the optical confinement. Typical BOX thickness for this large

cross section rib waveguide is ~300 nm.

Figure 5.29 Fundamental mode profile of the 3 μm rib waveguide. Color plot

shows the power flow in the propagation direction; contour plot shows the

electric field in the x-direction.

Figure 5.30 Electric field component in the x-direction along the central cut line

(the white dashed line in Figure 5.29).

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The two approaches to integrate the Ge/SiGe quantum wells with 3 μm large cross

section rib waveguides are shown in Figure 5.31 and Figure 5.32. With a BOX of

only 300 nm, the mode in the modulator active section is much better matched to the

SOI waveguide section than the small cross rib waveguide if the selective epitaxy

starts from the handle Si substrate. Furthermore, the 3 μm thick top Si layer makes it

possible to grow the quantum well epitaxy from an etched Si recess without even

removing the BOX. In both cases, we expect a low insertion loss since the mode

mismatch problem that exists in our proof-of-principle device is essentially eliminated.

Figure 5.31 Integration of Ge QW through growth from handle substrate

Figure 5.32 Integration of Ge QW through Si recess

One further advantage for the 3 μm SOI waveguide platform is that the free carrier

absorption in the active section from the doped region is reduced. In Figure 5.33, we

divide the 3 μm waveguide into four sections, and the optical power of the

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fundamental mode within in each section is calculated. Keeping in mind that in the Ge

quantum well active section, the top 200nm and bottom 200nm are doped to make

electrical contacts, the overlap between the optical mode and the doped regions is less

than 1%. So the free carrier absorption can be drastically reduced.

Figure 5.33 Optical distribution of the fundamental mode within the waveguide

From the modulator insertion loss point of view, the 3 μm large cross section rib

waveguide platform might be preferred. However, this type of waveguide is large in

footprint and requires relatively large bending radius (~mm) to realize low loss

bending. The quantum well waveguide modulators integrated on this waveguide

platform are large in size and need more pairs of quantum wells to match the mode

profile. This can increase the device capacitance, driving voltage swing, and power

consumption, all of which are undesirable for on-chip optical interconnect systems.

For longer distance optical interconnects such as telecommunication systems, on the

other hand, our proposed quantum well modulator is very attractive. By using

monolithic integration and CMOS-compatible technology, the cost can be drastically

reduced compared to the current III-V based modulator components. This is a good

example in which our efforts towards solving on-chip optical interconnect problems

can bring substantial improvements and benefits to optical interconnect systems of

longer distances.

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5.6 Conclusions

In this chapter, we discussed our efforts towards realizing a Ge/SiGe quantum well

waveguide modulator integrated with SOI waveguides through direct-butt coupling.

This type of device can be very compact in size, operate under low voltage swing, and

have low device capacitance of and sub-femto joule energy consumption.

We designed and fabricated Ge/SiGe quantum well modulators integrated with SOI

waveguides using selective epitaxial growth. The fabricated diodes show very low

reverse leakage current and high breakdown voltage, suggesting very high epitaxial

materials quality. With an applied 8 V bias (approximately 20 V/μm, the largest

electrical field ever successfully applied to this quantum well system), efficient

modulation occurs for wavelengths above 1.5 μm. A waveguide modulator with a

footprint of only 8 μm2 is measured, showing direct electrical-to-optical modulation of

more than 3 dB with only 1 V drive voltage swing operating at 1460 nm wavelength.

We also proposed and analyzed the integration of this Ge/SiGe quantum well

waveguide modulator to the 3 μm large cross section SOI waveguide platform for

optical interconnect systems of longer distances.

Our analysis and experimental demonstrations show the great potential of waveguide-

based Ge/SiGe quantum well modulators for on-chip and off-chip optical interconnect

applications.

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Chapter 6

Summary and Future Work

6.1 Summary

In this dissertation, we studied the growth and integration of QCSE-based Ge/SiGe

quantum well waveguide modulators with SOI waveguides for on-chip and off-chip

optical interconnect applications.

Thanks to the development of silicon VLSI technology over the past several decades,

we can now integrate far more transistors onto a single chip than ever before.

However, this also imposes more stringent requirements, in terms of bandwidth,

density, and power consumption, on the interconnect systems that link transistors. The

interconnect system is currently one of the major hurdles for the further advancement

of the electronics technology. Optical interconnect is considered a promising solution

to overcome the interconnect bottleneck. Chapter 1 overviewed the major motivations

for bringing optics to and on Si chips and outlined the requirements for the

components in such optical interconnect systems.

Chapter 2 reviewed the basic physical properties of the Ge/SiGe quantum wells and

the quantum-confined Stark effect in this material system. Two optical modulator

configurations, surface normal based and waveguide based, were addressed and

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compared. This chapter also discussed different types of SOI waveguides and their

properties, including propagation loss and low loss bending.

In Chapter 3, the growth of Ge/SiGe quantum wells was discussed with a focus on two

special growth aspects: the thin buffer growth and selective epitaxial growth. We

demonstrated that material quality degrades when the buffer thickness is reduced.

With a 150 nm thin relaxed buffer, clear QCSE was observed, though the excitonic

features are somewhat smeared out. The selective epitaxial growth of Ge/SiGe

quantum wells on pre-patterned Si substrates with masking SiO2 was investigated. We

demonstrated perfect selectivity between the mask and the growth window. The grown

epitaxy showed no dependence on the pattern size and oxide coverage. The faceting

behavior at different temperatures was also explored.

A dielectric thin spacer was proposed in Chapter 4 for the integration of Ge/SiGe

quantum wells to the SOI waveguides. Through numerical simulations, we showed

that the insertion loss penalty of a SiO2 spacer decreases with reducd spacer thickness.

For a spacer of 20 nm, the insertion loss penalty is only 0.13 dB. We also proposed

and demonstrated a robust fabrication to realize this thin spacer with excellent wafer-

scale uniformity and batch reproducibility.

In Chapter 5, we investigated the integration of the QCSE Ge/SiGe quantum well

modulators with the SOI waveguides. The performance metrics of idealized devices in

this category were first estimated, serving as the motivation. Then the device designs

and the practical compromises of our device were addressed. Experimentally, we

demonstrated a QCSE Ge/SiGe quantum well waveguide modulator integrated with

SOI waveguides with a footprint of only 8 μm2. The device can deliver more than 3

dB modulation with merely 1 V voltage swing at a speed of 16 Gbps. Also, for the

first time, we demonstrated efficient QCSE modulation with this quantum well system

for wavelengths above 1.5 μm at room temperature. A 3 dB optical modulation

bandwidth of 2.8 THz, covering more than half of the telecommunication C-band is

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measured from a surface normal modulator fabricated together on the same chip with

the waveguide modulators.

6.2 Possible Future Work

The Ge/SiGe quantum well system is a very new and exciting material platform with

many great science and engineering opportunities. Since our first demonstration of the

QCSE in such system in 2005, there have been several groups working actively on this

topic. In this section, I will confine myself to the future work that is related to work in

this dissertation only.

6.2.1 Material Aspects

In our thin buffer growth study, we only investigated the effect of the thin buffer on

bulk epitaxy. It is well known that selective growth can help reduce the threading

dislocation density and partially relax built-in stress in the grown epitaxy. It will be

very interesting if we can explore the possibility of further reducing the buffer

thickness using selective heteroepitaxial and superlattice growths. Thinner buffers will

lead to further flexibility to integrate this material system with other optoelectronic

and electronic devices.

The faceting at the growth window boundary of the selective growth, though not a

major problem for the modulators, is undesirable. Avoiding the faceting can further

improve the performance of the waveguide-based modulators. In Chapter 2, we have

already mentioned the IMEC work of facet-less selective Ge growth by growing at a

lower temperature. This is definitely an interesting direction to explore. Another

possible approach is to add HCl during the selective epitaxy. In the literature, people

have shown that the addition HCl can change the growth rates for different

crystallographic planes, and hence modify the faceting behavior of the selectively

grown epitaxy. Applying this technical trick to Ge/SiGe quantum well system may

bring better faceting control for the selective epitaxy.

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6.2.2 Device Integration Aspects

From the device design/integration perspective, better mode matching of the quantum

well waveguide active section to the SOI waveguide has potential to greatly improve

the device performance, especially the insertion loss. I already outlined some possible

improvements in Chapter 5, including selective Si growth and precise CMP control.

We also proposed a similar device on the large cross section SOI rib waveguide

platform.

In addition to the above improvements, building a resonator cavity based waveguide

modulator is another interesting possible research direction. Figure 6.1 illustrates two

such examples, one based on linear gratings, and one based on a 1-D photonic crystal.

With a quality factor of several hundred, resonator based waveguide modulators could

further reduce the device footprint, drive voltage, and power consumption, and

increase modulation extinction ratio.

Figure 6.1 Resonator based Ge/SiGe quantum well waveguide modulator: (a).

grating based; (b). 1-D photonic crystal based.

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Appendix I

Thin Spacer Fabrication

Process

This appendix describes the thin spacer fabrication process in full detail. This

fabrication process is designed to have several self-limiting etching steps, and is robust

to fabrication variations [1, 2]. Excellent uniformity can be achieved across the entire

wafer. The fabrication process is done using tools at the Stanford Fabrication Facility.

The specific machine names and processing recipes are in italics.

1 Oxidation

In this step, thermal oxidation is carried out to thin down the top Si layer of the SOI

substrate. This oxide will also act as the dielectric mask for later selective growth.

Deposited LPCVD SiO2 can also be used, but densification is required to improve

selectivity during the selective epitaxy step.

Tool: Tylan; Recipe: Dry1100

2 Lithography: Define Growth Window

In this step, the growth window is defined using ASML I-line stepper.

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Wafer prime in YES oven

0.7 μm SPR 995CM: 3.5 krpm for 30sec at SVGCOAT

Pre-exposure bake: 90oC for 120sec at SVGCOAT

The post-exposure bake: 120oC for 90sec at SVGDEV

Develop: MF-26A at SVGDEV

Post-develop bake: 120oC for 60sec at SVGDEV

3 SiO2 Dry Etch

This step is to remove the oxide cladding above the growth window.

Plasma chemistry: O2 and CHF3; Pressure: 40mT.

Tool: AMT Etcher; Recipe: Std Oxide

4 Si Dry Etch

This step etches the top silicon of the SOI substrate.

Plasma chemistry: Cl2, CF4, and HBr; Pressure: 100 mT; RF power: 200W; Magnetic

field: 40 Gauss.

Tool: Applied Material P5000, Recipe: ChC.POLY.ETCH

5 SiO2 Dry Etch

This step is to remove the majority of the BOX.

Plasma chemistry: O2 and CHF3; Pressure: 40mT.

Tool: AMT Etcher; Recipe: Std Oxide

6 HF Wet Etch

This step is to remove the remaining SiO2 right above the handle substrate of the SOI

substrate. HF at room temperature is used. Spectroscopic ellipsometry measurement

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(Wollam) is needed to make sure that the oxide inside the growth window is removed

completely.

7 Resist Stripping and Wafer Cleaning

9:1 H2SO4:H2O2 at 120oC for 20 min

8 Conformal LTO SiO2 Deposition

Low temperature oxide is deposited at 400oC, 350 mTorr. A calibration deposition is

needed to measure the deposition rate of the process. Then the deposition time of the

actual spacer can be calculated.

Tool: TylanBPSG; Recipe: LTO400PC

9 LTO Densification

This step is to densify the deposited SiO2 layer. An anneal step at 1000oC for 40 min is

used.

10 Conformal Nitride Deposition

This step deposits the conformal sacrificial Si3N4. A prior calibration step is needed to

deposit the designed thickness.

Tool: TylanNitride; Recipe NEWLSN

11 Anisotropic Nitride Etch

This step etches the Si3N4 completely inside the growth window, leaving with a nitride

spacer on the sidewall. The end point detector can be used to monitor the etching

process so that etching stops after hitting the oxide inside the growth window.

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Plasma chemistry: CHF3, CF4, Ar, and O2; Pressure: 30 mT; Power: 50 W; Magnetic

field: 60 Gauss.

Tool: P5000; Recipe: CHB.NIT-SPACE

12 HF Wet Etch

This step removes deposited oxide on the surface of the growth window. HF at room

temperature is used. Spectroscopic ellipsometry (Wollam) is used to make sure that the

oxide is removed completely.

13 Hot Phosphoric Acid Wet Etch

Hot phosphoric acid at 155oC is used to remove the nitride spacer on the sidewall

facet, followed by water rinse and spin/dry.

Tool: WBNITRIDE

References:

1. S. Ren and D. A. B. Miller, US Provisional Patent, 61/402358

2. S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Dielectric

Spacer for the Integration of Germanium Quantum Wells on SOI Waveguide,”

IEEE Group IV Photonics, Beijing, China, WD5 (2010)