©2004 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev.1.0.1

Features• Optimized for Quasi-Resonant Converter (QRC)• Advanced Burst-Mode operation for under 1 W standby

power consumption• Pulse by Pulse Current Limit (5A)• Over load protection (OLP) - Auto restart• Over voltage protection (OVP) - Auto restart• Abnormal Over Current Protection (AOCP) - Latch• Internal Thermal Shutdown (TSD) - Latch• Under Voltage Lock Out (UVLO) with hysteresis• Low Startup Current (typical : 25uA)• Low Operating Current (typical : 4mA)• Internal High Voltage SenseFET• Built-in Soft Start (20ms)• Extended Quasi-resonant Switching for Wide Load Range

Application• CTV• DVD Receiver • Audio Power Supply

DescriptionIn general, Quasi-Resonant Converter (QRC) shows lowerEMI and higher power conversion efficiency compared to theconventional hard switched converter with a fixed switchingfrequency. Therefore, it is well suited for applications that aresensitive to the noise, such as color TV and audio. TheFSCQ0765RT is an integrated Pulse Width Modulation(PWM) controller and Sense FET specifically designed forQuasi-resonant off-line Switch Mode Power Supplies(SMPS) with minimal external components. The PWMcontroller includes integrated fixed frequency oscillator, undervoltage lockout, leading edge blanking (LEB), optimized gatedriver, internal soft start, temperature compensated precisecurrent sources for a loop compensation and self protectioncircuitry. Compared with discrete MOSFET and PWMcontroller solution, it can reduce total cost, component count,size and weight simultaneously increasing efficiency, produc-tivity, and system reliability. This device is a basic platformwell suited for cost effective designs of Quasi resonantswitching flyback converters.

Table 1. Notes: 1. Maximum practical continuous power in an open frame design at 50°C ambient. 2. 230 VAC or 100/115 VAC with doubler.

Typical Circuit

Figure 1. Typical Flyback Application

OUTPUT POWER TABLE

PRODUCT230VAC ±15%(2) 85-265VACOpen Frame(1) Open Frame(1)

FSCQ0765RT 100 W 85 W

FSCQ1265RT 170 W 140 W

FSCQ1565RT 210 W 170 W

Vcc

GND

Drain

Sync

Vo

PWM

VFB

ACIN

FSCQ0765RT

FSCQ0765RTGreen Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Switching Converter

FSCQ0765RT

2

Internal Block Diagram

Figure 2. Functional Block Diagram of FSCQ0765RT

9V/15V

3 1

2

4

AuxiliaryVref Main bias

S

Q

Q

R

OSC

Vcc

Vref

Idelay

IFB

VSD

TSD

Vovp

Sync

Vocp

S

Q

Q

R

R2.5R

Vcc good

Vcc Drain

FB

GND

AOCP

Gatedriver

Vcc good

LEB600ns

PWM

Soft start

Internalbias

Normaloperation

VBurst

Vref

IB

VrefIBFB

Burst modeController

Normal operation Burst Switching

5Sync

Threshold

Quasi-resonant(QR) switching

controller

+

-

+

-

S

Q

Q

R

Power off Reset

4.6V/2.6V : Normal QR3.0V/1.8V : Extended QR

fs

FSCQ0765RT

3

Pin Definitions

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Number Pin Name Pin Function Description1 Drain High voltage power SenseFET drain connection. 2 GND This pin is the control ground and the SenseFET source.

3 Vcc This pin is the positive supply input. This pin provides internal operatingcurrent for both start-up and steady-state operation.

4 Vfb

This pin is internally connected to the inverting input of the PWM comparator.The collector of an opto-coupler is typically tied to this pin. For stableoperation, a capacitor should be placed between this pin and GND. If thevoltage of this pin reaches 7.5V, the over load protection triggers resulting inshutdown of the FPS.

5 Sync

This pin is internally connected to the sync detect comparator for quasiresonant switching. In normal quasi-resonant operation, the threshold of thesync comparator is 4.6V/2.6V. Meanwhile, the sync threshold is changed to3.0V/1.8V in extended quasi-resonant operation.

5.Sync4.Vfb3.Vcc2.GND1.Drain

TO-220F-5L

FSCQ0765RT

4

Absolute Maximum Ratings(Ta=25°C, unless otherwise specified)

Notes:1. Tj = 25°C to 150°C2. Repetitive rating: Pulse width limited by maximum junction temperature3. L = 21mH, VDD = 50V, RG = 25Ω, starting Tj = 25°C

Parameter Symbol Value UnitDrain-Source (GND) Voltage (1) VDSS 650 VDrain-Gate Voltage (RGS=1MΩ) VDGR 650 VGate-Source (GND) Voltage VGS ±30 VDrain Current Pulsed (2) IDM 15 ADCSingle Pulsed Avalanche Energy (3) EAS 570 mJContinuous Drain Current (Tc = 25°C) ID 3.8 ADC

Continuous Drain Current (TC=100°C) ID 2.4 ADCSupply Voltage VCC 20 V

Analog Input Voltage RangeVsync -0.3 to 13V VVFB -0.3 to VCC V

Total Power Dissipation PD 45 WOperating Junction Temperature TJ +150 °COperating Ambient Temperature TA -25 to +85 °CStorage Temperature Range TSTG -55 to +150 °CThermal Resistance Rthjc 2.6 °C/W

FSCQ0765RT

5

Electrical Characteristics (SenseFET Part)(Ta=25°C unless otherwise specified)

Note:1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2%

Parameter Symbol Condition Min. Typ. Max. UnitDrain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 650 - - V

Zero Gate Voltage Drain Current IDSSVDS = Max, Rating, VGS = 0V - - 200 µAVDS= 0.8*Max., RatingVGS = 0V, TC = 85°C - - 300 µA

Static Drain-source on Resistance (Note) RDS(ON) VGS = 10V, ID = 2.3A - 1.4 1.6 Ω

Input Capacitance CissVGS = 0V, VDS = 25V,f = 1MHz

- 1415 1840pFOutput Capacitance Coss - 100 130

Reverse Transfer Capacitance Crss - 15 20Turn on Delay Time td(on) VDD= 0.5BVDSS, ID= 7.0A

(MOSFET switchingtimes are essentiallyindependent of operating temperature)

- 25 60

nsRise Time tr - 60 130Turn Off Delay Time td (off) - 110 230Fall Time tf - 65 140Total Gate Charge(Gate-Source+Gate-Drain) Qg VGS = 10V, ID = 7.0A,

VDS = 0.5BVDSS (MOSFET Switching times are essentially independent of operating temperature)

- 40 52

nCGate-Source Charge Qgs - 7 9.1Gate-Drain (Miller) Charge Qgd - 12 17

FSCQ0765RT

6

Electrical Characteristics (Continued)

(Ta=25°C unless otherwise specified)

Note:1. These parameters is the current flowing in the Control IC.2. These parameters, although guaranteed, are tested only in EDS (wafer test) process.3. These parameters indicate Inductor Current.4. These parameters, although guaranteed at the design, are not tested in mass production.

Parameter Symbol Condition Min. Typ. Max. UnitUVLO SECTIONVcc Start Threshold Voltage VSTART VFB = GND 14 15 16 VVcc Stop Threshold Voltage VSTOP VFB = GND 8 9 10 VSENSEFET SECTIONDrain To PKG Breakdown Voltage (Note4) BVpkg 60HZ AC, Ta = 25°C 3500 - - VDrain To Source Breakdown Voltage BVdss Ta = 25°C 650 - - VDrain To Source Leakage Current Idss Vdrain = 400V, Ta = 25°C - - 200 uAOSCILLATOR SECTIONInitial Frequency FOSC - 18 20 22 kHzVoltage Stability FSTABLE 12V ≤ Vcc ≤ 23V 0 1 3 %Temperature Stability (Note2) ∆FOSC -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 %Maximum Duty Cycle DMAX - 92 95 98 %Minimum Duty Cycle DMIN - - - 0 %FEEDBACK SECTIONFeedback Source Current IFB VFB = 0.8V 0.5 0.65 0.8 mAShutdown Feedback Voltage VSD Vfb ≥ 6.9V 7.0 7.5 8.0 VShutdown Delay Current IDELAY VFB = 5V 4 5 6 µAPROTECTION SECTIONOver Voltage Protection VOVP Vsync ≥ 11V 11 12 13 VOver Current Latch Voltage (Note2) VOCL - 0.9 1.0 1.1 VThermal Shutdown Temp (Note4) TSD - 140 - °C

FSCQ0765RT

7

Electrical Characteristics (Continued)

(Ta=25°C unless otherwise specified)

Note:1. These parameters is the current flowing in the Control IC.2. These parameters, although guaranteed, are tested only in EDS (wafer test) process.3. These parameters indicate Inductor Current.4. These parameters, although guaranteed at the design, are not tested in mass production.

Parameter Symbol Condition Min. Typ. Max. UnitSync SECTIONSync Threshold in normal QR (H) VSH1 Vcc = 16V, Vfb = 5V 4.2 4.6 5.0 VSync Threshold in normal QR (L) VSL1 Vcc = 16V, Vfb = 5V 2.3 2.6 2.9 VSync Threshold in extended QR (H) VSH2 Vcc = 16V, Vfb = 5V 2.7 3.0 3.3 VSync Threshold in extended QR (L) VSL2 Vcc = 16V, Vfb = 5V 1.6 1.8 2.0 VExtended QR enable frequency FSYH - 90 - kHzExtended QR disable frequency FSYL - 45 - kHzBURST MODE SECTIONBurst Mode Enable Feedback Voltage VBEN 0.25 0.40 0.55 VBurst Mode Feedback Source Current IBFB 60 100 140 uABurst Mode switching Time TBS VFB = 0V 1.2 1.4 1.6 msBurst Mode Hold Time TBH VFB = 0V 1.2 1.4 1.6 msSOFTSTART SECTIONSoft start Time (Note2) TSS 18 20 22 msCURRENT LIMIT(SELF-PROTECTION)SECTIONPeak Current Limit (Note3) ILIM - 4.4 5.0 5.6 ABurst Mode Peak Current Limit (Note4) IBPK - 0.65 0.9 1.15 ATOTAL DEVICE SECTIONStartup Current ISTART VCC = VSTART-0.1V - 25 50 uASustain Latch Current ISL VCC = VSTOP-0.1V - 50 100 uAOperating Supply Current (Note1)- In normal operation- In burst mode (without switching)

IOP Vfb = 2V, VCC = 18V - 4 6 mAIOB Vfb = GND, VCC = 18V - 0.25 0.50 mA

FSCQ0765RT

8

Comparison Between KA5Q0765RT and FSCQ0765RTFunction KA5Q0765RT FSCQ0765RT FSCQ0765RT Advantages

Startup Current Max. 200uA Max. 50uA Lower standby power consumption

Operating supply Current Typ. 10mA Typ. 4mA Operating current is reduced in burst operation to minimize standby power consumption- Normal operation : 4mA - Burst mode with switching : 4mA- Burst mode without switching : 0.25mA

Switching in Burst mode Quasi-resonant switching

Fixed frequency switching (20kHz)

Output regulation in standby mode

Vcc control with hysteresis

Output voltage feedback control

Easy to determine the output voltage in the standby mode

Output Voltage drop in burst mode

about half Any level Lower power consumption in the standby mode through larger output voltage drop

Primary side regulation Available N/A

Soft start N/A Available Internal soft-start (20ms)

Extended Quasi-resonant switching

N/A Available - Guarantees wide load range- Improved efficiency at high line input

FSCQ0765RT

9

Electrical characteristics

-50 0 50 100 1500.8

1.0

1.2

Temp[ ]

Operating Supply Current

Nor

mal

ized

to 2

5

-50 0 50 100 1500.6

0.8

1.0

1.2

1.4

Temp[ ]

Burst-mode Supply Current( Non-Switching)

Nor

mal

ized

to 2

5

-50 0 50 100 1500.6

0.8

1.0

1.2

1.4

Temp[ ]

Start-Up Current

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Start Threshold Voltage

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Stop Threshold Voltage

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Initial Frequency

Nor

mal

ized

to 2

5

Temp[ ]

FSCQ0765RT

10

Electrical characteristics

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Maximum Duty Cycle

Nor

mal

ized

to 2

5

Temp[ ]-50 0 50 100 150

0.90

0.95

1.00

1.05

1.10

Temp[ ]

Over Voltage Protection

Nor

mal

ized

to 2

5

-50 0 50 100 1500.8

0.9

1.0

1.1

1.2

Temp[ ]

Shutdown Delay Current

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Shutdown Feedback Voltage

Nor

mal

ized

to 2

5

-50 0 50 100 1500.8

0.9

1.0

1.1

1.2

Temp[ ]

Feedback Source Current

Nor

mal

ized

to 2

5

-50 0 50 100 1500.8

0.9

1.0

1.1

1.2

Temp[ ]

Burst_mode Feedback Source Current

Nor

mal

ized

to 2

5

FSCQ0765RT

11

Electrical characteristics

-50 0 50 100 1500.6

0.8

1.0

1.2

1.4

Temp[ ]

Burst_Mode Enable Feedback Voltage

Nor

mal

ized

to 2

5

-50 0 50 100 1500.6

0.8

1.0

1.2

1.4

Nor

mal

ized

to 2

5

Temp[ ]

Feedback Offset Voltage

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Sync. Threshold in Normal QR(H)

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Sync. Threshold in Normal QR(L)

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Sync. Threshold in Extended QR(H)

Nor

mal

ized

to 2

5

-50 0 50 100 1500.90

0.95

1.00

1.05

1.10

Temp[ ]

Sync. Threshold in Extended QR(L)

Nor

mal

ized

to 2

5

FSCQ0765RT

12

Functional Description1. 1. 1. 1. Startup : Figure 4 shows the typical startup circuit andtransformer auxiliary winding for FSCQ0765RT application.Before FSCQ0765RT begins switching, FSCQ0765RTconsumes only startup current (typically 25uA) and thecurrent supplied from the AC line charges the externalcapacitor (Ca1) that is connected to the Vcc pin. When Vccreaches start voltage of 15V (VSTART), FSCQ0765RT beginsswitching, and the current consumed by FSCQ0765RTincreases to 4mA. Then, FSCQ0765RT continues its normalswitching operation and the power required for this device issupplied from the transformer auxiliary winding, unless Vccdrops below the stop voltage of 9V (VSTOP). To guarantee thestable operation of the control IC, Vcc has under voltagelockout (UVLO) with 6V hysteresis. Figure 5 shows therelation between the FSCQ0765RT operating supply currentand the supply voltage (Vcc).

Figure 4. Startup circuit

Figure 5. Relation between operating supply current and Vcc voltage

The minimum average of the current supplied from the AC isgiven by

where Vacmin is the minimum input voltage, Vstart is theFSCQ0765RT start voltage (15V) and Rstr is the startupresistor. The startup resistor should be chosen so that Isupavg

is larger than the maximum startup current (50uA).

Once the resistor value is determined, the maximum loss inthe startup resistor is obtained as

where Vacmax is the maximum input voltage. The startupresistor should have proper rated dissipation wattage.

2. Synchronization : FSCQ0765RT employs quasi-resonantswitching technique to minimize the switching noise and loss.In this technique, a capacitor (Cr) is added between theMOSFET drain and source as shown in Figure 6. The basicwaveforms of quasi-resonant converter are shown in Figure7. The external capacitor lowers the rising slop of drainvoltage to reduce the EMI caused when the MOSFET turnsoff. In order to minimize the MOSFET switching loss, theMOSFET should be turned on when the drain voltage reachesits minimum value as shown in Figure 7.

Figure 6. Synchronization circuit

FSCQ0765RT

1N4007

Rstr

Vcc

Ca1

Da

Isup

AC line(Vac

min - Vacmax)

CDC

Ca2

Icc

VccVstop=9V

25uA

4mA

Vstart=15V Vz

Power UpPower Down

Isupavg 2 Vac

min⋅π

------------------------------Vstart

2--------------–

1

Rstr----------⋅=

Loss 1Rstr----------

Vacmax( )

2Vstart

2+2

---------------------------------------------------2 2 Vstart Vac

max⋅ ⋅π

------------------------------------------------------–

⋅=

Vcc

Ca1

Da

CDC

Ca2

GND

Cr

Drain

Ids

Rcc

RSY1

RSY2

Sync

+VDC

-Lm Vo

CSY

+Vds

-

Vco

DSY

Np

Ns

Na

FSCQ0765RT

13

Figure 7. Quasi-resonant operation waveforms

The minimum drain voltage is indirectly detected bymonitoring the Vcc winding voltage as shown in Figure 6and 8. The voltage divider RSY1 and RSY2 should be chosen sothat the peak voltage of sync signal (Vsypk) is lower than theOVP voltage (12V) in order to avoid triggering OVP innormal operation. It is typical to set Vsypk to be lower thanOVP voltage by 3-4 V. In order to detect the optimum time toturn on MOSFET, the sync capacitor (CSY) should bedetermined so that TR is the same with TQ as shown in Figure8. The TR and TQ are given as, respectively

where Lm is the primary side inductance of the transformer,Ns and Na are the number of turns for the output winding andVcc winding, respectively, VFo and VFa are the diodeforward voltage drops of the output winding and Vccwinding, respectively, and Ceo is the sum of the outputcapacitance of MOSFET and external capacitor Cr.

Figure 8. Normal quasi-resonant operation waveforms

Figure 9. Extended quasi-resonant operation

In general, quasi-resonant converter has a limitation in awide load range application, since the switching frequencyincreases as the output load decreases, resulting in a severeswitching loss in the light load condition. In order to get overthis limitation, FSCQ0765RT employs extended quasi-resonant switching operation. Figure 9 shows the modechange between normal quasi-resonant operation andextended quasi-resonant operation. In the normal quasi-resonant operation, the FSCQ0765RT enters into theextended quasi-resonant operation when the switchingfrequency exceeds 90kHz as the load reduces. Then, theMOSFET is turned on, when the drain voltage reaches the

VDC

VRO

VRO

IpkIds

Vds

Vgs

MOSFEToff

MOSFETon

TR RSY2 CSYVco2.6---------

RSY2RSY1 RSY2+-----------------------------------⋅

ln⋅ ⋅=

TQ π Lm Ceo⋅⋅=

VcoNa Vo VFO+( )⋅

Ns----------------------------------------- VFa–=

Vs ync

Vds

MOSFET Gate

2VRO

Vrh (4 .6V)

Vrf (2 .6V)

ON

TQ

TR

ON

Vsypk

Output power

Switchingfrequency

Normal QR operation

Extended QR operation

90kHz

45kHz

FSCQ0765RT

14

second minimum level as shown in Figure 10, which reducesthe switching frequency. Once FSCQ0765RT enters intoextended quasi-resonant operation, the first sync signal isignored. After the first sync signal is applied, the syncthreshold levels are changed from 4.6V and 2.6V to 3V and1.8V, respectively, and the MOSFET turn-on time issynchronized to the second sync signal. The FSCQ0765RTgoes back to its normal quasi-resonant operation when theswitching frequency reaches 45kHz as the load increases.

Figure 10. Extended quasi-resonant operation waveforms

3. Feedback Control : FSCQ0765RT employs current modecontrol, as shown in Figure 11. An opto-coupler (such as theH11A817A) and shunt regulator (such as the KA431) aretypically used to implement the feedback network.Comparing the feedback voltage with the voltage across theRsense resistor plus an offset voltage makes it possible tocontrol the switching duty cycle. When the reference pinvoltage of the KA431 exceeds the internal reference voltageof 2.5V, the H11A817A LED current increases, thus pullingdown the feedback voltage and reducing the duty cycle. Thisevent typically happens when the input voltage is increasedor the output load is decreased.

3.1 Pulse-by-pulse current limit: Because current modecontrol is employed, the peak current through the Sense FETis limited by the inverting input of PWM comparator (Vfb*)as shown in Figure 11. The feedback current (IFB) andinternal resistors are designed so that the maximum cathodevoltage of diode D2 is about 2.8V, which occurs when all IFBflows through the internal resistors. Since D1 is blockedwhen the feedback voltage (Vfb) exceeds 2.8V, themaximum voltage of the cathode of D2 is clamped at thisvoltage, thus clamping Vfb*. Therefore, the peak value ofthe current through the Sense FET is limited.

3.2 Leading edge blanking (LEB) : At the instant theinternal Sense FET is turned on, there usually exists a highcurrent spike through the Sense FET, caused by externalresonant capacitor across the MOSFET and secondary-siderectifier reverse recovery. Excessive voltage across theRsense resistor would lead to incorrect feedback operation inthe current mode PWM control. To counter this effect, theFSCQ0765RT employs a leading edge blanking (LEB)circuit. This circuit inhibits the PWM comparator for a shorttime (TLEB) after the Sense FET is turned on.

Figure 11. Pulse width modulation (PWM) circuit

4. Protection Circuit : The FSCQ0765RT has several selfprotective functions such as over load protection (OLP),abnormal over current protection (AOCP), over voltageprotection (OVP) and thermal shutdown (TSD). OLP andOVP are auto-restart mode protection, while TSD and AOCPare latch mode protection. Because these protection circuitsare fully integrated into the IC without external components,the reliability can be improved without increasing cost.

-Auto-restart mode protection: Once the fault condition isdetected, switching is terminated and the Sense FET remainsoff. This causes Vcc to fall. When Vcc falls down to theunder voltage lockout (UVLO) stop voltage of 9V, theprotection is reset and FSCQ0765RT consumes only startupcurrent (25uA). Then, Vcc capacitor is charged up, since thecurrent supplied through the startup resistor is larger than thecurrent that FPS consumes. When Vcc reaches the startvoltage of 15V, FSCQ0765RT resumes its normal operation.If the fault condition is not removed, the SenseFET remainsoff and Vcc drops to stop voltage again. In this manner, theauto-restart can alternately enable and disable the switchingof the power Sense FET until the fault condition iseliminated (see Figure 12).

-Latch mode protection: Once protection triggers,switching is terminated and the Sense FET remains off untilthe AC power line is un-plugged. Then, Vcc continuescharging and discharging between 9V and 15V. The latch isreset only when Vcc is discharged to 6V by un-plugging theAc power line.

Vsync

Vds

MOSFET Gate

2VRO

4.6V

2.6V3V

1.8V

ONON

4 OSC

Vcc Vref

Idelay IFB

VSD

R

2.5R

Gatedriver

OLP

D1 D2

+Vfb*

-

Vfb

KA431

CB

VoH11A817A

Rsense

SenseFET

FSCQ0765RT

15

Figure 12. Auto restart mode protection

4.1 Over Load Protection (OLP) : Overload is defined asthe load current exceeding its normal level due to anunexpected abnormal event. In this situation, the protectioncircuit should trigger in order to protect the SMPS. However,even when the SMPS is in the normal operation, the overload protection circuit can be triggered during the loadtransition. In order to avoid this undesired operation, theover load protection circuit is designed to trigger after aspecified time to determine whether it is a transient situationor an overload situation. Because of the pulse-by-pulsecurrent limit capability, the maximum peak current throughthe Sense FET is limited, and therefore the maximum inputpower is restricted with a given input voltage. If the outputconsumes more than this maximum power, the outputvoltage (Vo) decreases below the set voltage. This reducesthe current through the opto-coupler LED, which alsoreduces the opto-coupler transistor current, thus increasingthe feedback voltage (Vfb). If Vfb exceeds 2.8V, D1 isblocked and the 5uA current source starts to charge CBslowly up to Vcc. In this condition, Vfb continues increasinguntil it reaches 7.5V, when the switching operation isterminated as shown in Figure 13. The delay time forshutdown is the time required to charge CB from 2.8V to7.5V with 5uA. In general, a 20 ~ 50 ms delay time is typicalfor most applications. This protection is implemented in autorestart mode.

Figure 13. Over load protection

4.2 Abnormal Over Current Protection (AOCP) : Whenthe secondary rectifier diodes or the transformer pins areshorted, a steep current with extremely high di/dt can flowthrough the SenseFET during the LEB time. Even though theFSCQ0765RT has OLP (Over Load Protection), it is notenough to protect the FSCQ0765RT in that abnormal case,since sever current stress will be imposed on the SenseFETuntil OLP triggers. The FSCQ0765RT has an internal AOCP(Abnormal Over Current Protection) circuit as shown inFigure 14. When the gate turn-on signal is applied to thepower Sense FET, the AOCP block is enabled and monitorsthe current through the sensing resistor. The voltage acrossthe resistor is then compared with a preset AOCP level. Ifthe sensing resistor voltage is greater than the AOCP level,the set signal is applied to the latch, resulting in theshutdown of SMPS. This protection is implemented in latchmode.

Figure 14. AOCP block

4.3 Over voltage Protection (OVP) : If the secondary sidefeedback circuit were to malfunction or a solder defectcaused an open in the feedback path, the current through theopto-coupler transistor becomes almost zero. Then, Vfbclimbs up in a similar manner to the over load situation,

Faultsituation

9V

15V

Vcc

Vds

Iop

4mA

25uA

tttt

Faultoccurs Fault

removed

Normaloperation

Normaloperation

Poweron

VFB

t

2.8V

7.5V

Over load protection

T12= CB*(7.5-2.8)/Idelay

T1 T2

2

S

Q

Q

R

OSC

R

2.5R

GND

Gatedriver

LEB

PWM

+

- VaocpAOCP

Rsense

FSCQ0765RT

16

forcing the preset maximum current to be supplied to theSMPS until the over load protection triggers. Because moreenergy than required is provided to the output, the outputvoltage may exceed the rated voltage before the over loadprotection triggers, resulting in the breakdown of the devicesin the secondary side. In order to prevent this situation, anover voltage protection (OVP) circuit is employed. Ingeneral, the peak voltage of the sync signal is proportional tothe output voltage and the FSCQ0765RT uses sync signalinstead of directly monitoring the output voltage. If syncsignal exceeds 12V, an OVP is triggered resulting in ashutdown of SMPS. In order to avoid undesired triggering ofOVP during normal operation, the peak voltage of syncsignal should be designed to be below 12V. This protectionis implemented in auto restart mode.

4.4 Thermal Shutdown (TSD) : The SenseFET and thecontrol IC are built in one package. This makes it easy forthe control IC to detect the abnormal over temperature of theSenseFET. When the temperature exceeds approximately150°C, the thermal shutdown triggers. This protection isimplemented in latch mode.

5. Soft Start : The FSCQ0765RT has an internal soft startcircuit that increases PWM comparator inverting inputvoltage together with the SenseFET current slowly after itstarts up. The typical soft start time is 20msec. The pulsewidth to the power switching device is progressivelyincreased to establish the correct working conditions fortransformers, inductors, and capacitors. It also helps toprevent transformer saturation and reduce the stress on thesecondary diode during startup. For a fast build up of theoutput voltage, an offset is introduced in the soft-startreference current.

6. Burst operation : In order to minimize the powerconsumption in the standby mode, FSCQ0765RT employsburst operation. Once FSCQ0765RT enters into burt mode,FSCQ0765RT allows all output voltages and effectiveswitching frequency to be reduced. Figure 15 shows thetypical feedback circuit for C-TV applications. In normaloperation, the picture on signal is applied and the transistorQ1 is turned on, which de-couples R3, Dz and D1 from thefeedback network. Therefore, only Vo1 is regulated by thefeedback circuit in normal operation and determined by R1and R2 as

In standby mode, the picture on signal is disabled and thetransistor Q1 is turned off, which couples R3, Dz and D1 tothe reference pin of KA431. Then, Vo2 is determined by thezener diode breakdown voltage. Assuming that the forwardvoltage drop of D1 is 0.7V, Vo2 in standby mode is approxi-mately given by

Figure 15. Typical feedback circuit to drop output voltage in standby mode

Figure 16 shows the burst mode operation waveforms. Whenthe picture ON signal is disabled, Q1 is turned off and R3and Dz are connected to the reference pin of KA431 throughD1. Before Vo2 drops to Vo2stby, the voltage on the referencepin of KA431 is higher than 2.5V, which increases thecurrent through the opto LED. This pulls down the feedbackvoltage (VFB) of FSCQ0765RT and forces FSCQ0765RT tostop switching. If the switching is disabled longer than1.4ms, FSCQ0765RT enters into burst operation and theoperating current is reduced from 4mA (IOP) to 0.35mA(IOB). Since there is no switching, Vo2 decrease until itreaches Vo2stby. As Vo2 reaches Vo2stby, the current throughthe opto LED decreases allowing the feedback voltage torise. When the feedback voltage reaches 0.4V, FSCQ0765RTresumes switching with a predetermined peak drain currentof 0.9A. After burst switching for 1.4ms, FSCQ0765RTstops switching and checks the feedback voltage. If thefeedback voltage is below 0.4V, FSCQ0765RT stopsswitching until the feedback voltage increases to 0.4V. If thefeedback voltage is above 0.4V, FSCQ0765RT goes back tothe normal operation.

Vo1norm 2.5

R1 R2+R2

--------------------- ⋅=

Vo2stby VZ 0.7 2.5+ +=

Picture ON

MicomLinearRegulator

VO2

VO1 (B+)

KA431R2

R1R3

Rbias

RD

RFCF D1Q1

A

CR

Dz

FSCQ0765RT

17

Figure 16. Waveforms of burst operation

Vo2norm

VFB

Iop

Vds

0.4V

Vo2stby

IOP (4m A)

Picture On Picture Off

IOB (0.35m A)

Picture On

Burst Mode

(a) (c)(b)

0.4V

0.9A

1.4ms

(b) Burst operation (c) Mode change to Normal operation

VFB

Vds

Ids

0.3V0.4V

1.4ms

(a) Mode change to Burst operation

0.4V

0.9A

1.4ms

FSCQ0765RT

18

Typical application circuit

Features• High efficiency (>80% at 85Vac input)• Wider load range through the extended quasi-resonant operation• Low standby mode power consumption (<1W)• Low component count • Enhanced system reliability through various protection functions • Internal soft-start (20ms)

Key Design Notes• 24V output is designed to drop to around 8V in standby mode

1. Schematic

Application Output power Input voltage Output voltage (Max current)

C-TV 83WUniversal input

(85-265Vac)

12V (1A)

18V (0.5A)

125V (0.4A)

24V (0.5A)

CCCC11110000333311110000uuuuFFFF55550000VVVV

1111

3333

4444

11110000

TTTT1111EEEEEEEERRRR3333555544440000

11112222VVVV,,,, 1111AAAA

CCCC2222000044441111000000000000uuuuFFFF

33335555VVVV

DDDD222200005555EEEEGGGGPPPP22220000DDDD

11111111

LLLLFFFF111100001111

CCCC111100001111333333330000nnnnFFFF

222277775555VVVVAAAACCCC

FFFFUUUUSSSSEEEE222255550000VVVV3333....0000AAAA

CCCC111100002222222222220000uuuuFFFF444400000000VVVV

RRRRTTTT1111000011115555DDDD----9999

BBBBDDDD111100001111

DDDD1111000033331111NNNN4444999933337777

RRRR1111000033335555....1111ΩΩΩΩ

0000....22225555WWWW

6666

7777

RRRR1111000044441111....5555kkkkΩΩΩΩ0000....22225555WWWW2222 4444

5555

1111

3333

GGGGNNNNDDDD

DDDDrrrraaaaiiiinnnnSSSSYYYYNNNNCCCC

FFFFBBBB

VVVVcccccccc

DDDD1111000066661111NNNN4444111144448888

IIIICCCC111100001111FFFFSSSSCCCCQQQQ0000777766665555RRRRTTTT

CCCC11110000666644447777nnnnFFFF55550000VVVV

RRRR111100005555444477770000ΩΩΩΩ0000....22225555WWWW

CCCC1111000055553333....9999nnnnFFFF55550000VVVV

ZZZZDDDD11110000222211118888VVVV1111WWWW

CCCC1111000077771111nnnnFFFF1111kkkkVVVV

BBBBEEEEAAAADDDD111100001111

DDDD1111000055551111NNNN4444999933337777

CCCC222211110000444477770000ppppFFFF1111kkkkVVVV

11118888VVVV,,,, 0000....5555AAAA

DDDD222200004444EEEEGGGGPPPP22220000DDDD

CCCC2222000055551111000000000000uuuuFFFF

33335555VVVV

11113333

CCCC222200009999444477770000ppppFFFF1111kkkkVVVV11112222

111122225555VVVV,,,, 0000....4444AAAA

DDDD222200002222EEEEGGGGPPPP22220000JJJJ

CCCC222200001111111100000000uuuuFFFF111166660000VVVV

11114444

CCCC222200007777444477770000ppppFFFF1111kkkkVVVV

LLLL222200002222BBBBEEEEAAAADDDD

11116666

CCCC22220000222244447777uuuuFFFF111166660000VVVV

22224444VVVV,,,, 0000....5555AAAA

DDDD222200003333EEEEGGGGPPPP22220000DDDD

CCCC2222000033331111000000000000uuuuFFFF

33335555VVVV

11117777

CCCC222200008888444477770000ppppFFFF1111kkkkVVVV11118888

OOOOPPPPTTTTOOOO111100001111888811117777AAAA

RRRR2222000011111111kkkkΩΩΩΩ

0000....22225555WWWW

CCCC222200006666111155550000nnnnFFFF55550000VVVV

CCCC3333000011112222....2222nnnnFFFF QQQQ222200001111

KKKKAAAA444433331111LLLLZZZZ

RRRR22220000333333339999kkkkΩΩΩΩ0000....22225555WWWW

RRRR2222000022221111kkkkΩΩΩΩ

0000....22225555WWWW

RRRR222200005555222222220000kkkkΩΩΩΩ0000....22225555WWWW

RRRR2222000044444444....7777kkkkΩΩΩΩ0000....22225555WWWW

VVVVRRRR22220000111133330000kkkkΩΩΩΩ

DDDD2222000011111111NNNN4444111144448888

QQQQ222200002222KKKKSSSSCCCC999944445555 RRRR222200006666

11110000kkkkΩΩΩΩ0000....22225555WWWW

RRRR2222000077775555....1111kkkkΩΩΩΩ0000....22225555WWWW

SSSSWWWW222200001111

11115555

RRRR111100002222111155550000kkkkΩΩΩΩ0000....22225555WWWWRRRR111100001111

111100000000kkkkΩΩΩΩ0000....22225555WWWW RRRR111100006666

1111kkkkΩΩΩΩ1111WWWW

CCCC11110000444411110000uuuuFFFF55550000VVVV

ZZZZDDDD2222000011115555....1111VVVV0000....5555WWWW

RRRR2222000088881111kkkkΩΩΩΩ

0000....22225555WWWW

FSCQ0765RT

19

2. Transformer Schematic Diagram

3.Winding Specification

4.Electrical Characteristics

5. Core & BobbinCore : EER 3540Bobbin : EER3540Ae : 107 mm2

No Pin (s→f) Wire Turns Winding MethodNp1 1 - 3 0.5φ × 1 32 Center Winding

N125V/2 16 - 15 0.5φ × 1 32 Center WindingN24V 18 - 17 0.4φ × 2 13 Center WindingN12V 12 - 13 0.5φ × 2 7 Center WindingNp2 3 - 4 0.5φ × 1 32 Center Winding

N125V/2 15 - 14 0.5φ × 1 32 Center WindingN18V 11 - 10 0.4φ × 2 10 Center Winding

Na 7 - 6 0.3φ × 1 20 Center Winding

Pin Specification RemarksInductance 1 - 3 515uH ± 5% 1kHz, 1VLeakage Inductance 1 - 3 10uH Max 2nd all short

EER3540

N24V

N a7

13

14

15

16

17

18

N125V/2

N12V

N18V

Np1

Np2

1

2

3

4

5

6

8

9 10

11

12

N125V/2

N125V/2

Np2

N12V

N125V/2

N24V

Np1

N18V

Na

FSCQ0765RT

20

6.Demo Circuit Part List

Part Value Note Part Value NoteFuse C210 470pF / 1kV Ceramic Capacitor

FUSE 250V / 3A C301 3.3nF / 1kV AC Ceramic CapacitorNTC Inductor

RT101 5D-9 BEAD101 BEADResistor BEAD201 5uH 3A

R101 100kΩ 0.25 W DiodeR102 150kΩ 0.25 W D101 1N4937 1A, 600VR103 5.1Ω 0.25 W D102 1N4937 1A, 600VR104 1.5kΩ 0.25 W D103 1N4148 0.15A, 50VR105 470Ω 0.25 W D104 ShortR106 1kΩ 1 W D105 OpenR107 Open ZD101 1N5246 18V, 1WR201 1kΩ 0.25 W ZD102 OpenR202 1kΩ 0.25 W ZD201 1N5231 5.1V, 0.5WR203 39kΩ 0.25 W D201 1N4148 0.15A, 50VR204 4.7kΩ 0.25 W , 1% D202 EGP20J 2A, 600VR205 220kΩ 0.25 W , 1% D203 EGP20D 2A, 200VR206 10kΩ 0.25 W D204 EGP20D 2A, 200VR207 5.1kΩ 0.25 W D205 EGP20D 2A, 200VR208 1kΩ 0.25 W

VR201 30kΩ Bridge DiodeCapacitor BD101 GSIB660 6A, 600V

C101 330n/275VAC Box Capacitor Line FilterC102 220uF / 400V Electrolytic LF101 14mHC103 10uF / 50V Electrolytic TransformerC104 10uF / 50V Electrolytic T101 EER3540C105 3.9nF / 50V Film Capacitor SwitchC106 47nF / 50V Film Capacitor SW201 ON/OFF For MCU SignalC107 1nF / 1kV Film Capacitor ICC108 Open IC101 FSCQ0765RT TO220F-5LC201 100uF / 160V Electrolytic OPT101 817AC202 47uF / 160V Electrolytic Q201 KA431LZ TO-92C203 1000uF / 35V Electrolytic Q202 KSC945C204 1000uF / 35V ElectrolyticC205 1000uF / 35V ElectrolyticC206 150nF / 50V Film CapacitorC207 470pF / 1kV Ceramic CapacitorC208 470pF / 1kV Ceramic CapacitorC209 470pF / 1kV Ceramic Capacitor

FSCQ0765RT

21

7. Layout

Figure 17. Layout Considerations for FSCQ0765RT

Figure 18. Layout Considerations for FSCQ0765RT

FSCQ0765RT

22

Package DimensionsDimensions in Millimeters

TO-220F-5L(Forming)

FSCQ0765RT

23

Ordering Information

YDTU : Forming Type

Product Number Package Marking Code BVdss Rds(ON) Max.FSCQ0765RTYDTU TO-220F-5L(Forming) CQ0765RT 650V 1.6 Ω

FSCQ0765RT

7/7/04 0.0m 001 2004 Fairchild Semiconductor Corporation

LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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