EEE3410 Microcontroller Applications Department of Electrical

1Week 4© Vocational Training Council, Hong Kong.

The 8051 ArchitectureThe 8051 Architecture

EEE3410 Microcontroller ApplicationsDepartment of Electrical Engineering

│ Lecture 4 │


EEE3410 Microcontroller Applications

Overview

General physical & operational features

Block diagram

Pin assignments

Logic symbol

Hardware description

Pin description

Read-modify-write port instructions

In this Lecture In this Lecture …………



Made by Intel in 1981

An 8-bit, single-chip microcontroller optimized for control applications

128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O ports

40 pins in a dual in-line package (DIP) layout

Overview of the 8051Overview of the 8051



4KB ROM

128 bytes internal RAM4 register banks of 8 bytes each (R0-R7)16 bytes of bit-addressable area80 bytes of general purpose memory

Four 8-bit I/O ports (P0-P3)

Two 16-bit timers (Timer0 & Timer1)

One serial receiver-transmitter interface

Five interrupt sources (2 external & 3 internal)

One oscillator (generates clock signal)

General Physical FeaturesGeneral Physical Features



Memory of 8051 can be increased externally:Increase memory space for codes (programs) by 64KIncrease memory space for data by 64K

Boolean instructions work with 1 bit at a time

Assume clock frequency = 12MHz, it takes about 4 µs (i.e. 4 x 10-6s) to carry out a 8-bit multiplication instruction

General Operational FeaturesGeneral Operational Features



The 8051 Block DiagramThe 8051 Block Diagram

Interrupt Control

External Interrupts

CPU

OSC

Timer 1

Timer 0

SerialPort

I/O PortsBus

Control

CounterInputs

P0 P3P1

4K byteROM

128 byteRAM

P2(Address/Data)

TXD RXD



The 8051 Pin AssignmentsThe 8051 Pin Assignments1234567891011121314151617181920

4039383736353433323130292827262524232221

VCC

P0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P2.4 (A12)P2.3 (A11)P2.2 (A10)P2.1 (A9)P2.0 (A8)

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD) P3.0(TXD) P3.1(INT0) P3.2(INT1) P3.3

(T0) P3.4(T1) P3.5

(WR) P3.6(RD) P3.7

XTAL2XTAL1

GND

8051



The 8051 Logic SymbolThe 8051 Logic Symbol

VSS VCC RST

PO RT0

ADDRESS ANDDATA BUS

XTAL1

XTAL2

ALE

EA

PSEN

P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

RxDTxDINT0INT1T0T1WRRD

SECONDARYFUNCTIONS

PORT3

PORT2

ADDRESSBUS

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0

P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0

PORT1



1. Oscillator circuit2. Program counter (PC)3. Data pointer (DPTR)4. Accumulator (“A”) register5. B register6. Flags7. Program status word (PSW)8. Internal memory (ROM, RAM, additional

memory)9. Stack & stack pointer (SP)10. Special function register (SFR)

Hardware DescriptionHardware Description



The heart of the 8051Produces clock pulsesSynchronize all 8051’s internal operations

Oscillator CircuitOscillator Circuit



Machine CycleMachine Cycle

Machine cycle is the basic repetitive process that the CPU performs once it is powered on. A machine cycle consists of a fixed number of clock cycles (pulses). It is different for different kinds of CPU. The 8051 family needs 12 clock cycles for a machine cycle. The CPU takes one or more machine cycles to complete an instruction. More complex instructions require more number of machine cycles to complete the instruction. The number of machine cycles of the 8051 instructions are ranging from 1 to 4.



Example 4Example 4--11Find the elapse time of the machine cycle for:(a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz(c) XTAL = 20 MHz

Solution:(a) 11.0592 MHz / 12 = 921.6 kHz

Machine cycle = 1 / 921.6 kHz = 1.085 µs(b) 16 MHz / 12 = 1.333 MHz

Machine cycle = 1 / 1.333 MHz = 0.75 µs(c) 20 MHz / 12 = 1.667 MHz

Machine cycle = 1 / 1.667 MHz = 0.60 µs



PC is a 16-bit register

PC is the only register that does not have an internal address

Holds the address of the memory location to fetch the program instruction

Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the chip for addresses that exceed 0FFFH

Program ROM may be totally external for all addresses from 0000H to FFFFH

PC is automatically incremented (+1) after every instruction byte is fetched

Program Counter (PC)Program Counter (PC)



DPTR is a 16-bit register

DPTR is made up of two 8-bit registers: DPH and DPL

DPTR holds the memory addresses for internal and external code access and external data access

DPTR is under the control of program instructions and can be specified by its 16-bit name, or by each individual byte name, DPH and DPL

DPTR does not have a single internal address; DPHand DPL are each assigned an address (83H and 82H)

Data Pointer (DPTR)Data Pointer (DPTR)



Accumulator (A Register)Accumulator (A Register)

Most versatile CPU register and is used for many operations, including addition, integer multiplication and division, and Boolean bit manipulations

A register is also used for all data transfer between the 8051 and any external memory



B register is used with the A register for multiplication and division operations

No other special function other than as a location where data may be stored

B RegisterB Register



Flags are 1-bit registers provided to store the results of certain program instructionsOther instructions can test the condition of the flags and make decisions based on the flag statesFlags are grouped inside the program status word (PSW) and the power control (PCON) registers for convenient addressingMath flags: respond automatically to the outcomes of math operations (CY, AC, OV, P)User flags: general-purpose flags that may be used by the programmer to record some event in the program (F0, GF0, GF1)

FlagsFlags



PSW contains the math flags, user program flag F0, and the register select bits that identify which of the four general-purpose register banks is currently in use by the program

P--OVRS0RS1F0ACCY01234567

Program Status Word (PSW)Program Status Word (PSW)



Program Status Word (PSW)Program Status Word (PSW)

Parity flag; shows parity of register A: 1 = Odd Parity

P0

Reserved for future use--1

Overflow flag; used in arithmetic instructionsOV2

Register bank select bit 0RS03

Register bank select bit 1RS14

User flag 0F05

Auxiliary carry flag; used for BCD arithmeticAC6

Carry Flag; used in arithmetic, JUMP, ROTATE, and BOOLEAN instruction

CY7

FunctionSymbolBit



Instruction that Affect Flag BitsInstruction that Affect Flag Bits

XCJNEXRLC

Note: X can be 0 or 1XMOV C, bit

XORL C, /bitXRRC

XORL C, bitXDA

XANL C, /bitX0DIV

XANL C, bitX0MUL

XCPL CXXXSUBB

0CLR CXXXADDC

1SETB CXXXADD

ACOVCYInstructionACOVCYInstruction



A functioning computer must have memory for program code bytes, commonly in ROM, and RAM memory for variable data that can be altered as the program runs8051 has internal RAM (128 bytes) and ROM (4Kbytes)8051 uses the same address but in different memories for code and dataInternal circuitry access the correct memory based on the nature of the operation in progressCan add memory externally if needed

Internal MemoryInternal Memory



8051 Internal RAM Organisation8051 Internal RAM OrganisationR7R6R5R4R3R2R1R0R7R6R5R4R3R2R1R0R7R6R5R4R3R2R1R0R7R6R5R4R3R2R1R0

0706050403020100

0F0E0D0C0B0A0908

1716151413121110

1F1E1D1C1B1A1918

Ban

k 0

Ban

k 1

Ban

k 2

Ban

k 3

2726252423222120

2F2E2D2C2B2A2928

7F 7877 706F 6867 605F 5857 504F 4847 403F 3837 302F 2827 201F 1817 100F 0807 00 30

7F

Working Registers Bit Addressable General Purpose



Example 2Example 2--55State the contents of RAM locations after the following program:

MOV R0, #99HMOV R1, #85HMOV R2, #3FHMOV R7, #63HMOV R5, #12H

After the execution of the above program we have the following:

RAM location 0 has value 99H RAM location 1 has value 85HRAM location 2 has value 3FH RAM location 7 has value 63HRAM location 5 has value 12H



Example 2Example 2--66Repeat Example 2-5 using RAM addresses instead of register names.

This is called direct addressing mode and uses the RAM address location for the destination address.

MOV 00, #99HMOV 01, #85HMOV 02, #3FHMOV 07, #63HMOV 05, #12H



Example 2Example 2--77State the contents of RAM locations after the following program:

SETB PSW.4MOV R0, #99HMOV R1, #85HMOV R2, #3FHMOV R7, #63HMOV R5, #12H

By default, PSW.3=0 and PSW.4=0; therefore, the instruction “SETB PSW.4” sets RS1=1 and RS0=0, thereby selecting register bank 2. Register bank 2 uses RAM locations 10H – 17H. After the execution of the above program we have the following

RAM location 10 has value 99H RAM location 11 has value 85HRAM location 12 has value 3FH RAM location 17 has value 63HRAM location 15 has value 12H



SP is a 8-bit register used to hold an internal RAM address that is called the “top of the stack”Stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quicklySP holds the internal RAM address where the last byte of data was stored by a stack operationWhen data is to be placed on the stack, the SPincrements before storing data on the stack so that the stack grows up as data is storedAs data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data

Stack and Stack Pointer (SP)Stack and Stack Pointer (SP)



Stack OperationStack Operation

SP = 0A Address 0A SP = 0AStore Data Get Data

SP = 09 Address 09 SP = 09Store Data Get Data

SP = 08 Address 08 SP = 08Store Data Get Data

SP = 07 Address 07 SP = 07

Storing Data on the Stack(Increment then store)

Internal RAM(Get then decrement)

Getting Data From the Stack



Example 2Example 2--88Show the stack and stack pointer for the following. Assume the default stack area.

MOV R6, #25HMOV R1, #12HMOV R4, #0F3HPUSH 6PUSH 1PUSH 4

0B0A0908

0B0A0908

0B0A0908

0B0A0908

SP = 07

25

After PUSH 6

SP = 08

1225

SP = 09

After PUSH 1

F31225

SP = 0A

After PUSH 4



Example 2Example 2--99Examine the stack, show the contents of the registers and SP after execution of the following instruction. All values are in hex.

POP 3 ;POP stack into R3POP 5 ;POP stack into R5POP 2 ;POP stack into R2

0B0A0908

0B0A0908

0B0A0908

0B0A0908

Start SP = 0B

54F9766C

54F9766C

SP = 0AR3 = 54

After POP 354F9766C

After POP 5

SP = 09R5 = F9

54F9766C

After POP 2

SP = 08R2 = 76



Example 2Example 2--1010Show the stack and stack pointer for the following.

MOV SP, #5FHMOV R2, #25HMOV R1, #12HMOV R4, #0F3HPUSH 2PUSH 1PUSH 4

63626160

63626160

63626160

6362616025

1225

F31225

Start SP = 5F SP = 60 SP = 61 SP = 62

After PUSH 2 After PUSH 1 After PUSH 4



8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes)

Not all of the addresses from 80H to FFH are used for SFRs

Attempt to use the “empty” addresses may get unpredictable result

Special Function Registers (SFR)Special Function Registers (SFR)



Special Function Register MapSpecial Function Register MapBit addressable



Internal ROMInternal ROM

Internal ROM occupies the code address space from 0000H to 0FFFH

Program addresses higher than 0FFFH will automatically fetch code bytes from external program memory

Code bytes can also be fetched exclusively from an external memory by connecting the external access pin (EA) to ground



VCC (pin 40 - provides supply voltage of +5V)GND (pin 20)XTAL1 & XTAL2 (pins 19 & 18 - to crystal and then caps)RST (pin 9- reset)EA (pin 31 - external access)PSEN (pin 29 - program store enable)ALE (pin 30 - address latch enable)Ports 0-3

Some Important PinsSome Important Pins



I/O Ports (P0 I/O Ports (P0 -- P3) P3)

One of the most useful features of the 8051 is that it consists of 4 I/O ports (P0 - P3)

All ports are bidirectional (they can take input and to provide output)All ports have multiple functions (except P1)All ports are bit addressableOn RESET all the ports are configured as outputWhen a bit latch is to be used as an input, a “1”must be written to the corresponding latch by the program to configure it as input



Occupies a total of 8 pins (Pins 32-39)Can be used for :

Input onlyOutput onlyInput and output at the same time (i.e. some pins for input and the others for output)

Can be used to handle both address and dataNeed pull-up resistors

Port 0Port 0



Port 0 as an Output PortPort 0 as an Output Port

The following code will continuously send out to port 0 the alternating values 55H and AAH

MOV A, #55HBACK: MOV P0, A

ACALL DELAYCPL ASJMP BACK



Port 0 as an Input PortPort 0 as an Input Port

In the following code, port 0 is configured first as an input port by writing 1s to it, and then data is received from that port and sent to P1

MOV A, #0FFHMOV P0, A

BACK: MOV A, P0MOV P1, ASJMP BACK



Dual Role of Port 0Dual Role of Port 0

When connecting an 8051 to an external memory, port 0 provides both address and data (AD0 – AD7)

When ALE = 0, it provides data D0 – D7

When ALE = 1, it provides data A0 – A7

ALE is used for demultiplexing address and data with the help of a 74LS373 latch



Occupies a total of 8 pins (Pins 1-8)

Can be used as input or output

Does not need any pull-up resistors

Upon reset, port 1 is configured as an output port

No alternative functions

Port 1Port 1



Port 1 as an Input PortPort 1 as an Input PortIn the following code, port 1 is configured first as an input port by writing 1s to it, and then data is received from that port and saved in R7, R6, and R5

MOV A, #0FFHMOV P1, AMOV A, P1MOV R7, AACALL DELAYMOV A, P1MOV R6, AACALL DELAYMOV A, P1MOV R5, A



Occupies a total of 8 pins (Pins 21-28)

Similar function as Port 1

Can be used as input or output

Does not need any pull-up resistors

Upon reset, port 1 is configured as an output port

Port 2Port 2



Port 2 as an Input PortPort 2 as an Input Port

In the following code, port 2 is configured first as an input port by writing 1s to it, and then data is received from that port and sent to P1

MOV A, #0FFHMOV P2, A

BACK: MOV A, P2MOV P1, ASJMP BACK



Dual Role of Port 2Dual Role of Port 2

When connecting an 8051 to an external memory, port 2 provides both address (A8 – A15)

It is used along with P0 to provide the 16-bit address

When P2 is used for the upper 8 bits of the 16-bit address, it cannot be used for I/O



Occupies a total of 8 pins (Pins 10-17)Similar function as Port 1 and Port 2Can be used as input or outputDoes not need any pull-up resistorsUpon reset, port 1 is configured as an output portPins can be individually programmable for other usesMost commonly be used to provide some important signals (e.g. interrupts)

Port 3Port 3



Port 3 Alternate FunctionsPort 3 Alternate Functions

17RDP3.7

16WRP3.6

15T1P3.5

14T0P3.4

13INT1P3.312INT0P3.2

11TxDP3.1

10RxDP3.0PinFunctionP3 Bit



ReadRead--ModifyModify--Write FeatureWrite FeatureA method used to access the 8051 ports

Combining all 3 actions in a single instructions :Read the data at the portModify (do operation on) the data at the portWrite the results to the port

MOV P1, #55HAGAIN: XRL P1, #0FFH

ACALL DELAYSJMP AGAIN



SingleSingle--bit Addressability of Portsbit Addressability of Ports

One of the most powerful features of the 8051

Access only one or several bits of the port instead of the entire 8 bits

BACK: CPL P1.2ACALL DELAYSJMP BACK



Example 4Example 4--22

SETB P1.2MOV A, #45H

AGAIN: JNB P1.2, AGAINMOV P0,ASETB P2.3CLR P2.3

Write a program to perform the following:(a) Keep monitoring the P1.2 bit until it becomes high;(b) When P1.2 becomes high, write value 45H to port 0; and(c) Send a high-to-low (H-to-L) pulse to P2.3



General physical & operational features

8051 hardware description

8051 pin description

Read-modify-write port instructions

SummarySummary



1. In the 8051, the program counter is _________ bits wide.2. True or false. Every member of the 8051 family, regardless

of the maker, wakes up at memory 0000H when it is powered up.

3. At what ROM location do we store the first opcode of an 8051 program?

4. The instruction “MOV A, #44H” is a ______-byte instruction.5. What is the ROM address space for the 8052 chip?6. The flag register in the 8051 is called __________.7. What is the size of the flag register in the 8051?8. Which bits of the PSW register are user-definable?

Review QuestionsReview Questions



9. Find the CY and AC flag bits for the following code.MOV A, #0FFHADD A, #01

10. Find the CY and AC flag bits for the following code.MOV A, #0C2HADD A, #3DH

11. What is the size of the SP register?12. With each PUSH instruction, the stack pointer register (SP) is

_______ (incremented/decremented) by 1.13. With each POP instruction, the SP _____

(incremented/decremented) by 1.14. ON power up, the 8051 uses RAM location _____ as the first

location of the stack.




15. On power up, the 8051 uses bank ____ for registers R0 – R7.

16. On power up, the 8051 uses RAM locations _____ to _____ for register R0 – R7 (register bank 0).

17. Which register bank is used if we alter RS0 and RS1 of the PSW by the following two instruction?

SETB PSW.3SETB PSW.4

18. In Question 17, what RAM locations are used for register R0 – R7?




The 8051 Microcontroller and Embedded Systems -Using Assembly and C, Mazidi

Chapter 8 P.217 – P.227

The 8051 Microcontroller – Hardware, Software and Interfacing, James W. Stewart

Chapter 1 P.1 – P.16

Chapter 2 P.19 – P.35

Read referenceRead reference

EEE3410 Microcontroller Applications Department of Electrical

Documents

Transcript of EEE3410 Microcontroller Applications Department of Electrical