EE 330 Lecture 13 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect...

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EE 330 Lecture 13 Devices in Semiconductor Processes Diodes Capacitors MOSFETs

Transcript of EE 330 Lecture 13 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect...

Page 1: EE 330 Lecture 13 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 13 Spring 2016.pdf · Analyze circuit with model 4. ... Show difference between

EE 330Lecture 13

Devices in Semiconductor Processes

• Diodes

• Capacitors

• MOSFETs

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Diode Models

ID

VD

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Which model should be used?

The simplest model that will give acceptable results in the analysis of a circuit

Review from Last Lecture

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Example: Determine IOUT for the following circuit

10K

12V

IOUT

D1

Solution:

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

4. Validate state of guess in step 2

5. Assume PWL with VD=0.7V

6. Guess state of diode (ON)

7. Analyze circuit with model

8. Validate state of guess in step 6

9. Show difference between results using these two models is small

10. If difference is not small, must use a different model

Strategy:

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Solution:

10K

12V

IOUT

0.6V

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

1 14OUT

12V-0.6VI = .

10KmA

4. Validate state of guess in step 2

To validate state, must show ID>0

D OUTI =I =1.14mA>0

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Solution:

10K

12V

IOUT

0.7V

5. Assume PWL model with VD=0.7V, RD=0

6. Guess state of diode (ON)

7. Analyze circuit with model

1 13OUT

12V-0.7VI = .

10KmA

8. Validate state of guess in step 6

To validate state, must show ID>0

D OUTI =I =1.13mA>0

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Solution:

9. Show difference between results using these two models is small

OUT OUTI =1.14mA and I =1.13 mA are close

Thus, can conclude OUTI 1.14mA

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Example: Determine IOUT for the following circuit

10K

0.8V

IOUT

D1

Solution:

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

4. Validate state of guess in step 2

5. Assume PWL with VD=0.7V

6. Guess state of diode (ON)

7. Analyze circuit with model

8. Validate state of guess in step 6

9. Show difference between results using these two models is small

10. If difference is not small, must use a different model

Strategy:

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Solution:

10K

0.8V

IOUT

0.6V

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

20OUT

0.8 - 0.6VI =

10KA

4. Validate state of guess in step 2

To validate state, must show ID>0

D OUTI =I =20 A>0

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Solution:

10K

0.8V

IOUT

0.7V

5. Assume PWL model with VD=0.7V, RD=0

6. Guess state of diode (ON)

7. Analyze circuit with model

10OUT

0.8V-0.7VI =

10KA

8. Validate state of guess in step 6

To validate state, must show ID>0

D OUTI =I =10 A>0

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Solution:

9. Show difference between results using these two models is small

OUT OUTI =10 A and I =20 A are not close

10. If difference is not small, must use a different model

Thus must use diode equation to model the device

10K

0.8V

IOUT

0.6V

VDD

OUT

0.8-VI =

10K

D

t

V

V

OUT SI =I e

Solve simultaneously, assume Vt=25mV, IS=1fA

Solving these two equations by iteration, obtain VD= 0.6148V and IOUT=18.60μA

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Use of Piecewise Models for Nonlinear Devices when

Analyzing Electronic Circuits

Process:

1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

Observations:

o Analysis generally simplified dramatically (particularly if piecewise model is linear)

o Approach applicable to wide variety of nonlinear deviceso Closed-form solutions give insight into performance of circuito Usually much faster than solving the nonlinear circuit directlyo Wrong guesses in the state of the device do not compromise solution

(verification will fail)

o Helps to guess right the first timeo Model is often not necessary with most nonlinear devices

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Types of Diodes

Vd

Id Id

Vd

Id

VdVd

Id

Vd

Id

Vd

Id

Vd

Id

Vd

Id

pn junction diodes

Metal-semiconductor junction diodes

Signal or

Rectifier

Pin or

Photo

Light Emitting

LED

Laser Diode

Zener Varactor or

Varicap

Schottky Barrier

Vd

Id

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Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

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Capacitors

• Types

– Parallel Plate

– Fringe

– Junction

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Parallel Plate Capacitors

C

d

A1

A2

cond1

cond2

insulator

A = area of intersection of A1 & A2

d

AC

One (top) plate intentionally sized smaller to determine C

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Parallel Plate Capacitors

ACC d

d

AεC

areaunit

CapC If d

d

εCd

where

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Fringe Capacitors

d

C

d

AεC

A is the area where the two plates are parallel

Only a single layer is needed to make fringe capacitors

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Fringe Capacitors

C

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Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

ddepletion

region

C

Junction Capacitor

d

AC

Note: d is voltage dependent

-capacitance is voltage dependent

-usually parasitic caps

-varicaps or varactor diodes exploit

voltage dep. of C

d

p

n

VD

0.6VφB n ; 0.5

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Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

Junction Capacitor

0.6VφB n ; 0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

-4 -3 -2 -1 0 1

j0

C

C A

VD

Voltage dependence is substantial

VD

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Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

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n-Channel MOSFET

Poly

n-active

Gate oxide

p-sub

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n-Channel MOSFET

LEFF

L

W

Source

DrainGate

Bulk

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n-Channel MOSFET

Poly

n-active

Gate oxide

p-subdepletion region (electrically induced)

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Apply small VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0

Depletion region electrically induced in channel

IDIG

IB

Termed “cutoff” region of operation

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0Depletion region in channel becomes larger

IDIG

IB

Page 27: EE 330 Lecture 13 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 13 Spring 2016.pdf · Analyze circuit with model 4. ... Show difference between

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

ID=0

IG=0

IB=0

IDIG

IB

Model in Cutoff Region

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer forms in channel

IDIG

IB

(VDS and VBS small)

Inversion layer will support current flow from D to S

Channel behaves as thin-film resistor

Critical value of

VGS that creates

inversion layer

termed threshold

voltage, VT)

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Triode Region of Operation

OXTGS

CHCVV

1

W

LR

0II

VVVL

WμCI

BG

DSTGSOXD

For VDS small

VDS

VBS = 0

VGS

ID

IG

IB

VDSRCH

Behaves as a resistor between

drain and source

Model in Deep Triode Region

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Triode Region of Operation

OXTGS

CHCVV

1

W

LR

For VDS small

VBS = 0

VGS

ID

IG

IB

RCH

Resistor is controlled by the voltage VGS

Termed a “Voltage Controlled Resistor” (VCR)

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer in channel thickens

IDIG

IB

(VDS and VBS small)

RCH will decrease

Termed “ohmic” or “triode” region of operation

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS

ID=?

IG=0

IB=0

Inversion layer thins near drain

IDIG

IB

(VBS small)

ID no longer linearly dependent upon VDS

Still termed “ohmic” or “triode” region of operation

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Triode Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

OXTGS

CHCVV

1

W

LR

0II

V2

VVV

L

WμCI

BG

DSDS

TGSOXD

For VDS larger

Model in Triode Region

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more

ID=?

IG=0

IB=0

Inversion layer disappears near drain

IDIG

IB

(VBS small)

Termed “saturation”region of operation

Saturation first occurs when VDS=VGS-VT

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Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

VV2

VVVV

L

WμCI

V2

VVV

L

WμCI

BG

2

TGSOX

D

TGSTGS

TGSOXD

DSDS

TGSOXD

lyequivalentor

lyequivalentorFor VDS at onset of

saturation

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n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more (beyond VGS-VT)

ID=?

IG=0

IB=0

Nothing much changes !!

IDIG

IB

(VBS small)

Termed “saturation”region of operation

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Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

BG

2

TGSOX

D

For VDS in Saturation

Model in Saturation Region

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Model SummaryVDS

VBS = 0

VGS

ID

IG

IB

GS T

DSD OX GS T DS GS DS GS T

2

OX GS T GS T DS GS T

G B

0 V V

VWI μC V V V V V V V V

L 2

WμC V V V V V V V

2L

I =I =0

T

Note: This is the third model we have introduced for the MOSFET

Cutoff

Triode

Saturation

OXTGS

CHCVV

1

W

LR

(Deep triode special case of triode where VDS is small )

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End of Lecture 13