392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017

A Precision SiGe Reference Circuit Utilizing Siand SiGe Bandgap Voltage Differences

Yi Huang, Student Member, IEEE, and Laleh Najafizadeh, Member, IEEE

Abstract— Silicon–germanium (SiGe) BiCMOS technol-ogy platform provides designers with a unique opportunityto have access to both Si–Si and SiGe–Si p-n junctions.By taking advantage of the coexistence of these two p-njunctions, this paper presents a new temperature compen-sation technique for SiGe reference circuits. The source ofthe appearance of curvature in the thermal characteristicsof reference circuits is due to the fact that the temperature-dependent nonlinearities in the base–emitter junction arenot completely canceled across the temperature rangeof interest. Here, it is shown that under specific biasingconditions, the two Si–Si and SiGe–Si p-n junction volt-ages exhibit similar nonlinear temperature dependences.As such, a two-step temperature compensation technique isproposed: first, via a weighted subtraction of two currents,one proportional to the base–emitter junction of Si BJTand the other proportional to the base–emitter junctionof SiGe heterojunction bipolar transistor, major nonlineartemperature-dependent terms are canceled; second, viathe addition of a proportional to the absolute temperaturecurrent, the remaining linear temperature-dependent termis canceled. As a result of this two-step temperature com-pensation technique, an output voltage proportional to thedifference of the bandgap voltages of Si and SiGe can beobtained. The proposed compensation technique is utilizedto implement a precision reference circuit in IBM’s SiGeBiCMOS 8HP technology. Measurement results verify thestability of the circuit against temperature variations. As thegenerated output voltage of the circuit is proportional to thedifference of Si and SiGe bandgap voltages, the proposedcircuit can be utilized to experimentally evaluate the Ge-inducedbandgapoffset in a given SiGe technology platform.

Index Terms— Bandgap engineering, bandgap, bandgapreference circuits (BGRs), curvature compensation, refer-ence circuits, silicon (Si) bipolar junction transistor (BJT),Silicon–germanium (SiGe) heterojunction bipolar transis-tor (HBT).

I. INTRODUCTION

S ILICON–GERMANIUM (SiGe) BiCMOS technology,by offering high-speed, low-noise bandgap-engineered

heterojunction bipolar transistors (HBTs) while maintaining

Manuscript received October 12, 2016; revised November 28, 2016;accepted December 16, 2016. Date of publication January 5, 2017; dateof current version January 20, 2017. This work was supported in part bythe National Science Foundation under Award 1408202. This paper waspresented in part at the IEEE ISCAS 2014. The review of this paper wasarranged by Editor G. Niu. (Corresponding author: Laleh Najafizadeh.)

Y. Huang is with the Department of Electrical and ComputerEngineering, Rutgers University, Piscataway, NJ 08854, USA, and alsowith Intersil Corporation, Bridgewater, NJ 08807 USA.

L. Najafizadeh is with the Department of Electrical and ComputerEngineering, Rutgers University, Piscataway, NJ 08854 USA (e-mail:laleh.najafizadeh@rutgers.edu).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2016.2642101

integration capability with conventional silicon (Si)CMOS [1], [2], has emerged as a promising technologyplatform for the realization of a wide variety of analog, RF,and mixed-signal circuits [3]–[6]. High precision referencecircuits are needed in these and virtually all electronicsystems. A key requirement of reference circuits is togenerate a robust voltage that is invariant against temperaturevariations. Any variations in the reference voltage willdirectly affect the performance of the overall system (forexample, the resolution of data converters). The mostcommonly used topology for the realization of referencecircuits is the bandgap reference (BGR) [7]. A BGR isdesigned to generate an output voltage that is referred to thebandgap energy of the background semiconductor material.In Si-based BGR circuits, the relation to the bandgap energycan be established through the base–emitter voltage (VBE).However, VBE also depends linearly (∝ T ) and nonlinearly(∝ [T ln(T )]) to the temperature. Traditionally, a proportionalto the absolute temperature (PTAT) component is createdto cancel the linear-dependent term of VBE, known as thecomplementary to the absolute temperature (CTAT) term [7].The major problem with this approach is that the output ofBGRs will still be dependent on the temperature (due to theexistence of ∝ [T ln(T )] terms), limiting their application forhigh-performance electronics.

To date, a variety of high-order temperature compensa-tion solutions have been proposed to cancel the nonlineartemperature effects. In Si-based technologies, the majorityof the solutions are based on expressing VBE by its Taylorseries, and canceling the temperature dependencies to fewdegrees via various design techniques [7]. For example, in [8],the temperature dependence is canceled up to the secondorder via creating PT AT 2 components. In other approaches,nonlinear temperature-dependent components are generatedand used to improve the temperature stability of referencecircuits [9]–[11]. Recently, a curvature compensation tech-nique exploiting the bandgap narrowing effect was also pro-posed [12] to actively adjust the temperature characteristics ofthe BJT used in the circuit.

Compared with the Si-based technology, in SiGe BiCMOStechnology, a relatively smaller amount of work exists forreference circuits. A first-order temperature compensated BGRcircuit was realized in [13] to demonstrate the feasibility ofthis technology for implementing BGRs. The influence ofGe grading on the temperature characteristics of SiGe-basedreference circuits was investigated in [14] and [15], demon-strating that Ge grading can impact the accuracy of references.Temperature characteristics of the current gain (β) of SiGe

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HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 393

HBTs were also exploited in [3] and [16] for high-ordertemperature compensation. Recently, HBTs operating in theirinverse-mode region were also utilized for realizing referencecircuits [17]. While, these circuits have been shown to operatereliably at temperatures as low as 1 K [16], their accuracy hasnot yet reached the level of their Si-based BGR counterparts.

In this paper, a new compensation technique for SiGereference circuits is presented to improve their thermalstability. The proposed technique is motivated by two keyobservations: the existence of two p-n junctions in SiGetechnology platforms-the Si–Si p-n junction [through verticalp-n-p (VPNP) devices] and the SiGe–Si p-n junction (throughn-p-n HBTs), and the dependence of temperature-inducednonlinearities of VBE on the temperature order of the collectorcurrent. As the source of the curvature appearance in thethermal characteristics of reference circuits is due to the factthat the temperature-dependent nonlinearities in VBE are notcompletely canceled across the temperature range of interest,the proposed approach utilizes both Si–Si and SiGe–Si junc-tions, which exhibit similar temperature-dependent nonlineari-ties, under specific biasing conditions, to perform temperaturecompensation. The initial compensation concept was firstpresented in [18]. Here, the extensive theoretical discussionsare presented, and the experimental results are provided.Furthermore, it is shown that the proposed reference circuitgenerates an output voltage that is related to the differencein the bandgap voltages of Si and SiGe. As such, it can alsobe utilized to experimentally estimate the Ge-induced bandgapoffset in a given SiGe technology.

The rest of this paper is organized as follows. In Section II,the proposed compensation technique is presented. The designof a current-mode reference circuit employing the proposedcompensation technique is described in Section III. Experi-mental results are provided in Section IV, followed by discus-sions about the proposed technique in Section V. Finally, thispaper is concluded in Section VI.

II. PROPOSED COMPENSATION TECHNIQUE

In a typical SiGe BiCMOS technology platform, thedesigner has access to SiGe n-p-n HBTs as well as substrate-isolated Si VPNP transistors [19]. To describe the proposedcompensation technique, we first review the temperature char-acteristics of the base–emitter junction in Si BJTs and SiGeHBTs.

If a Si BJT transistor is biased such that its collector current(IC,BJT) follows:

IC,BJT(T ) = IC0,BJT

(T

T0

)θBJT

(1)

where T and T0 are the absolute and reference temperaturesin kelvin, respectively, IC0,BJT is the collector current at T0,and θBJT represents the order of the temperature dependencyof the collector current, its base–emitter voltage (VBE,BJT) canbe described as [20]

VBE,BJT(T ) = VG0,Si − [VG0,Si − VB E0BJT ] T

T0

−kT

q(η − θBJT) ln

(T

T0

)(2)

Fig. 1. Energy band diagram for the Si BJT and the SiGe HBT(after [2]).

where VG0,Si is the extrapolated bandgap voltage of Si at 0K (VG0,Si = (1/q)[Eg0 − Eapp

gb ], with Eg0 and Eappgb being the

bandgap energy of Si under low doping and in the presence ofheavy doping, respectively, and q being the electron charge),VB E0BJT is the base–emitter voltage at T0, k is the Boltzmannconstant, and η is a positive constant [21]. Reordering theterms in (2), VBE,BJT(T ) can be rewritten as (3) as shown atthe bottom of the next page, highlighting its two temperature-dependent terms: the linear term (∝ T ) and the nonlinear term(∝ [T ln(T )]).

In the case of SiGe HBT, the energy band diagram of agraded-base SiGe HBT is shown in Fig. 1 and is comparedwith that of the BJT [2], [22]. The introduction of composi-tionally graded Ge in the base (shown by the dashed lines)results in a finite band offset at the emitter–base junction(�Eg,Ge0) and a larger band offset at the collector–basejunction (�Eg,Ge_Wb), compared with its Si counterpart. TheGe grading (�Eg,Ge(grade)) is expressed as �Eg,Ge(grade) =�Eg,Ge_0 − �Eg,Ge_Wb.

If the SiGe HBT is biased such that its collector current(IC,HBT) follows:

IC,HBT(T ) = IC0,HBT

(T

T0

)θHBT

(4)

where IC0,HBT is the collector current at T0 and θHBT denotesthe order of the temperature dependence of the collectorcurrent, and the temperature characteristics of its base–emittervoltage (VBE,HBT) is expressed as [2]

VBE,HBT(T ) = VG0,SiGe − [VG0,SiGe − VB E0HBT] T

T0

−kT

q(l − θHBT) ln

(T

T0

)

−⎧⎨⎩

kT

qln

⎛⎝1 − exp

(−�Eg,Ge(grade)0kT0

)

1 − exp(−�Eg,Ge(grade)

kT

)⎞⎠

⎫⎬⎭

−{

kT

qln

(T0

T

�Eg,Ge(grade)

�Eg,Ge(grade)0

)}. (5)

In (5), VG0,SiGe is the extrapolated bandgap voltage of SiGeat 0 K , VB E0HBT and �Eg,Ge(grade)0 are the base–emitter volt-age and the Ge grading-induced bandgap offset at T0, respec-tively, and l is a positive constant. Assuming the temperaturedependence of Ge grading (�Eg,Ge(grade)) is negligible [2],rearranging the terms in (5) results in (6), as shown at thebottom of the next page, where the linear and nonlinear

394 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017

Fig. 2. Simulated deviation from linearity in VBE,BJT and VBE,HBT fordifferent biasing conditions.

temperature-dependent terms have been highlighted. Since theGe-induced bandgap offset is typically around 100 meV [1],the second nonlinear term in (6) can be neglected overconventional temperature ranges of interest (e.g., commercial,industrial, or military). Neglecting the second nonlinear termin (6), and comparing (3) and (6), one can see that bothVBE,BJT and VBE,HBT exhibit similar temperature-dependentterms: ∝ T and ∝ [T ln(T )].

The presence of similar temperature-dependent nonlinearterm in both VBE,BJT and VBE,HBT suggests that throughproper biasing (θBJT and θHBT) of the two transistors andappropriate weighted subtraction of the two junction voltages,the nonlinear term [T ln(T )] can be canceled.

Fig. 2 shows the deviation from linearity for thebase–emitter voltage of a Si BJT and a SiGe HBT (withidentical emitter areas) versus temperature for two differ-ent biasing conditions (collector current being temperatureindependent, and collector current being PTAT), obtainedthrough simulations. The deviation from linearity was obtainedby drawing a line between VBEs at the two temperature ends,and then subtracting this line from simulated data [14]. The

figure indicates that the deviation from linearity in both tran-sistors decreases as the order of the temperature dependence ofthe collector current increases. In addition, one can see that thedeviation from linearity of the BJT is closest to that of HBTif the BJT is biased with temperature-independent collectorcurrent and the HBT is biased with a PTAT collector current.

The expression for the weighted subtraction of the twovoltages is described in (7) as shown at the bottom ofthis page, where A1 and A2 represent the coefficientsof the linear term (∝ T ) in (3) and (6), respectively.Note that due to the inclusion of the graded Ge intothe base of SiGe HBTs, VG0,SiGe is a smaller valuethan VG0,Si.

We now summarize the proposed two-step compensationtechnique to minimize the temperature dependence of the SiGereference circuit.

Step 1: The temperature characteristics of the biasingcurrents (θBJT and θHBT) and the weighted subtraction coef-ficients α1 and α2 are set, such that the coefficient of thenonlinear term [T ln(T )] is set to zero, that is

α1

α2= l − θHBT − 1

η − θBJT. (8)

Equation (8) depends on parameters η and l, which aretypically between 3 and 4 [14]. As a rough estimate, if weassume η = l, to keep the ratio in (8) a positive value, theorder of the temperature dependence of the IC,HBT (i.e., θHBT)needs to be set to be smaller by one unit than that of IC,BJT(i.e., θBJT). For example, if the collector current of the Si BJTis designed to be PTAT (i.e., θBJT = 1 in (1)), then IC,HBTneeds to be temperature independent [i.e., θHBT = 0 in (4)].A temperature-independent current, to the first order, can begenerated through the summation of a PTAT current and aCTAT current. Alternatively, the BJT can be biased with aPTAT2 current (i.e., θBJT = 2), while the HBT is biased witha PTAT current (i.e., θHBT = 1).

VBE,BJT(T ) = VG0,Si −[

VG0,Si − VB E0BJT

T0− k

qln(T0)

(η−θBJT)

]︸ ︷︷ ︸

linear coefficient (A1)

T −[

k

q(η − θBJT)

][T ln(T )].

︸ ︷︷ ︸nonlinear

(3)

VBE,HBT(T ) = VG0,SiGe −[

VG0,SiGe − VB E0HBT

T0− k

qln

(T0

(l−θHBT−1)�Eg,Ge(grade)

�Eg,Ge(grade)0

[1 − exp

(−�Eg,Ge(grade)0

kT0

)])]

︸ ︷︷ ︸linear coefficient (A2)

T

−[

k

q(l − θHBT − 1)

][T ln(T )]

︸ ︷︷ ︸nonlinear 1

+[

kT

qln

(1 − exp

(−�Eg,Ge(grade)

kT

))]︸ ︷︷ ︸

nonlinear 2

(6)

α1VBE,BJT(T ) − α2VBE,HBT(T ) = [α1VG0,Si − α2VG0,SiGe]︸ ︷︷ ︸weighted differenceof bandgap voltages

− [α1 A1 − α2 A2]︸ ︷︷ ︸weighted difference

of linear terms

T

− k

q[α1(η − θBJT) − α2(l − θHBT − 1)]

︸ ︷︷ ︸weighted difference of nonlinear terms

[T ln(T )] (7)

HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 395

Step 2: In the second step, the linear term in (7) will becanceled. This can be achieved through the addition of a PTATcomponent, such that the linear coefficient of the PTAT current(α3) is set so

α3 = α1 A1 − α2 A2. (9)

Once the temperature-dependent parameters in (7) arecanceled, a temperature-independent output voltage related tothe weighted subtraction of the two bandgap voltages of Siand SiGe is obtained. Note that, in this step, for the completecancellation to be realizable through the addition of thePTAT component, one has to make sure that the coefficient[α1 A1 − α2 A2] in (7) remains positive after the directcancellation of the nonlinear terms. Using (8), and denotingC1 = (VG0,Si − VB E0BJT)/T0, C2 = (VG0,SiGe − VB E0HBT)/T0,and C3 = (�Eg,Ge(grade)/�Eg,Ge(grade)0)[1 −exp

(−�Eg,Ge(grade)0/(kT0))] in (6), [α1 A1 − α2 A2] can

be expressed as

[α1 A1 − α2 A2] = α1

[C1 − η − θBJT

l − θHBT − 1C2

]

+ k

qα1

η − θBJT

l − θHBT − 1ln(C3). (10)

The choice of emitter area for Si BJT and SiGe HBT and theircollector currents (defining VB E0BJT and VB E0HBT ) shouldthen be made in a way that (10) remains a positive value.

III. DESIGN EXAMPLE

In this section, the design of a current-mode referencecircuit utilizing the proposed temperature compensation tech-nique is described. The circuit consists of four main circuitblocks: the Si-based current generator, the SiGe-based currentgenerator, the PTAT current generator, and the VREF generator.Without loss of generality, for the realization of step 1 of theproposed solution, in this design, the BJT is biased with aPTAT current (i.e., θBJT = 1) and the HBT is biased with atemperature-independent current (i.e., θHBT ≈ 0).

A. Si-Based Current GeneratorThe schematic of the Si-based current generator is shown

on the left side of Fig. 3. A VPNP transistor (Q1) is biasedby a PTAT current IPTAT1. The PTAT current generator circuitwill be discussed in Section III-C. The base–emitter voltageof Q1 falls across resistor R1, generating current I1 related toVEB of Q1 as

I1(T ) = VEB,Q1(T )

R1= IVBE,BJT (T ) (10)

where VEB,Q1(T ) follows (3) with θBJT = 1. Transistors M1and M2 and M3 and M4 form a cascode current mirror, andM5 is the feedback transistor [21]. Capacitor C1 is added inthe circuit to stabilize the loop.

B. SiGe-Based Current GeneratorThe schematic of the SiGe-based current generator circuit

is shown on the right side of Fig. 3. The operation of thiscircuit is similar to that of the Si-based current generatordiscussed above, except that the HBT (Q2) is now biased

Fig. 3. Schematic of the Si-based and SiGe-based current generatorcircuits.

Fig. 4. Schematic of the PTAT current generator circuits.

with a current (IREF,1st_order) that is temperature independentto the first order (i.e., θHBT ≈ 0). This current is generatedthrough the weighted addition of the PTAT current and thecurrent generated through the Si-based current generator (I1),which decreases as the temperature increases. Proper weights(Kc and K p) are realized through the aspect ratio of thetransistors used in the current mirrors. A sink to source currentconverter, consisting of transistors MSS1-MSS6, is used for thecurrent conversion. The base–emitter voltage of HBT Q2 fallsacross resistor R2, generating current I2 as

I2(T ) = VBE,Q2(T )

R2= IVBE,HBT (T ) (11)

where VBE,Q2(T ) follows (6) with θHBT ≈ 0.

C. PTAT Current Generator

The schematic of the PTAT current generator with its startupcircuit [23] (consisting of transistors MS1–MS4) is shown inFig. 4. The core of the PTAT current generator (right sideof Fig. 4) consists of MOSFET transistors M11–M14, HBTsQ3 and Q4, and the resistor R3. The PTAT current circuitcan also be made using BJTs. We have used HBTs, sincethey offer significantly higher current gain compared withBJTs, to minimize the influence of base currents. In thiscircuit, a folded-cascode op-amp with large dc gain [11] isdesigned to enforce identical voltage levels at the invertingand noninverting input terminals (nodes A and B), ensuringthat the currents I3 and I4 are identical. The emitter area oftransistor Q3 is designed to be eight times larger than thatof Q4. The difference between the base–emitter voltages of the

396 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017

Fig. 5. Left: schematic of the VREF generator circuit. Right: diemicrophotograph of the circuit.

two transistors falls across the resistor R3, generating PTATcurrents I3 and I4 following [15]:

I3(T ) = VBE,Q4(T ) − VBE,Q3(T )

R3= k ln(n)

q R3T = IPTAT(T )

(12)

where n represents the emitter area ratio oftransistors Q3 and Q4 (here n = 8).

D. VREF GeneratorAfter the generation of the Si-based, the SiGe-based, and the

PTAT currents, a circuit needs to be implemented to properlyadd the PTAT current to the weighted subtraction of theSi-based and SiGe-based currents, so a temperature-independent output voltage is generated. As discussed, thenonlinear temperature-dependent components are canceledthrough the weighted subtraction of Si-based and SiGe-basedcurrents, and the remaining linear temperature-dependent com-ponent is canceled through the addition of the PTAT current.

Fig. 5 shows the simplified schematic of the VREF generatorcircuit. Mirrored versions of the Si-based current and the PTATcurrent will be added properly together at node VREF, while aportion related to the SiGe-based current will be taken away toimplement the weighted subtraction step. As such, VREF(T ) isexpressed as (13) as shown at the bottom of this page, whereK1, K2, and K3 are determined by the aspect ratio of thecorresponding mirroring transistors.

We now proceed with finding the required design equations,such that VREF becomes a temperature stable voltage.Following (8), to cancel the nonlinear temperature-dependentcomponent, we will have:

α1

α2= K1

K2

R2

R1= l − θHBT − 1

η − θBJT. (14)

Since in this design, θHBT ≈ 0 and θBJT = 1, and assuming

Fig. 6. Simulation results for IVBE,BJTand IVBE,HBT

(left), and IPTAT, andthe weighted subtraction of IVBE,BJT

and IVBE,HBT(right).

l ≈ η, (14) simplifies to

K1

K2= R1

R2. (15)

To cancel the linear temperature-dependent term, α3 in (14)should be set, such that (9) is satisfied. Assuming θBJT = 1,θHBT ≈ 0, and l ≈ η, the equation for canceling the linearterm is obtained as (16) as shown at the bottom of this page.Once conditions (15) and (16) are satisfied, the output voltage,related to the difference in the bandgap voltages of Si and SiGejunctions, is obtained as

VREF = K1R4

R1(VG0,Si − VG0,SiGe). (17)

These theoretically driven equations can provide guidanceand insight to designers on how to select circuit design para-meters (resistor values, current mirror ratios, and emitter arearatios) to achieve an optimum temperature coefficient (TC).Fig. 6 shows the simulations results for IPTAT, IVBE,BJT

and IVBE,HBT , and their weighted subtraction, in this design,respectively.

IV. MEASUREMENT RESULTS

The proposed reference circuit was fabricated in IBM’sSiGe 8HP BiCMOS technology. P+ polysilicon resistors wereused for all resistors, since their TC is very small. Common-centroid layout technique was employed for the realization ofthe current mirrors to minimize the effect of mismatch. The diemicrophotograph is shown in Fig. 5. The die was mounted in a28 pin ceramic DIP package and wirebonded. The package wasinserted into a zero-insertion-force socket soldered on a printedcircuit board. Temperature characterization was performedusing a ThermoJet ES precision temperature cycling systemfrom SP Scientific [24]. To minimize the loading effects ofthe measurement equipment, unity gain buffers were alsoincorporated.

VREF(T ) = R4[K1 IVBE,BJT (T ) − K2 IVBE,HBT (T ) + K3 IPTAT(T )] (13)

=[

K1R4

R1

]︸ ︷︷ ︸

α1

VEB,BJT(T ) −[

K2R4

R2

]︸ ︷︷ ︸

α2

VBE,HBT(T ) +[

K3R4k ln(n)

q R3

]︸ ︷︷ ︸

α3

T

K3

K1= q R3

k ln(n)R2

[VG0,Si − VG0,SiGe − VBE0BJT + VBE0HBT

T0+ k

qln

(�Eg,Ge(grade)

�Eg,Ge(grade)0

[1 − exp

(−�Eg,Ge(grade)0

kT0

)])](16)

HUANG AND NAJAFIZADEH: PRECISION SIGE REFERENCE CIRCUIT 397

TABLE IPERFORMANCE COMPARISON OF THE PROPOSED REFERENCE CIRCUIT WITH PRIOR SiGe-BASED BGRs

Fig. 7. Measured output voltage of the proposed reference circuit as afunction of temperature.

Fig. 7 shows the measured results for VREF of three samplesfrom different wafers as a function of temperature. Operatingwith a power supply of 3 V, unit 1 provides the best over-all thermal performance with a TC of 17.0 ppm/◦C across(−40 : 70) ◦C. The averaged TC for all measured samplesacross (−40 : 70) ◦C is 24.9 ppm/◦C. Incorporating trimmingnetworks would further improve the TC.

One important performance measure for BGR circuits is thepower supply rejection ratio (PSRR), which is indicative ofhow well they can reject the power supply noise. PSRR of theproposed circuit was measured at −70 ◦C, −30 ◦C, 0◦C and20 ◦C. As shown in Fig. 8, at all temperature points, the circuitshows PSRR less than −40 dB at 10 Hz and less than −30 dBup to 100 kHz. While this PSRR is comparable with that ofvoltage references in [13] and [25], it can be further improvedby employing PSRR enhancement techniques such as the oneproposed in [26]. Table I compares the performance of theproposed circuit with some of previously designed SiGe-basedBGR circuits. While a direct comparison is not possible (dueto differences in technology, design, and reported temperatureranges for TC), the proposed reference circuit offers the small-est TC for the best case and comparable TC for the averageacross three units, against temperature variations, verifying theeffectiveness of the proposed compensation technique.

V. DISCUSSION

The proposed temperature compensation technique,by taking advantage of the availability of two types of p-njunctions, offers a new promising approach for designinghighly stable reference circuits in SiGe BiCMOS technologyplatforms. To further evaluate the robustness of the circuitagainst process and mismatch variations, Monte Carlo

Fig. 8. Measured PSRR of the proposed reference circuit at four differenttemperatures.

Fig. 9. Distributions of VREF, from Monte Carlo simulation of 1000 runs,left figure for mismatch only, and right figure for mismatch and processvariation.

simulations of 1000 runs as well as corner simulationswere performed. Fig. 9 shows the result of Monte Carlosimulations at 25 ◦C. The coefficient of variation (σ/μ) [27]for VREF is obtained as 2.10% when mismatch is considered,and 2.83% when both mismatch and process variations areconsidered. Major sources of mismatch in reference circuitsinclude mismatch in current mirrors, transistors, and resistors.Mismatch in transistors and resistors was minimized usinglayout techniques for transistors, and realizing resistors withp+ polysilicon, which offers small temperature and voltagecoefficients, respectively. The observed variations could bedue to mismatch in current mirrors (which have also beenidentified as the dominant error in BGRs [28]). The coefficientof variation and the TC can be further improved by includingtrimming networks for R1-R3, specifically for R3, since thePTAT current plays a major role in generating IPTAT, IVBE,BJT,and IVBE,HBT. Table II summarizes the simulation results forMOS transistors corners. TC shows larger variations acrossprocess corners when T > 85 ◦C is considered (e.g., militarytemperature range). This observation could be due to the fact

398 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 2, FEBRUARY 2017

TABLE IITC AT TRANSISTOR CORNERS

that at high temperatures, the PTAT current dominates theoverall behavior, due to changes in the op-amp loop gain andthe offset voltage.

While the measurement results exhibited small TC verify-ing the effectiveness of the proposed approach in realizingprecise SiGe references, the output voltage still revealedsome levels of temperature sensitivity. Possible reasons forthe observed variations include the following. First, in thedesign example, it was considered that θHBT ≈ 0 to thefirst order. In practice, an exact θHBT = 0 is not achievedand some degree of temperature variability will exist. Devi-ation from θHBT = 0 will introduce temperature sensitivity.Alternative solutions can be considered (e.g., θHBT = 1 andθBJT = 2) to realize the proposed compensation approach.Second, post-fabrication variations, measurement setup (e.g.,the mechanical stress of the ceramic DIP packages [29]),and current mirror mismatch (as discussed above), could alsohave introduced variations during the measurement. Resis-tive trimming networks can be employed to minimize suchvariations.

An interesting aspect of the proposed compensation tech-nique is that this circuit generates an output voltage that isrelated to the “difference” of the bandgap voltages of Si andSiGe. As such, it can be utilized to experimentally estimate theGe-induced bandgap offset for different Ge grading profiles.In the circuit presented in this paper, the resistors R1 andR2 in Fig. 3 were set to 25.7 k�, resistor R4 in Fig. 5was set to 358.4 k�, and the mirroring ratios K1 and K2were both set to 1. Plugging these numbers and measuredVREF into (17) results in the bandgap voltage differenceof 87.2 mV.

VI. CONCLUSION

In this paper, a new temperature compensation techniquebased on the weighted difference of Si–Si and SiGe–Sip-n junction voltages for SiGe reference circuits waspresented. Unlike regular BGR circuits, in which the gen-erated output voltage is referred to the bandgap energy ofthe background semiconductor material, the circuit employingthe proposed technique can generate an output that is relatedto the difference in the bandgap voltages of Si and SiGe.As such, it can be used to experimentally evaluate the Ge-induced bandgap offset in a given SiGe technology.

ACKNOWLEDGMENT

The authors would like to thank Prof. J. Cressler and hisgroup at the Georgia Institute of Technology for their supportfor the fabrication of the chips.

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Yi Huang (S’14) received the B.Sc. degreein electronic information engineering fromthe Beijing University of Aeronautics andAstronautics, Beijing, China, and the M.Sc.degree in electrical engineering from StonyBrook University, Stony Brook, NY, USA. He iscurrently pursuing the Ph.D. degree with RutgersUniversity, Piscataway, NJ, USA.

He has been with Intersil Corporation,Bridgewater, NJ, USA, since 2011.

Laleh Najafizadeh (S’02–M’10) received theB.Sc. degree from the Isfahan University of Tech-nology, Isfahan, Iran, the M.Sc. degree from theUniversity of Alberta, Edmonton, AB, Canada,and the Ph.D. degree from the Georgia Instituteof Technology, Atlanta, GA, USA, all in electricalengineering.

She is currently an Assistant Professor withthe Department of Electrical and ComputerEngineering, Rutgers University, Piscataway, NJ,USA.