A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling
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A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling Dian Huang Ying Qiao
description
A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling. Dian Huang Ying Qiao. Motivation. CMOS IC technology keeps further scaling SoC benefits from All-Digital PLL (ADPLL) designs Dynamic frequency scaling in CPU Fast-locked phase-locked loop (PLL) for clock generation - PowerPoint PPT Presentation
Transcript of A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling
A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling
Dian HuangYing Qiao
Motivation
CMOS IC technology keeps further scaling SoC benefits from All-Digital PLL (ADPLL) designs
Dynamic frequency scaling in CPU Fast-locked phase-locked loop (PLL) for clock generation
Tradeoffs between locking time and clock jitter
We will focus on ADPLL design with bang-bang phase detector (BBPHD) Digitally controlled oscillator (DCO) frequency-search using algorithms
with Successive-Approximation Registers (SAR)
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ADPLL Architecture Conventional vs. Proposed ADPLL Architecture
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SAR Delay-Search
Divide by 16
SAR Frequency Search
BBPHD
BBPHD
β
0
1
0
1
DCDL 0
1
0
1
αDCO
D
Q
Q /SET
/CLR
PI Controler
reset
activate
Frequency Serch Mode
+
User-Defined
SAR Delay-Search
Ref_clk Ref_clkd Clock_out
+
MUX1MUX2
MUX3
Conventional BBPHD ADPLL
Proposed BBPHD ADPLL with SAR
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Design Considerations Tradeoff exists between frequency
phase locking time and output clock jitter performance
𝑡 𝑙𝑜𝑐𝑘=𝜋
2𝜋𝑓 𝑟𝑒𝑓
× ( 𝛽𝑘𝑣𝑐𝑜− 𝑓 𝑜𝑓𝑓 )
1𝑓 𝑟𝑒𝑓
Δ 𝑡𝑝𝑝=𝑁𝑘𝑣𝑐𝑜
4𝑞2 ((1+𝐷 )4𝛼3+4 (1+𝐷 )3𝛼2𝑞+8 (1+𝐷 )2𝛼𝑞2+8 (1+𝐷 )𝑞3 )
𝑞=𝛽− 𝛼 (1+2𝐷 )2
β - Proportional path gainα – Integral path gain
– reference clock frequency – initial frequency error – system loop gain
Fast-locking Techniques
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Simultaneous frequency and phase locking Yang, JSSC ’10 – adaptive loop gain
Hung, Trans Circuit & Syst. ’11 – modified bang-bang algorithm
Detangled frequency and phase locking Chung, JSSC ’11 – BSA frequency search + TDC phase locking
Proposed ADPLL Architecture
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SAR Delay-Search
Divide by 16
SAR Frequency Search
BBPHD
BBPHD
β
0
1
0
1
DCDL 0
1
0
1
αDCO
D
Q
Q /SET
/CLR
PI Controler
reset
activate
Frequency Serch Mode
+
User-Defined
SAR Delay-Search
Ref_clk Ref_clkd Clock_out
+
MUX1MUX2
MUX3
SAR-based Frequency Search
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Set DCO[MSB]=1
Set DAC[MSB-1]=1
Tref_clk>TDivider?
Tref_clk>VDivider?
Tref_clk>VDivider?
Frequency serch done
1->MSB 0->MSB
1->[MSB-1] 0->[MSB-1]
1->[LSB] 0->[LSB]
ref_c lk=0 activate DCO & divider
ref_c lk=1 deactivate DCO & divider
activate DCO & divider
deactivate DCO & divider
ref_c lk=0
ref_c lk=1
Reference clock
Divider output
BBPHD UP signal
Oscillator output
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Falling edge of divider output does not align with that of reference clock due to delay.
Add extra delay to reference clock Once frequency search is done, CPU designer can choose
whether input clock of PLL is reference clock or its delay version based on jitter and locking requirement.
SAR-based Delay Search
DELAY[0]
DELAY[2]DELAY[1] DELAY[3]
Vdd
DELAYN[0] DELAYN[1] DELAYN[2]REF_CLK
REF_CLKD
Locking Procedure
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2 cycles delay-search, 10 cycles frequency-search for a 10 bit DCO. Remained frequency error and phase error are tiny. Locks at 790ns
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Five Stage DCO DCO consists of 960 tri-state buffer: 64 row with
each row has 15 buffers. Five extra tri-state buffer are used to drive each to
node to either Vdd or ground during reset for fast start-up
DCO Frequency Range: 0.42GHz ~ 12GHz
PI Controller
With proposed frequency-search algorithm, small and can be chosen.
needs to be several time larger than for stability, but want to be 1 or 2 to minimize the quantization noise.
Integral path code increment by 1 only when it can increment by 4
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Performance
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Key Parameter
Technology 45nm
Locking Time 790ns
Jitter RMS 1.32ps
Jitter peak-to-peak 4.56ps
Power [email protected]
Achieves 790ns locking time while maintaining 1.32ps rms jitter. Peak-to-peak jitter is too optimistic.
Comparison
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[10] Hsu [8] Kim [9] Chung [2] Tierno This Work
CMOS Process 0.18µm 0.13µm 65nm 45nm 45nm
Core Area 0.14 mm2 0.2 mm2 0.07mm2 0.07 mm2 N/A
Power 26.7mW@600MHz [email protected] 1.81mW@520MHz NA [email protected]
Output Range 62~616MHz 0.3~1.4GHz 90~527MHz 0.8~12GHz 0.42~12GHz
Locking Time NA 3.5µs NA *46 µs 790ns
Jitter RMS 7.28ps @600MHz 3.7ps @1.35GHz 8.64ps @527MHz 1ps @5GHz 1.32ps @4.5GHz
Jitter peak-to-peak 56ps @600MHz 32ps @ 1.35GHz NA NA 4.56ps @4.5GHz
Conclusion
Proposed ADPLL realizes fast-locking without sacrificing jitter performance.
790ns locking time demonstrates that it is suitable to dynamic frequency scaling.
Future work includes ADPLL with smooth frequency change so that CPU does not needs to stall its instructions.
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