A CMOS Phase Locked Loop
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CS-EE 481 Spring 2003 Founder’s Day, 2003 1 University of Portland School of Engineering A CMOS Phase Locked Loop Authors: •Dan Booth •Jared Hay •Pat Keller Advisor: •Dr. Peter Osterberg Industry Representative: •Mr. Steve Kassel (Ret.), Intel Corp.
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A CMOS Phase Locked Loop. Authors: Dan Booth Jared Hay Pat Keller. Advisor: Dr. Peter Osterberg Industry Representative: Mr. Steve Kassel (Ret.), Intel Corp. Agenda. Introduction Dan Booth Background Dan Booth Methods Pat Keller Results Pat Keller Conclusions Jared Hay - PowerPoint PPT Presentation
Transcript of A CMOS Phase Locked Loop
CS-EE 481 Spring 2003
Founder’s Day, 2003 1University of Portland School of Engineering
A CMOS Phase Locked LoopAuthors:
•Dan Booth
•Jared Hay
•Pat Keller
Advisor:•Dr. Peter Osterberg
Industry Representative:•Mr. Steve Kassel
(Ret.), Intel Corp.
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Agenda
• Introduction Dan Booth
• Background Dan Booth
• Methods Pat Keller
• Results Pat Keller
• Conclusions Jared Hay
• Demonstration Jared Hay
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Introduction
• Special Thanks– Dr. Peter Osterberg
– Mr. Steve Kassel
– Dr. Wayne Lu
– Ms. Sandra Ressel
– MOSIS Educational Program
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Introduction
• Project problem definition:– Synthesize 90-110kHz from a 1kHz reference
• Why frequency synthesis?– Frequency generator– Signal conditioning – Clock multiplication
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Introduction
• Goals– Understanding of our Phase Locked Loop:
• Architecture
• Operation
• Applications
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Background
• Phase Locked Loop Architecture
Phasefrequency
detector
Loopfilter
VCO
FrequencyDivider
finfout
N Contro
l
CMOS Chip
VC
fd
Verror
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Background
• What our PLL frequency synthesizer does:– Produces an output of 90-110kHz in 1kHz increments
• fin = 1kHz
• N = integers from 90 to 110
• fout = N*fin = 90 – 110kHz
• Key functional specifications:– fin and fout are 0 to 5 volt digital signals
– Lock range of 90 – 110kHz
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Background
Situation A:Frequencies are in phase - VC held constant
Situation B:fin leads fd - VC increases
Situation C:fd leads fin - VC decreases
fin
fd
verror
fin
fd
verror
fin
fd
verror
fd
fd
Phase Lock Feedback
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Methods
Phase I:
Research of PLLs
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Methods
Phase II: Design of Chip• B2Logic Simulations
- Phase Frequency Detector- Frequency Divider
• Custom Design!
• TPR File- CMOS Chip Layout
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Methods
Phase III: Building• Macromodel of Chip• VCO configuration
- set control voltage range, VC
- set output frequency range
• Loop Filter- 2nd order low pass filter- set pole and zero for stability
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Methods
• Closing the feedback loop- Achieving lock
• User interface- N-Control switches- Seven-segment displays
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Results
• Digital CMOS Chip– Frequency Divider– Phase Frequency Detector
=
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Results
• Off Chip Components– Loop Filter– Voltage Controlled
Oscillator
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Conclusions
• CMOS Chip works!• Operation is stable• Increased Performance
– Output range: 51 – 127kHz
• Limited by VC range of 0-5 V
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Conclusions
• Possible Improvements– Increase reference frequency accuracy
• Crystal oscillator
• Applications– Frequency generator
– Signal conditioning
– Clock multiplication
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Demonstration
• Power up
• fout displayed on scope- fout is N times fin
- Lock is achieved quickly
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Questions?
