Analysis and Comparison of Phase Locked Loop

Techniques for Grid Utility ApplicationsL. R. Limongi, R. Bojoi, C. Pica, F. Profumo and A. Tenconi

Politecnico di Torino, Department of Electrical Engineering, Torino - Italy

Abstract- This paper presents an analysis and comparison ofPhase Locked Loop techniques used in grid utility applicationsto find the voltage vector angle generated from the supplyvoltages. The Phase Locked Loop (PLL) has a wide rangeof applications as Distributed Generation (DG), Flexible ACTransmission Systems (FACTS), static VAR compensators,cycloconverters, Active Power Filters (APF's) and others systemsconnected to the utility. The performance of these systems ingrid connected applications is strongly influenced by the adoptedPLL strategy. For this reason, the goal of the proposed paper isto present a comparison of different PLL-based techniques forutility applications to indicate the appropriate solution dedicatedto a specific application. The criteria to compare the PhaseLocked Loops techniques is the performance under distortedand unbalanced supply voltages.

Index Terms Grid applications, Phase Locked Loop, Utilityvector angle.

I. INTRODUCTION

During the last decade it has been noted an increasedinterest for power electronics for grid utility applications. Itcan be mentioned here Distributed Generation (DG) systemsfor three-phase and single-phase grids, Flexible AC Transmis-sion Systems (FACTS), Active Power Filters (APF), ActivePower Rectifiers (APR) etc. For these utility applications, apower electronic converter is connected to the distribution gridand for this reason it is often necessary to get the voltagevector position of the grid voltage at the converter's couplingpoint. In many cases the distribution grid exhibits distortedand unbalanced voltages, especially in industrial environmentswhere front end diode/thyristor rectifiers are intensively used.In this case, the scheme used to obtain the voltage vectorposition must mitigate with all these effects and stronglyinfluence the performance of the whole control scheme of thegrid connected power converter.The literature presents different solutions to compute the

voltage vector angle. One of the first techniques was the zerocrossing method which presents poor performance because thezero crossing points are only detected at every half cycle ofthe utility voltage frequency [1]. Another alternative to findthe phase angle of the utility grid voltage is obtained byfiltering the voltages signals in o3 or dq reference frames [2],[3]. However, the delay introduced by the filters representsa drawback for these techniques; their performance are notsatisfactory, as shown detailed in [2].

In [4], an Enhanced PLL (EPLL) based on non-lineardynamical system is presented. For each phase of the threephase system, an EPLL is used. The phase voltages and

their respective 90-degrees shifted waveforms detected by eachEPLL are used by an Instantaneous Symmetrical Components(ISC) method to detect the positive sequence voltage of thethree-phase system. After that, a fourth EPLL uses the outputof the ISC scheme to estimate the angle of the positivesequence voltage [4], [18].Among the various solutions to compute the voltage vector

angle, the Synchronous Reference Frame (SRF)-PLL-basedschemes are the more addressed [5]-[18] (for single-phase andthree-phase systems), with single-phase systems presented in[5]-[8], and three-phase implementations in [10]-[18]. In [11],this SRF-PLL topology is presented; the scheme is extremelysimple but is sensitive to voltage distortions/unbalances. Forthis reason, improved versions of SRF-PLL are presented withthe objective of overcome these problems. In general, theseimproved versions uses specific "filtering" techniques in orderto deliver a non distorted signal to the SRF-PLL. Some ofthese techniques, employ sinusoidal signal integrators to getrobustness against utility voltage distortions and imbalances[16]-[18]. Further, a Double Synchronous Reference FramePLL (DSRF-PLL) [12], [13] is introduced as an optimal solu-tion for utility grids with unbalanced voltages. These solutionsare different in terms of complexity, performance and easinessof implementation with industrial processors. For this reason,the goal of the proposed paper is to present a comparisonof different PLL-based techniques for utility applications toindicate the right solution dedicated to a specific application.The compared PLL schemes are:

. Synchronous Reference Frame PLL (SRF-PLL). Thisscheme is simple and used in almost all PLL techniquesfor three-phase systems [ 1];

. Double Synchronous Reference Frame PLL (DSRF-PLL).This technique is based on the separation of the positiveand negative sequences and was introduced as an optimalsolution for utility grids with unbalanced voltages [12],[13];

. Synchronous Reference Frame PLL with Positive Se-quence Filter (PSF-PLL). This strategy employs sinu-soidal signal integrators (SSI) as a positive sequencefilter;

. Synchronous Reference Frame PLL with Sinusoidal Sig-nal Integrator (SSI-PLL). This techniques uses a differentstrategy of SSI filter to avoid distortions on the voltagevector angle [17];

. Double Second Order Generalized Integrator PLL

1-4244-0844-X/07/$20.00 ©2007 IEEE. 674

(DSOGI-PLL). This is another method that uses SSIfilters to find the fundamental positive sequence fromsupply voltages [18].

The methods are compared from the following characteris-tics:

* Distortion rejection;* Unbalance robustness;. Amplitude of positive sequence detection;. Structural simplicity.The possibility to operate with single phase distribution grid

is also an issue to be evaluated. All compared PLL techniqueshave been simulated in Matlab/Simulink and simulation resultsare presented. The simulation conditions have been chosenaccording to real operating conditions of a grid connectedconverter in industrial environments. For example, all PLLsolutions are tested with supply voltages affected by notches;this situation is typical for grids supplying front-end thyristorrectifiers. Some simulation conditions (such as the unbalancedsupply voltages) are worse than in real environments toemphasize the characteristics of each PLL scheme used forcomparison. In addition, experimental results are obtainedusing the dSPACE 1103 board as a control system. The abilityto find the correct angle and the transient response under theconditions above will determine the right solution to a specificapplication.

II. SYNCHRONOUS REFERENCE FRAME PHASE LOCKEDLooP

The basic configuration of PLL is shown in Fig. 1 andis called SRF-PLL [ 1]. The stationary abc voltages aretransformed in Vd, Vq voltages using the Clarke and Parktransforms (in a frame of reference synchronized to the utilityfrequency). The angle 0* is found integrating the output w*of the PI regulator which uses the error signal vq -vq in dqframe. The frequency of rotation of this reference frame isidentical to the frequency of the utility voltage. In this casethe voltages Vd and vq appear as dc quantities [11].The SRF-PLL of Fig. 1, yields to good results under

undistorted and balanced supply voltages. However, underdistorted and/or unbalanced supply voltages, the output ofthe PLL becomes distorted. A high bandwidth of the SRF-PLL increases the problems related to distortions. To reducethe effects of these distortions, the PLL bandwidth can belowered [11]. However, reducing the PLL bandwidth resultsin the increase of time response, which means that the systemcannot track the angle 0* quickly. If the supply voltages areunbalanced, the decrease of the PLL bandwidth will improvethe performance but the angle is still found with an error.To illustrate these scenarios, the SRF-PLL is simulated underthese conditions. It can be seen in Fig. 2, the performanceof SRF-PLL under unbalanced and distorted supply voltage(even if the supply voltage is usually less unbalanced anddistorted). In this simulation, the PLL was implemented witha low bandwidth.The supply voltages are initially distorted and balanced;

after about 50 ms a high impedance is connected in series

with one phase to unbalance the supply voltages. With thisPLL strategy, the voltage vector is not accurately found.

VaV

V,,

O)ff

SRF-PLL

Fig. 1. SRF-PLL scheme

200

time (ms) time (ms)

Fig. 2. SRF-PLL steady state simulation results. From top to bottom: 1-(Va, Vb, v,) (V), 2- 0, (rad).

III. DOUBLE SYNCHRONOUS REFERENCE FRAME PHASELOCKED LooP

The second technique to be compared, called Double Syn-chronous Reference Frame PLL (DSRF-PLL), is shown inFig. 4. With this PLL is possible to get the positive se-

quence voltages v+j and v+1, avoiding problems related tod q

unbalanced voltages [12], [13]. The goal of DSRF-PLL isto decouple the positive and negative sequence of a voltagevector (to overcome the problems related to imbalances). Thisdecoupling scheme is shown in Fig. 5.

In this technique, the voltage vector is decoupled into twogeneric components rotating with nw and mw frequencies,respectively:

VS0)= o n + vm =V ~.14 0, )

Vn cos(nwt + on) 1 cos(mTt + (m)s L sin(nwt + on) j + VsL sin(mwt+ $m) (1)

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0) 20 40 6 0 0222001

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180

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5 0=-180 ~

0 20 40 60 80 100 120

-o100

010

7

5a)

1 ;/

0 20 40 60

time (ms)

80 100 120

Vs"I

separate the positive and negative sequences where n = +1and m =-1. Therefore, the positive sequence voltage vsq+1can be used as the vq signal in the scheme of SRF-PLL shownin Fig. 1.

VaVb

vc

Fig. 3. SRF-PLL transient response with distorted and unbalanced voltages.From top to bottom: 1- (va, Vb, vC) (V), 2- (v,, v3) (V), 3- Vd (V), 4- 0,(rad).

v

where n and m can be the positive and negative sequence +1and -1. The vector v, consists of two subvectors: vj , rotatingwith a angular frequency nw, and v', rotating with a angularfrequency mw.

It will be considered two rotating reference frames, dqn anddqm, whose angular positions are nO' and mO' (being 0' thephase angle of PLL). Expressing the voltage vector on eachreference frame and considering that 0' = wt, where w is thefundamental supply frequency, will result in:

EVsd- 1 Fr 1O(nVS(dqn) = LV = Ls(on) +

+Vss,)( sm)cos((n-m)wt) +-sM((n(- m)wt) ]

+Vs'msin(qsm) sin((n-)) ]

V1mVSd

Vs(

(2)VI

EVsdTn 1 Fm1o (VS(dqT) L V = Vs L +jvs[n sin(om) +

+v5 cos(&,) [ cos((n- m)wnt) 1 +[ sM((n(- m)wt) ]

+ nsj (q5n) [ cos((n-

The amplitude of the signal oscillating in the dq', shownin (2), depends on the mean value of the signal in the dqmaxes (mean value of (3)), and vice versa. The decoupling cellshown in Fig. 5 is based on this principle. In the Fig. 6 isshown the block diagram of the two decoupling cells used to

Fig. 6. Scheme of positive and negative sequences decoupling.

Simulation results of this PLL technique are shown in Fig.7. This technique was proposed with the intention to avoid thedistortions caused by unbalanced supply voltages. Therefore,

676

20 40 60 80 100 120

Fig. 4. DSRF-PLL scheme.

_O VSd

Fig. 5. Decoupling scheme of DSRF-PLL.

VsqM

-* Vsdn

q

- m)t) 1

m)wt) (3)0*

DC(n )

VaVbV0

Fig. 9. PSF-PLL and SSI-PLL scheme.

7

6-

5-

< 3 /

2

0 20 40 6time (ms)

7

6-

5-

a) 4

< 3

2

30 0

Fig. 7. DSRF-PLL steady state response with distvoltage. From top to bottom: 1- (Va, Vb, vc) (V), 2- 0

n3 C

o) ,

> t

400

200

_200n b

SSI filter and the SRF-PLL. The use of SSI filters allowsdelivering the fundamental positive sequence to the SRF-PLL, avoiding problems related to voltage distortions andimbalances. The configuration of the SSI filter, shown in Fig.10, is described in [16].

/L The simulation results are shown in Fig. 11. The supply20 40 60 voltages are unbalanced (first case), distorted and also in

time (ms)presence of line notches (second case). Even in these adverse

torted and unbalanced conditions, the PSF-PLL calculate correctly the angle. The(rad). transient response of the PSF-PLL under these adverse condi-

tions is shown in Fig. 12.

-400'0 20 40 60 80 100 120

180 -

0

180_0 20 40 60 80 100 120

180

140

100l0 20 40 60 80 100 120

7

5

0 20 40 60 80 100 120

time (ms)

Fig. 8. DSRF-PLL transient response with distorted and unbalanced voltages.From top to bottom: 1- (Va, Vb, v,) (V), 2- (v, v3) (V), 3- Vd (V), 4- 0,(rad).

the presence of distortion and line notches (on supply voltages)inserts distortions in the estimated angle. Better results can beobtained if the bandwidth of the DSRF-PLL is decreased (inthe same way as done for SRF-PLL). However, reducing thePLL bandwidth will result in the increase of the time response.The application target of PLL must dictate how much ispossible to reduce this bandwidth. The transient response forthe DSRF-PLL is shown in Fig. 8.

IV. SYNCHRONOUS REFERENCE FRAME PHASE LOCKEDLoop WITH POSITIVE SEQUENCE FILTER

The third PLL technique used in this comparison is shownin Fig. 9. It uses digital resonant elements [19] as sinusoidalsignal integrators (SSI). The SSI was introduced in [16] toimprove the PLL characteristics. It is basically formed by an

V. SYNCHRONOUS REFERENCE FRAME PHASE LOCKEDLooP WITH SINUSOIDAL SIGNAL INTEGRATOR

The fourth PLL strategy has the same structure of PSF-PLLshown in Fig. 9. However, the SSI filter is built with anotherSSI structure that filters only the vc, voltage [17] as shownin Fig. 13. The vo voltage is calculated from v, (with thefact that the ao3 voltages are delayed of 90 degrees) and itmakes possible to avoid systems distortions and imbalances.The sign of vo is chosen by a sequence detector. If the voltagesequence is known in advance, the sequence detector can beeliminated. Filtering v, guarantees that distortions will notfeed the PLL. Moreover, calculating vo from vc, guaranteesthe same amplitude to both a and Q voltages, thus avoidingimbalances to PLL input of Fig. 1.As v8 is calculated from vO, the amplitude of the positive

sequence component is not precisely found (if the supplyvoltages contains a high amount of negative sequence). How-ever, as the amplitude of vc, and v8 are the same, the angleis correctly determined. In general, the single phase PLL'sutilizes the same structure of the Fig. 1 with some strategyto generate a component 90 degrees delayed [5]-[8]. Thus,the SSI-PLL can be successfully used also in single-phasesystems. In Figs. 14 and 15 are shown the good response ofthe SSI-PLL in the same condition of the former PLL's. It canbe noted, in Fig. 15, that the vd value is different from thatone calculated using the PSF-PLL. The digital implementationof the SSI filter is described in [17].

VI. DOUBLE SECOND ORDER GENERALIZED INTEGRATORPHASE LOCKED LooP

The DSOGI-PLL utilizes the same principle of SSI-PLLand PSF-PLL. However, in this case, two SSI filters (calledDSOGI-Quadrature Signal Generator, DSOGI-QSG) are usedallowing the correct computation of the positive sequencecomponent amplitude. The Fig.16 shows the scheme of this

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Va,fil

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V,flt

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VP,filltV3X

VP

Fig. 10. Positive Sequence Filter used in PSF-PLL.

200

100

2 100

60

Fig. 13. Sinusoidal Signal Integrator filter scheme used in SSI-PLL.

7

6-

5-

MID

3

2

0 20 40 60

time (ms)

7

6-

5

3

2

00 20 40 60

time (ms)

7

6-

5

3i4

3

2

6

5

3 /

2

20 40 60 0 20 40 60

time (ms) time (ms)

Fig. 11. PSF-PLL steady state response under distorted and unbalancedsupply voltages. From top to bottom: 1- (V,, Vb,Vm) (V), 2- 0, (rad).

400200

= 0

? _200-400 a b c

0 20 40 60 80 100 120

E0

1800 20 40 60 80 100 120

180

ID> 0

1800 20 40 60 80 100 120

180

> 140-

100_0

a) 5

1 _

100 _20 40 60 80 100 120 0| a1 7

7

0,(D5-

20 40 60

time (ms)

80 100 120

Fig. 14. SSI-PLL steady state response under distorted and unbalancedsupply voltages. From top to bottom: 1- (va, Vb, vC) (V), 2- 0, (rad).

400200

a 00U) >_200

400 C0 20 40 60 80 100 120

180wE

0

1800 20 40 60 80 100 120

180

~3> 0

1800 20 40 60 80 100 120

180

> 140-

20 40 60 80 100 120

20 40 60 80 100 120

time (ms)

Fig. 12. PSF-PLL transient response with distorted and unbalanced voltages.From top to bottom: 1- (Va, Vb, vc) (V), 2- (va, v3) (V), 3- (Vafilt, Vafilt)(V), 4- Vd (V), 5- 0, (rad).

Fig. 15. SSI-PLL transient response with distorted and unbalanced voltages.From top to bottom: 1- (Va, Vb, vc) (V), 2- (va, vo) (V), 3- (Vafilt, Vaf ilt)(V), 4- Vd (V), 5- 0, (rad).

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o2100-G

7Fr r

VaVb

Vc

Fig. 16. DSOGI-PLL scheme6

5

m 4

3-

2 -

1-

0-L0 ) 20 40 60

7

6-

5-

C:4

3

2

0 20 40 60

time (ms) time (ms)

Fig. 18. DSOGI-PLL steady state response with distorted and unbalancedvoltage. From top to bottom: 1- (Va, Vb, vc) (V), 2- 0, (rad).

...........................DSOGI-QSG

Fig. 17. DSOGI-QSG filter scheme.

PLL strategy. The supply voltages va, Vb and v, are trans-formed in ao3 components and a DSOGI-QSG filter is usedwith a Positive Sequence Calculation (PSC) to deliver thepositive sequence of fundamental frequency to the SRF-PLL.The configuration of the two SSI filters are shown in Fig. 17.

In fact, the SSI filter used to construct the DSOGI-QSG is thesame of Fig. 13 (used in SSI-PLL) implemented in a differentway. In [18] is shown that the positive sequence componentsof supply voltages into o/3 reference frame can be expressedby:

[v+d0=20 l vad, q = e-i 2 (4)

where q is a phase-shift operator in the time-domain whichobtains the quadrature-phase waveform of the original wave-form. The DSOGI filter plus PSC are implemented accordingwith (4). To make this PLL topology robust against frequencyvariations, the angular frequency w* of PLL is used to dynam-ically adapt the DSOGI resonant frequency.

In Figs. 18 and 19 are shown the simulation results obtainedfor this PLL topology.

VII. EXPERIMENTAL RESULTS

In order to verify the simulation results, experimental resultswere obtained using a three-phase diode rectifier to distort the

200_2:, 200

) 400 -084000 20 40 60 80 100 120

180

CZ 0

-1800 20 40 60 80 100 120

180

3> 0

-1800 20 40 60 80 100 120

180

> 140-

1000

7

a) 50,5c: 30

1 "0

20 40 60 80 100 120

20 40 60

time (ms)

80 100 120

Fig. 19. DSOGI-PLL transient response with distorted and unbalancedvoltage. From top to bottom: 1- (Va, Vb, vc) (V), 2- (va, v3) (V), 3- (vffilt,V8filt) (V), 4- Vd (V), 5- 0, (rad).

supply voltages (a common situation found in industry) and ahigh impedance connected in one phase to simulate a set ofunbalanced voltages.The experimental results for the SRF-PLL are shown in Fig.

20(a). The supply voltages are initially distorted and balanced;approximately after 40 ms, the impedance is connected tounbalance the supply voltages. At this moment the anglebecomes considerably distorted and the SRF-PLL is not able tocalculate the Vd component. This results shows the SRF-PLLintolerance to imbalances. The experimental results for DSRF-PLL are shown on Fig. 20(b). This PLL topology calculatesthe position of voltage vector with a good approximationconsidering the highly distorted supply voltages.The same experiment is done for the SSI-PLL. Although

679

a1)

a)C)g

0)

0-

.(0)

7

400

200

0

-200-

-4000 20 40 60 80 100 120

0

-1800 20 40 60 80 100 120

180k n n

>,>200400 1

0 20 40 60 80 100 120

' E

U) 0

0 20 40 60 80 100 120

1870 ,

> 150

20 40 60 80 100 120 130

20 40 60

time (ms)

80 100 120

5

1 0X0

20 40 60 80 100 120

20 40 60

time (ms)

8080 100 120

(a) SRF-PLL. From top to bottom: 1- (Va, Vb, v,) (V), 2- (va,, v3) (V),3- Vd (V), 4- 0, (rad).

(b) DSRF-PLL. From top to bottom: 1- (Va, Vb, v,) (V), 2- (va,, v3) (V),3- Vd (V), 4- 0, (rad).

Fig. 20. Experimental results for SRF-PLL and DSRF-PLL.

400C1D200

U) ° -200A-400

0 20 40 60 80 100 120200

wE0

-2000 20 40 60 80 100 120

180 =

oc> 0

180

0 20 40 60 80 100 120

170

> 150

130_0

7

130_20 40 60 80 100 120 0

.1 Ml AlF-7

400lllll200

') ° -200-400 a b c

0 20 40 60 80 100 120180

wE0

1800 20 40 60 80 100 120

180

~5 > 0

1800 20 40 60 80 100 120

170 T

> 150

20 40 60 80 100 120

cz53t 5 E

___"1I_

0 20 406080 100 120 0 20 40 6080100 120

time (ms) time (ms)

(a) SSI-PLL. From top to bottom: 1- (Va, Vb, Vc) (V), 2- (va, v3) (V),3- (VOgfiit, vafilt) (V), 4- Vd (V), 5- 0, (rad).

(b) DSOGI-PLL. From top to bottom: 1- (Va, Vb, Vc) (V), 2- (va, v3) (V),3- (VOgfilt, vafilt) (V), 4- Vd (V), 5- 0, (rad).

Fig. 21. Experimental results for SSI-PLL and DSOGI-PLL.

the amplitude of vd components does not correspond to thepositive sequence amplitude, the PLL angle is found correctlyas shown in Fig. 21(a). The results for the DSOGI-PLL isshown in Fig. 21(b). In this case, the amplitude of positivesequence component is found accurately as can be seen bythe vd component.

The experimental results for PSF-PLL are shown in Fig. 22.The performance of this PLL (in terms of angle determination)is identical to the SSI-PLL and DSOGI-PLL. In the PSF-PLLtopology, the amplitude of positive sequence component isaccurately calculated, as DSOGI-PLL does.

VIII. CONCLUSIONS

The performance of SRF-PLL presents some problems inthe presence of distorted and unbalanced supply voltages.However, the simplicity of this structure have encouragedsome authors to propose new schmes, based on this topology.Since the PLL presents problems in the presence of distortedand unbalanced supply voltages, the idea is to use some

approach to deliver the fundamental positive sequence to theSRF-PLL. The techniques compared in this paper have beenproposed in this way.

The DSRF-PLL was presented as an optimal solution forutility grids with unbalanced voltages. The results shows thegood performance under this condition as proposed by the

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a)

n3 o

a) 0

> t

> 140

100ioo07

0Z5

1 /

0

400>': 2000L0

C') ~, 200

-400' a c0 20 40 60 80 100 120

, 8a180 Xa)E

5 0=

a)

LL t

IIII:

0 20 40 60 80 100 120180

0

-1800 20 40 60 80 100 120

170_

150

1300 20 40 60 80 100 120

7

234

0 20 40 60 80 100 120

time (ms)

Fig. 22. PSF-PLL. From top to bottom: 1- (Va,Vb,v,) (V), 2- (v, v3)(V), 3- (v,filt, vOfilt) (V), 4- Vd (V), 5- 0, (rad).

author.The PSF-PLL was the first implementation using this kind

of filter; it employs a high complexity scheme (compared withothers resonant schemes), using four resonant filters.The SSI-PLL with only one resonant filter is able to

calculate precisely the angle of the voltage vector in theadverse conditions tested in this paper. This topology is alsoable to calculate the angle in single phase systems with thesame performance. However, if the supply voltages have ahigh negative sequence component (usually, it does not occurs)and the determination of the amplitude of positive sequencecomponent is a concern, the SSI-PLL is not indicated to beused (even if the voltage vector angle is correctly calculated).The DSOGI-PLL presents a good performance under tested

conditions. This topology uses one more resonant filter relatedto SSI-PLL and is not able to detect the angle in single phasesystems. The strong points of this PLL technique are thecapacity of calculate precisely the amplitude of fundamentalvoltage and the structural simplicity.The synthesis of PLL's characteristics are shown in Table I.

The signs "+" and "-" are used to indicate the presence or not,of the characteristics compared in this paper. The SRF-PLLand DSRF-PLL are signed with "-" considering the Distortionrejection, due to bandwidth reduction to obtain satisfactoryresults. The SSI-PLL and DSOGI-PLL are considered lesscomplex in terms of easiness of implementation with industrialprocessors.

REFERENCES

[1] F. M. Gardner "Phase Lock techniques", New York: Wiley, 1979.[2] A. Timbus, M. Liserre, R. Teodorescu, F. Blaabjerg "Synchronization

Methods for Three Phase Distributed Power Generation Systems. AnOverview and Evaluation", Conf. Rec. IEEE PESC' 05, Sept. 2005pp:2474- 2481.

TABLE I

COMPARISON OF PLL METHODS

SRF DSRF PSF SSI DSOGIDistortion rejection + + +Unbalance robustness + + + +Positive seq. detection + + +Structural simplicity + + +

Single phase utilization +

[3] F. Blaabjerg, R. Teodorescu, M. Liserre, A. V. Timbus "Overview ofControl and Grid Synchronization for Distributed Power GenerationSystems", IEEE Transactions on Industrial Electronics, Vol. 53, n. 5,Oct. 2006 pp:1398 - 1409.

[4] M. Karimi-Ghartemani, M.R. Iravani "A method for synchronization ofpower electronic converters in polluted and variable-frequency environ-ments", IEEE Transactions on Power Systems, Vol. 19, n. 3, Aug. 2004pp:1263- 1270.

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[6] S. M. Silva, M. Sidelmo, L. N. Arruda and B. C. Filho "Wide BandwidthSingle and Three-Phase PLL Structures for Utility Connected Systems",Conf. Rec. EPE '91, Florence, September 1991, pp: 1660-1663.

[7] L. N. Arruda, S. M. Silva, B. J. C. Filho; "PLL Structures for UtilityConnected Systems", Industry Applications Conference, 2001. Con. RecIAS'01, Vol. 4, 2001 pp:2655 - 2660.

[8] S. M. Silva B. M. Lopes B. J. C. Filho R. P. Campana W. C. Bosventura"Performance Evaluation of PLL Algorithms for Single-phase Grid-connected Systems", Conf. Rec. IAS'04, Vol. 4, 3-7 Oct. 2004 pp:2259- 2263.

[9] G. Hsieh, and J.C. Hung, "A Phase-locked loop techniques a survey,",IEEE Transactions on Industrial Electronics, Vol. 43, n. 6, Dec. 1996pp:609 - 615.

[10] S. K Chung "A Phase Tracking System for Three Phase Utility InterfaceInverters", IEEE Transactions on Power Electronics, Vol. 15, n. 3, May2000 pp:431 - 438.

[11] V. Kaura and V. Blasko "Operation of a Phase Locked Loop SystemUnder Distorted Utility Conditions", IEEE Transactions on IndustryApplications, Vol. 33, n. 1, Jan.-Feb. 1997 pp:58 - 63.

[12] P. Rodriguez, L. Sainz and J. Bergas "Synchronous Double ReferenceFrame PLL applied to a Unified Power Quality Conditioner", Harmonicsand Quality of Power, 2002. 10th International Conference on Volume2, 2002 pp:614 - 619.

[13] P. Rodriguez, J. Pou, J. Bergas, I. Candela, R. Burgos, D. Boroyevic"Double Synchronous Reference Frame PLL for Power ConvertersControl", COnf. Rec. PESC'05, Sept. 2005 pp:1415 - 1421.

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