9/27/05 ELEC 5970-001/6970-001 Lecture 9 1

ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits

Dynamic Power: Glitch-Free ASICs

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

9/27/05 ELEC 5970-001/6970-001 Lecture 9 2

Motivation• Application Specific Integrated Circuit

(ASIC) chips employ standard cell design style.

• Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design.

• Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 3

Power Dissipation in CMOS Logic (0.25µ)

%75 %5%20

Ptotal (0→1) = CL VDD2

+ tscVDD Ipeak + VDDIleakage

CL

9/27/05 ELEC 5970-001/6970-001 Lecture 9 4

Prior Work: Hazard Filtering

• Glitch is suppressed when the inertial delay of gate exceeds the differential input delay.

1 or 32

Filtering Effect of a gate

Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997.

or

2

2

9/27/05 ELEC 5970-001/6970-001 Lecture 9 5

Prior Work: A Reduced Constraint Set LP Model for Glitch Removal

• Satisfy glitch suppression condition at all gates:Differential path delay at gate input < inertial delay

• Use a linear program (LP) to find delays– Path enumeration avoided– Reduced (linear) size of LP allows scalability

• Design gates with specified delays• 40-60% dynamic power savings in custom design• Procedure is not suitable for pre-designed cell

libraries

Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 6

Prior Work: ASIC• J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power

Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01– Transistor sizing results in 20 - 25% savings in power– Power optimized by minimizing parasitic capacitances– No glitch reduction attempted

• Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01– Mixed Integer Linear Program (MILP) to select from different

realizations of cells such that power consumption is minimized without violating delay constraints

– Sum of dynamic and leakage power is minimized– Library contains cells of varying sizes, supply voltages, and

threshold voltages– Achieved 79% power saving on an average– No glitch reduction attempted.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 7

A Glitch-Free Design

• Balance differential delays at cell inputs:– Use Resistive Feedthrough cell delay

elements

• Automate the design– Customized delay cell generation – Insertion into the circuit

9/27/05 ELEC 5970-001/6970-001 Lecture 9 8

Delay Elements

• Inverter pair: delay controlled by W/L of transistors.

• Diffusion capacitor: n-diffusion, SiO2, polysilicon.

• Polysilicon resistor: R□L/W– Sheet resistance (0.25μ CMOS process)

• R□= 3.6Ω/square, with silicide• R□= 173.6Ω/square, with silicide masked

• Transmission gate

9/27/05 ELEC 5970-001/6970-001 Lecture 9 9

Evaluation of Delay ElementsBuffer

(a)

Vdd

GND

1 1 000

Vdd

GND

0 1 1 0a

(b)

Gate LeakageSubthreshold

9/27/05 ELEC 5970-001/6970-001 Lecture 9 10

Comparison of Delay Elements

Delay

element

Average delay

(ns)

Delay/Power

ns/μW

Delay/

Area

ns/grids

I 0.28 0.22 0.03

II 0.31 0.23 0.05

III 0.44 0.33 0.11

IV 0.35 0.22 0.16

II. n diffusion capacitor(2.7fF)

III. Polysilicon resistor (15.4kΩ)

IV. Transmission gate

I. Inverter pair

• Resistor shows– Maximum delay– Minimum power

and area per unit delay

– Hence, best delay element

• Resistive feed through cell– A fictitious buffer at

logic level

9/27/05 ELEC 5970-001/6970-001 Lecture 9 11

Resistive Feedthrough Cell

• A parameterized cell

• Physical design is simple – easily automated

• No routing layers(M2 to M5) used – not an obstruction to the router

R□*(length of poly)

Width of polyR =

S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’sThesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 12

RC Delay Model• CL varies during

transition (model not perfectly linear)

• Spectre simulation data stored as a 3D lookup table

• Average of signal rise and fall delays

• Linear interpolation used

TPLH + TPHL

2TP =

VinR

CL

Vout

CL R

TP

9/27/05 ELEC 5970-001/6970-001 Lecture 9 13

Design Optimization Flow

Design Entry

Tech. Mapping

Layout

RemoveGlitches

Find delays from LP

Find resistor values from lookup table

Generate feed through cells and

modify netlist

9/27/05 ELEC 5970-001/6970-001 Lecture 9 14

Results

Circuit

New Standard Cell Based DesignPower saved (%) in custom design

Raja et al. Area overhead

(%)Power saved

(%)

4 bit ALU 29.5 23.7 N/A

c432 114.0 50.0 35.0

C499 86.0 32.0 29.0

C880 98.0 43.0 44.0

C1355 22.0 68.3 56.0

C2670 14.0 30.0 31.0

S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’sThesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 15

Glitch Elimination on net86 in4-bit ALU

Source: Post layout simulation in SPECTRE

9/27/05 ELEC 5970-001/6970-001 Lecture 9 16

Layouts of c880

Original layout of c880 Optimized layout of c880

Power saving = 43%Area increase= 98%

9/27/05 ELEC 5970-001/6970-001 Lecture 9 17

Reference• S. Uppalapati, M. L. Bushnell and V. D. Agrawal,

“Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells,” Proc. 9th VLSI Design and Test Symp., Aug. 11-13, 2005, pp. 41-48.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 18

Conclusion• Successfully devised a glitch removal method for the

standard cell based design style• Does not require redesign of the library cells• Does not increase the critical path delay• Modified design flow maintains the benefits of ASIC

• On an average • Dynamic power saving: 41%• Area overhead: 60%

• Possible ways to reduce area overhead• Cell replacements from existing library• On-the-fly-cell design• Adjust routing delays for glitch suppression

9/27/05 ELEC 5970-001/6970-001 Lecture 9 19

Custom Design

• Model gates with input and output delays.

Gate

Output delay= d

Input 1

Input 2

d1

d2

Delay = d + d2

Delay = d + d1

0 ≤ d1, d2 ≤ ub

9/27/05 ELEC 5970-001/6970-001 Lecture 9 20

Determination of Delays• Determine the realizable upper bound (ub) on

gate input differential delay by simulation of gates and delay elements.

• Determine input and output delays for all gates for glitch suppression.

• Implement gates with required delays.• References:1. T. Raja, V. D. Agrawal and M. L. Bushnell, “Design of Variable Input Delay

Logic for Low Dynamic Power Circuits,” Proc. PATMOS, Sep 2005. 2. T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay Logic and

Its Application to Low Power Design,” Proc. 18th Int’l. Conference on VLSI Design, Jan 2005, pp. 596-603.

3. T. Raja, V. D. Agrawal and M. L. Bushnell, “CMOS Design of Circuits for Minimum Dynamic Power and Highest Speed,” Proc. 17th Int’l. Conference on VLSI Design, Jan 2004, pp. 1035-1040.

9/27/05 ELEC 5970-001/6970-001 Lecture 9 21

Implementation of Delays

Gatedelay = d+d1

VDD

d1 < d2

Delay = d2-d1

9/27/05 ELEC 5970-001/6970-001 Lecture 9 22

Design of c7552 Circuit

Un-optimizedGate Count = 3827

Transistor Count ≈ 40,000

Critical Delay = 2.15 ns

Area = 710 x 710 μm2

OptimizedGate Count = 3828

Transistor Count ≈ 45,000

Critical Delay = 2.15 ns

Area = 760 x 760 μm2(1.14)

9/27/05 ELEC 5970-001/6970-001 Lecture 9 23

Instantaneous Power by Spice

Power Saving: Peak 68%, Average 58%

9/27/05 ELEC 5970-001/6970-001 Lecture 9 24

Energy Measured by Spice

Power Saving: Average 58%