11/17/05 ELEC 5970-001/6970-001 Lecture 20 1

ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits

Test Power

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

11/17/05 ELEC 5970-001/6970-001 Lecture 20 2

Test Power Problem

• A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function.

• Power buses are laid out to carry the maximum current necessary for the function.

• Heat dissipation of package conforms to the average power consumption during the intended function.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 3

Testing Differs from Function

VLSI chip

system

Systeminputs

Systemoutputs

Functional inputs Functional outputs

Other chips

11/17/05 ELEC 5970-001/6970-001 Lecture 20 4

Basic Mode of Testing

VLSI chipTest vectors:

Pre-generated and stored in

ATE

DUT output for comparison with expected response stored in ATE

Automatic Test Equipment (ATE):Control processor, vector memory,timing generators, power module,

response comparator

PowerClock

Packaged or unpackaged device under test (DUT)

11/17/05 ELEC 5970-001/6970-001 Lecture 20 5

Functional Inputs vs. Test Vectors

• Functional inputs:• Functionally meaningful

signals• Generated by circuitry

• Restricted set of inputs

• May have been optimized to reduce logic activity and power

• Test vectors:• Functionally irrelevant

signals• Generated by software

to test faults• Can be random or

pseudorandom• May be optimized to

reduce test time; can have high logic activity

• May use testability logic for test application

11/17/05 ELEC 5970-001/6970-001 Lecture 20 6

An Example

VLSI chipBinary to decimal

converter

3-bit random vectors

8-bit1-hot

vectors

VLSI chip

system

VLSI chip in system operation

VLSI chip under test

High activity8-bit

test vectors from ATE

11/17/05 ELEC 5970-001/6970-001 Lecture 20 7

Reducing Comb. Test Power

1 1 0 0 01 0 1 0 01 0 1 0 11 0 1 1 1

V1 V2 V3

V4 V5

3 4

1

3 223

2

1

1

V1 V2 V3 V4 V5

10 input transitions

Traveling salesperson problem (TSP): Find the shortest distance closed path (or cycle) to visit all nodes exactly once.

V1 V3 V5 V4 V21 0 0 0 11 1 0 0 01 1 1 0 01 1 1 1 0

5 input transitions

11/17/05 ELEC 5970-001/6970-001 Lecture 20 8

Traveling Salesperson Problem

• A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.

• E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 9

Scan Testing

Combinational logic

Scan flip- flops

Primary inputs

Primary outputs

Scan-inSI

Scan-outSO

Scan enableSE DFF

mu

x

SE

SI

D

D

D’

D’

SO1

0

11/17/05 ELEC 5970-001/6970-001 Lecture 20 10

Example: State Machine

S5

S1

S4

S2

S3

Reduced power state encodingS1 = 000S2 = 011S3 = 001S4 = 010S5 = 100

State transitionComb. Input

changes

000 → 001 1

000 → 100 1

011 → 010 1

001 → 011 1

010 → 000 1

100 → 010 2

Functional transitions

11/17/05 ELEC 5970-001/6970-001 Lecture 20 11

Scan Testing of State Machine

Combinational logic

FF=0

FF=0

FF=1

Primary inputs

Primary outputs

Scan-in010

Scan-out100

State transition

Comb. Input

changes

100 → 010 2

010 → 101 3

101 → 010 3

Test transitions

11/17/05 ELEC 5970-001/6970-001 Lecture 20 12

Low Power Scan Flip-Flop

DFF

mu

x

SE

SI

DDFFm

ux

SE

SI

DSO

D’ D’

SO

Scan FF cell Low power scan FF cell

1

0

11/17/05 ELEC 5970-001/6970-001 Lecture 20 13

Built-In Self-Test (BIST)

Linear feedback shift register (LFSR)

Multiple input signature register (MISR)

Circuit under test (CUT)

Pseudo-random patterns

Circuit responses

BISTController

Clock

C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: KluwerAcademic Publishers, 2002.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 14

Test Scheduling Example

R1 R2

M1 M2

R3 R4

A datapath

11/17/05 ELEC 5970-001/6970-001 Lecture 20 15

BIST Configuration 1: Test Time

LFSR1 LFSR2

M1 M2

MISR1 MISR2

Test time

Te

st p

ow

er

T1: test for M1

T2: test for M2

11/17/05 ELEC 5970-001/6970-001 Lecture 20 16

BIST Configuration 2: Test Power

R1 LFSR2

M1 M2

MISR1 MISR2Test time

Te

st p

ow

er

T1: test for M1T2: test for M2

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Testing of MCM and SOC

• Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).

• Test resources (R1, . . . ) and tests (T1, . . . ) are identified for the system to be tested.

• Each test is characterized for test time, power dissipation and resources it requires.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 18

Resource Allocation Graph

T1 T2 T3 T4 T5 T6

R2R1 R3 R4 R5 R6 R7 R8 R9

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Test Compatibility Graph (TCG)T1

(2, 100)

T2(1,10)

T3(1, 10)

T4(1, 5)

T5(2, 10)

T6(1, 100)

Tests that form a clique can be performed concurrently.

Power Test time

Pmax = 4

11/17/05 ELEC 5970-001/6970-001 Lecture 20 20

Test Scheduling Algorithm

• Identify all possible cliques in TCG:• C1 = {T1, T3, T5}• C2 = {T1, T3, T4}• C3 = {T1, T6}• C4 = {T2, T5}• C5 = {T2, T6}

• Break up clique sets into power compatible sets (PCS), that satisfy the power constraint.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 21

Test Scheduling Algorithm . . .• PCS (Pmax = 4), tests within a set are ordered

for decreasing test length:• C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)• C2 = {T1, T3, T4} → (T1, T3, T4)• C3 = {T1, T6} → (T1, T6)• C4 = {T2, T5} → (T2, T5)• C5 = {T2, T6} → (T2, T6)

• Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied.

• Select test sessions to cover all tests such that the added time of selected sessions is minimum.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 22

TS Algorithm: Cover TableTest sessions T1 T2 T3 T4 T5 T6 Length

(T1, T3, T4) X X X 100

(T1, T5) X X 100

(T1, T6) X X 100

(T2, T6) X X 100

(T3, T5) X X 10

(T2, T5) X X 10

(T3, T4) X X 10

(T5) X 10

(T4) X 5

Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 23

A System Example: ASIC Z*

RAM 2Time=61

Power=241

RAM 3Time=38

Power=213

ROM 1Time=102

Power=279

ROM 2Time=102

Power=279

RAM 1Time=69

Power=282

RAM 4Time=23

Power=96

Reg. fileTime = 10Power=95

Random logic 1, time=134, power=295

Random logic 2, time=160, power=352

*Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., April 1993, pp. 4-9.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 24

Test Scheduling for ASIC Z1200

900

600

300

Po

we

r

Power limit = 900

0 100 200 300 400Test time 331

RAM 1

RAM 3

Random logic 2

Random logic 1

ROM 2

ROM 1

RAM 2

Reg. file

RAM 4

•R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175-185, June 1997.

11/17/05 ELEC 5970-001/6970-001 Lecture 20 25

References

• N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, 2003.

• E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer 2005.