Memory and I/O Interfacing

EMT 248:Design 8085 Microprocessor SystemSemester II 2013/14School of Microelectronic Engineering Universiti Malaysia Perlis

OutlineBus organizationAddress/Data BusControl BusMemory and I/OAddress DecodersI/O Mapping

Bus Organization

8085 CPU

8085 Microprocessor System Block Diagram

Example Block Diagram8085MemoryAddress BusData BusControl Bus Interface

What is an Interface?an interface is a concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software.

This allows a component, (such as a graphics card or an Internet browser), to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol.

8085Higher Address BusLower Address/Data BusALE

A15 A8AD7 AD0

Control Bus 8085 Interfacing Pins

Consists of 16 address lines: A0 A15 Operates in unidirectional mode: The address bits are always sent from the MPU to peripheral devices, not reverse. 16 address lines are capable of addressing a total of 216 = 65,536 (64k) memory locations. Address locations: 0000 (hex) FFFF (hex)The 8085 Bus Structure

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Data Bus Consists of 8 data lines: D0 D7Operates in bidirectional mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.A15A14A13A12A11A10A9A8AD7AD6AD5AD4AD3AD2AD1AD0

Lower-order AddressHigher-order Address

Data BusThe 8085 Bus Structure

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Control BusComprised of various signal lines that carry synchronization signals The MPU use such lines to perform the third function: providing timing signalsA group of signal includes:two control signals (RD/ and WR/)Three status signals ( ) to identify the nature of the operation,One special signal (ALE) to indicate the beginning of the operation.

The 8085 Bus Structure

Address/Data Bus

The higher order address bus is a unidirectinal bus.

It carries most significant 8-bits of a 16-bit address of memory or I/O device.

Address remains on lines as long operation is not completed.Higher Order Address Bus

This bus is bidirectional and works on time division multiplexing between address and data.

During first clock cycle, it serves as a least significant 8-bits of memory/ IO address.

For second and third clock cycles it acts as data bus and carries data. Lower Order Address/Data Bus

How the processor knows the Lower Order bits is for Address or Data?

Question Demultiplexing (DEMUX)

A hardware register provided by the system designer to save the contents of the data bus and low order address lines.8085 microprocessor commonly uses latch to demultiplex the address and data bus.The most widely used latch for demultiplexing is 74LS373 IC. separation of address/data bus AD0-AD7 into address bus A7A0 and data bus D7D0.The data bus and low order address lines are multiplexed in order to save pin count.Demultiplexing

1st clock cycle, lower address is transferred on AD0AD7. ALE is high and latch is enabled. Address available at A0 A7. 2nd and 3rd clock cycle ALE goes low and latch is disabled. ADoAD7 will act as D0D7.How the Latch / Demultiplexer is Function?

Multiplexing

A method by which multiple digital data streams are combined into one signal over a shared medium.

Lower order address bus & Data bus are on the 8085 microprocessor multiplexed on same lines i.e. AD0 to AD7 and A8 to A15.

74LS373

Control Bus

8085 Machine Cycle Status and Control Signal

8085 Machine Cycle Status and Control Signal

Memory and I/O

Memory and I/OMemoryWhere instructions (programs) and data are storedOrganized in arrays of locations (addresses), each storing one byte (8 bits) in generalA read operation to a particular location always returns the last value stored in that location.The memory is made up of semiconductor material used to store the programs and data. The types of memory is,Primary or main memory - RAM and ROM storing a program temporarily (commonly called loading) and executing a program.speed of this type of memory should be fast.

I/O devicesEnable system to interact with the worldThe MPU views the I/O device registers just like memory that can be accessed over the bus. However, I/O registers are connected to external wires, device control logic, etc.The MPU accepts binary data as input from devices (keyboards and Analog To Digital (A/D) converters) and sends the data to output devices (LEDs and printer) Secondary memory - Floppy, Hard Disk and CD-ROMused for bulk storage of data and informationSlower and Sequential Access Nature.non-volatile nature.Memory and I/O

Address Decoders

Memory ChipMemory2n wordsk bits per word

k data input lines

k data output lines

n address linesreadwriteChip select

Interface with two memory chips11100100

11100100

A0A1Memory 1Memory 2

11100100

11100100

A0A1Memory 1Memory 2

A2011010001000

111110101100

Interface with two memory chips

In case of multiple chips, simple circuit like NOT gate will not work.

In this case normally decoder circuits like 3-to-8 decoder circuit 74LS138 are used.

These circuit are called address decoders.Interface with Multiple Chips

Using random logic - Using logic gates such as AND, OR, NOT and etc.

Using M-Line to N-Line Decoder - Use existing general decoders such as 74LS138, 74LS154 and etc.

Using PAL or FPGA - Using Programmable logic array devices such as PAL22V10 , PAL16L8 or Field Programmable Gate Array, i.e. XILINK.Interface with Multiple Chips

ExampleROM size 8K x 8 bit13 bit address line A0 - A12 213 = 8192 (0000H - 1FFFH)

RAM size 8K x 8 bit13 bit address line A0 - A12 213 = 8192 (0000H - 1FFFH)

ROM & RAM Size

Memory MapROMRAM

Not Used

0000H1FFFH2000H3FFFH4000HFFFFHRAMROM

Not Used

0000H1FFFH2000H3FFFH4000HFFFFHOR

Address Decoding A15..A12 A11..A8 A7..A4 A3..A0ROM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1RAM 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: ROM A13 = 0 , RAM A13 = 1Memory access, signal IO/M = 0

Memory Decoding Using Random Logic

A14A13A15ROM CSRAM CS

OR

Memory Decoding Using 3 to 8 Decoder(74LS138)ROM CS

RAM CSA13A14A15+5VIO/MGND

Truth Table 74LS138INPUTOUTPUTCBAG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y7XXX0XX11111111XXX11X11111111XXX101111111110001000111111100110010111111010100110111110111001110111110010011110111101100111110111101001111110111110011111110

Types of Address DecodingThere are two types of address decoding techniquesExhaustive DecodingPartial Decoding

Exhaustive DecodingIn this type of scheme all the 16 bits of the 8085 address bus are used to select a particular location in memory chip.Advantages:Complete Address UtilizationEase in Future ExpansionNo Bus Contention, as all addresses are unique.DisadvantagesIncreased hardware and cost.Speed is less due to increased delay.

Partial DecodingIn this scheme minimum number of address lines are used as required to select a memory location in chip.Advantages:Simple, Cheap and Fast. Disadvantages:Unutilized space & fold back (multiple mapping).Bus Contention.Difficult future expansion.

I/O Mapping

Interfacing I/O DevicesUsing I/O devices data can be transferred between the microprocessor and the outside world.This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O.The other method is serial I/O where one bit is transferred at a time using the SID and SOD pins on the Microprocessor.

Types of Parallel InterfaceThere are two ways to interface 8085 with I/O devices in parallel data transfer mode:Memory Mapped I/OI/O Mapped I/O

Memory Mapped I/OIt considers them like any other memory location.They are assigned a 16-bit address within the address range of the 8085.The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory.

I/O Mapped I/OIt treats them separately from memory.I/O devices are assigned a port number within the 8-bit address range of 00H to FFH.The user in this case would access these devices using the IN and OUT instructions only.

I/O Mapped I/OMemory Mapped I/OI/O is treated as memory.16-bit addressing.More Decoder Hardware.Can address 216=64k locations.Less memory is available

I/O Mapped I/OI/O is treated I/O.8- bit addressing.Less Decoder Hardware.Can address 28=256 locations.Whole memory address space is available.

I/O mapped I/O Vs Memory Mapped I/OMemory Mapped I/OMemory Instructions are used.Memory control signals are used.Arithmetic and logic operations can be performed on data.Data transfer b/w register and IO.

I/O Mapped I/OSpecial Instructions are used like IN, OUT.Special control signals are used.Arithmetic and logic operations can not be performed on data.Data transfer b/w accumulator and IO.

The interfacing of output devicesOutput devices are usually slow.Also, the output is usually expected to continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally.

The interfacing of output devicesTo do this, the external latch should be enabled when the ports address is present on the address bus, the IO/M signal is set high and WR is set low.The resulting signal would be active when the output device is being accessed by the microprocessor.Decoding the address bus (for memory-mapped devices) follows the same techniques discussed in interfacing memory.

The interfacing of Input devicesThe basic concepts are similar to interfacing of output devices. The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IO/RD signal is generated by combining the IO/M and the RD signals from the microprocessor.

The interfacing of Input devicesA tri-state buffer is used to connect the input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IO/RD.

Thank youQ&A