ECE 353Introduction to Microprocessor Systems

Michael Schulte

Week 13

AdministrationHomework #6 due Friday, May 9th

Reading for week 13 (serial I/O) Textbook Chapter 10 ADUC p. 62-71 Supplement #4 (Learn@UW)

Final exam on Saturday, May 17th from 7:45am to 9:45am in 3418 EH Cumulative exam covering Modules 1-6

+ Serial I/O (week 13) Review this Friday

Quiz #3 returned

Quiz #3 Data

High: 92%, Low: 66.5%Avg: 79%, Median: 80%Grade Breakdown for Quiz #3 85-100 A 80-84.9 AB 75-79.9 B 70-74.9 BC 65-69.9 C

TopicsSerial I/O Serial data transfer concepts Asynchronous and synchronous transfers UARTs

UART Interrupts Circular buffering RS-232 and flow control

ADuC7026 Serial Peripherals UART SPI I2C

Serial I/O ConceptsSerial communication transmits data one bit at a time.Why? Data transfers over long distances Reduced pin and interconnection count Easier to route with switches Eliminates parallel bus skew issues

Terminology Communications channel Simplex vs. duplex vs. half-duplex Transmission rates (baud rate vs. bit rate) Information codes Data Frames

Serial Communications Concepts -Morse CodeA .- N -. 1 .---- . .-.-.-B -... O --- 2 ..--- , --..--C -.-. P .--. 3 ...-- ? ..--..D -.. Q --.- 4 ....- ( -.--.E . R .-. 5 ..... ) -.--.-F ..-. S ... 6 -.... - -....-G --. T - 7 --... " .-..-.H .... U ..- 8 ---.. _ ..--.-I .. V ...- 9 ----. ' .----.J .--- W .-- 0 ----- : ---...K -.- X -..- / -..-. ; -.-.-.L .-.. Y -.-- + .-.-. $ ...-..-M -- Z --.. = -...-

Asynchronous vs. Synchronous

Asynchronous Communication No common clock signal between

transmitter and receiver Synchronization must be established

on a per frame basis Example – RS232

Synchronous Communication Clock is transmitted in addition to

data, or is recovered from data signal Often includes a framing signal as

well Example – I2S

Asynchronous Data TransferRS-232 signal phases Idle Start bit Data Parity Stop bit Idle or Start next frame

START D0 D1 D2 D3 D4 D5 D6 P STOPIDLEIDLE orSTART

UARTsUniversal Asynchronous Receiver-Transmitter Basic UART construction Practical UARTs

Complex I/O device functionality encapsulated behind a register interface

Control Status Data

FIFOs MODEM control signals

UART InterruptsUARTs often can generate interrupts for a number of conditions Receive data ready Receive data error

Framing, parity, overrun Modem signal status changes Transmitter buffer empty

If data available, just sent it If no data available and level sensitive

interrupts, ISR should mask the transmit interrupt and the program putting data in the queue should unmask it

Circular BufferingImplement simple FIFO queueing in software to minimize data movement.Some CPUs (especially DSPs) implement circular addressing modes in hardware for speed.

RS-232RS-232 is one of many physical-level standards for serial communications. Selected serial communications standards

RS-232 defines many aspects of the serial data channel Equipment definitions Connector construction and pin-outs Modem control signals Signal levels

RS-232 line drivers and receivers

Flow ControlA serial channel may deliver data faster than the receiving device can process.Flow control gives the receiver a way to signal the transmitter to stop transmission.Flow control can be implemented as Software

XON/XOFF flow control protocol Hardware

RTS/CTS

ADuC7026 Serial Peripherals

There are 4 serial peripherals on the ADuC7026; a UART and 3 synchronous ports (SPI and I2C)There are ten pins that are used by the serial peripherals in two modes

ADuC7026 UARTCOMCON0 Basic frame

configuration

Baud rate Basic baud rate divider Fractional baud rate

divider

ADuC7026 SPI PortThe Serial Peripheral Interface (SPI) port can be configured as a master or slave (shown below) SPI consists of 2 unidirectional data lines, a

clock line, and a chip select line

ADuC7026 I2C PortsThe Inter-Integrated Circuit (I2C) ports can operate as master or slave I2C supports multi-master buses using just 2

bidirectional lines (clock and data) Both use open-drain drivers and pull-up resistors Collisions can occur without damage – recognized when

a line will not return high after it is released

Asynchronous Communications -RS232 Framing

Back

What do you need to know in order to figure out what the data is?When should the data be sampled?

Synchronous Communications

Backframe

Clock Recovery

Back

11 1 1 1 1 10 0+V

-V

+V

-V

1

011 1 1 1 1 10 0 Raw data

RZ, bipolar

1 1 1 1 1 1 100 NRZ, Manchester

Serial Communications Standards

Back

RS-232 Connectors

Back

RS-232 Signal Levels

Back

Data signals are shown. Control signals have opposite polarity.

MAX221

Back

Basic UART ConstructionTransmitter

Receiver

shift register

clock

data holding register

controlunit

load

serial data outdata

1

data bus/wr

load

serial data in

shift

shift registerdata

data holding registerloadcontrol

unit

data bus/rd

shift

dav

ready

clock routing not shown for clarity

Back