Microprocessor System Design Lab

Sharif University of Technology

Electrical Engineering Department

Fall 2014

Outline

• Introduction

• Grading Policy

• Objective

• RISC vs. CISC

• MIPS

• Altera DE2 Board

• ARM7-TDMI

• NXP LPC2378 Board

• Laboratory in a Glance

Introduction

• Microprocessor Systems' Lab (25-723)

▫ Dr. M. Hashemi

▫ Lab Hours: Sundays 16:30 – 19:30

▫ Course Webpage:

http://microlab.ee.sharif.ir

▫ Including:

3 Labs conducted on Altera DE2 Boards

2 Labs conducted on NXP LPC2378 ARM7 Boards

Grading PolicyNote that we have no policy for (Pre)Reports late submission, so

lately submitted (Pre)Reports won’t take into account.

Objectives

• Getting to know NIOS II and ARM processor families and gathering some practical experience on both hardware and software of these processors.

• Learning about JTAG interface for Debugging and programming.

• Learning about Soft-Processors and the principles of Reconfigurable Computing.

• Familiarizing the students with different memories and different applications for them.

RISC Vs. CISC

• RISC:

▫ Reduced Instruction Set Computing

▫ A system using a small, highly-optimized set of instructions.

▫ Examples: MIPS, PowerPC, ARM

• CISC:

▫ Complex Instruction Set Computing

▫ A system using a huge set of instructions.

▫ Examples: x86, Motorola 68K

MIPS

• Microprocessor w/o Interlocked Pipeline Stages

• A RICS family

• Developed from early 32-Bit to 64-Bit Processors

• MIPS architecture greatly influenced the Later RISCs.

Altera DE2 Board

• Cyclone II FPGA Chip with 35000 LEs

• USB Blaster & JTAG

• 50-MHz and 27-MHz Clock Sources

NIOS II

• The Most Popular Soft-Core

• The world's most versatile processor

• Available for Standard-Cell ASICs through Synopsys.

• Support of hundreds of peripheral IP Cores.

• Perfect for Prototyping

• Available in 3 flavors:

▫ Fast

▫ Economy

▫ Standard

ARM Evolution

ARM7

• 32-Bit Processor

• Up to 130 MIPS

• Up to 72 MHz

• Fully static operation

• Fast interrupt response

• 32-Bit Address/Data Bus

• 3 Level pipelining

NXP LPC2378

• ARM7-TDMI Family▫ T: Thumb Support

Suited to high-volume applications with memory restrictions.

▫ D: Debug Support through JTAG▫ M: Hardware Multiplier

▫ I: ICEBreaker

• Memory:▫ 32 kB SRAM▫ 512 kB FLASH Program Memory

• Up to 32 Vectored Interrupts• USB 2.0, Ethernet, CAN, 10-Bit ADC/DAC,

4 Timer/Counters, …

NXP LPC2378 Board

• ARM7TDMI Microcontroller

• JTAG/ JLINK Support

• USB Bootloader

• 12 MHz Oscillator

What we are going to need…

NIOS II ARM7

• Quartus 9.0 or Higher

• SoPC Builder

• NIOS II Software

• Altera Monitor Program

• Keil μVision

• NXP LPC2378 Schematics

• LPC2378 Datasheets for Register Addresses

All the necessary documentations are available on the course’s webpage.

http://microlab.ee.sharif.ir/

NIOS II Labs

• 1. NIOS II Intro.▫ Learning about NIOS assembly▫ Implementation of a costume hardware▫ Debugging process

• 2. Character LCD▫ Coding in C for NIOS▫ Using interrupts▫ Usage of predefined IP cores

• 3. VGA Demonstration▫ Implementation of a Complex System

ARM7/Cortex M3 Labs

• 4. Speech Recognition

▫ Starting with calculating correlation

▫ Coding in C for ARM/NIOS II

• 5. QuadBot

▫ Technical expertise in using AVR/ARM Timers

▫ Implementation of a Robot system from A to Z

▫ Walking Algorithms

Warning

The debugging process in this labs is highly time consuming and the only possible way in

which you will see the results, is if you have studied the related documentations before the lab.