Virtual ASMC 2021 PDF Agenda

VIRTUAL ASMC 2021 AGENDA

10:00 – 10:05am Welcome Remarks Dave Anderson, President, SEMI Americas

10:05 – 10:20 Opening Remarks Conference Co-Chairs: Alexa Greer, KLA & Ishtiaq Ahsan, IBM

10:20 – 11:20 KEYNOTE—Continuing Moore’s Law Gary Patton, Corporate Vice President and General Manager, Design Enablement, Intel

11:20 – 11:35 Break. Visit Virtual Sponsor Booths

11:35am – 12:35pm WORKFORCE DEVELOPMENT PANEL— Advanced Manufacturing: Success Demands Innovation, Education, and Public-Private Partnership Panelists: Amanda Scarnatti, Senior Research Associate, Investment Research, Citi LaMar Hill, Office of the President, NY CREATES Santosh Kurinec, Professor, Rochester Institute of Technology Joel Hartman, Executive Vice President, STMicroelectronics Philip Wong, Chief Scientist, TSMC Moderator: Ed Sperling, Editor-in-Chief, Semiconductor Engineering


12:50 – 1:50 INVITED PRESENTATION—Heterogenous Integration Mukta Farooq, Distinguished Research Staff Member, IBM Research

1:50 – 2:00 Closing Remarks Conference Co-Chairs: Alexa Greer, KLA & Ishtiaq Ahsan, IBM

MONDAY, MAY 10, 2021 (Times in Eastern Daylight Times—EDT)

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10:00 – 11:00am KEYNOTE—A Reflection on the Impact of the Pandemic on the Semiconductor Industry John Pellerin, Vice President, Technology, Engineering and Quality Organization, GLOBALFOUNDRIES


11:15am – 12:40pm Live Q&A: Technical Sessions 1, 2 & 3 11:15 – 11:40am Session 1: Yield Enhancement 11:40am – 12:05pm Session 2: Yield Management 12:05 – 12:40pm Session 3: Advanced Metrology


12:55 – 2:10 Live Q&A: Technical Sessions 4 & 5 12:55 – 1:30pm Session 4: Advanced Equipment and Materials 1:30 – 2:10pm Session 5: Defect Inspection and Reduction

2:10 – 3:10 TUTORIAL—Quantum Computing Lester Lampert, Quantum Computing Engineer, Intel


TUESDAY, MAY 11, 2021 (Times in Eastern Daylight Times—EDT)

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10:00 – 10:45am INVITED PRESENTATION—Semiconductor Manufacturing Market Trends Christian Dieseldorff, Senior Principal, Semiconductors at Industry Research and Statistics (IR&S) Group, SEMI

10:45am – 12:00pm Live Q&A: Technical Sessions 6 & 7 10:45 – 11:20am Session 6: Factory Automation; Industrial Engineering 11:20am – 12:00pm Session 7: Equipment Optimization


12:15 – 1:35 Live Q&A: Technical Session 8, 9 & 10 12:15 – 12:50pm Session 8: Smart Manufacturing;| Advanced Process Control; Fabless Experience 12:50 – 1:10pm Session 9: Contamination Free Manufacturing 1:10 – 1:35pm Session 10: Innovative Silicon Devices and Processes; Advanced Patterning/Design for Manufacturability; Non-Silicon and Non-CMOS; Advanced Semiconductor Developments


01:50 – 2:50 KEYNOTE—Emerging Trends in the Global Semiconductor Market Robert Maire, President, Semiconductor Advisors


WEDNESDAY, MAY 12, 2021 (Times in Eastern Daylight Times—EDT)

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TECHNICAL PRESENTATIONS

All Technical Presentations Are Pre-Recorded and Available On-Demand Starting May 6, 2021

SESSION 1: YIELD ENHANCEMENT

Co-Chairs: Brett Williams, ON Semiconductor; Reshmi Mitra, Samsung Austin Semiconductor; Gary Green, Green Consulting; Qintao Zhang, Applied Materials; Sagar Kekare, KLA

Yield improvement in today’s fabs requires deep understanding of root cause of fails and tight process control. This session covers papers that provides details of root causes of yield fails, addresses methodologies enabling tight process control and pattern matching techniques using machine learning for accelerated yield learning.

1.1 Physical and Electrical Characterization of Deep Trench Isolation in Bulk Silicon and SOI Substrates. Moshe Agam, Rick Jerome, Lachen Boukhanfra, Masaichi Eda, Lan Su, Sallie Hose, Johan Janssens, Jaroslav Pjencak, Weize Chen, Thomas Long, Kenn Bates - ON Semiconductor

1.2 Product Yield Enhancement by Spacer Thickness Variation Reduction. Ritesh Ray Chaudhuri, William Simpson, Daniel Fedor, Prabhakar Bharatan, Joseph Thompson, Farid Sellidj, John Lee, Michael Hurt, Glen Martin - Micron

1.3 Study on Cu Ion Migration Factors and Its Mechanism. Chang Tai Nai, Xiaochong Guan, Chandrasekar Venkataramani, Tao Lin, Yonghai Li - GLOBALFOUNDRIES

1.4 Fab Fingerprint for Proactive Yield Management. David,Gross - Skywater Technology Prasad Bachiraju - Onto Innovation

1.5 Investigating the Root Cause of WAC Vt Fliers and Control Plan for RF FEM. Uzma Rana, Steven Shank, Aaron Vallett, Anthony Stamper – GLOBALFOUNDRIES

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SESSION 2: YIELD MANAGEMENT

Co-Chairs: Brett Williams, ON Semiconductor; Reshmi Mitra, Samsung Austin Semiconductor; Gary Green, Green Consulting; Qintao Zhang, Applied Materials; Sagar Kekare, KLA

Yield improvement in today’s fabs requires careful process development and proactive preventive steps for mitigating yield loss. This session covers papers detailing cobalt process development work for improved yield & reliability, preventive measures to mitigate potential yield loss during new product introductions, a detailed study of BEOL defectivity for AI applications and describes challenges of optimizing yield in fabs with a diverse product mix.

2.1 Introduction to Analog Testing of Resistive Random-Access Memory (RRAM) Devices Towards Scalable Analog Compute Technology for Deep Learning. Ruturaj Pujari, Arthur Gasasira, Youngseok Kim, Veenadhar Katagadda, Coon-Cheon Seo, Xuefeng Liu, Sean Teehan, Nicole Sauliner, Ishtiaq Ahsan, Vijay Narayanan, Taskashi Ando - IBM

2.2 Dashboard for CMOS Parametric Yield and Performance Monitoring in Semiconductor Manufacturing. William Simpson, Ritesh Ray Chaudhuri, John Lee, Michael Hurt - Micron

2.3 Machine Learning vs Deep Learning In Low Yield Wafer Map Classification. Congshu Zhou, Jason Khaw, Summer Boo, Heinmun Lam, Hingpoh Kuan, Guozhong You, Douglas Chan, Saiking Chong, Juliana Puey, Elton Ng - GLOBALFOUNDRIES

2.4 One-Chamber Workflow for STEM Examination of EBIRCH-Localized Defects. Gregory Johnson - ZEISS Microscopy

2.5 Improving Diagnosis Resolution with Population Level Statistical Diagnosis. Manish,Sharma, Gaurav Veda, Wu-Tung Cheng, Mathew Knowles - Siemens EDA Kun Young Chung, Shaun Nicholson, Soumya Mittal, Martin Parley - Qualcomm

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SESSION 3: ADVANCED METROLOGY

Co-Chairs: Franz Heider, Infineon; Ronny Haupt, NOVA Process Insight; Felix Levitov, Applied Materials; Jay Mody, GlobalFoundries; Janay Camp, KLA; Delphine LeCunff, STMicroelectronics

This session will focus on novel metrology techniques to characterize EUV resist, overlay structures, doping levels and process related properties.

Techniques that are incorporated in this session are: CD-SEM, scatterometry, machine learning, FTIR, optoacoustic method and photoluminescence.

3.1 Image based CD SEM tool Real Time Monitoring. Zheng Zou, Sengkeat Lim - GLOBALFOUNDRIES

3.2 Advanced EUV Resist Characterization Using Scatterometry and Machine Learning. Daniel Schmidt, [email protected], Karen Petrillo, Mary Breton, Jennifer Fullam – IBM Roy Koret, Igor Turovets, Aron Cepler - Nova Measuring Instruments

3.3 Multiple Layers’ Effects on OCD Measurement. Bin Zhu, Zou Zheng, Zhang Jian, Murawala Aditya, Soo Chen Lim, Stanley Wong - GLOBALFOUNDRIES

3.4 Room Temperature Micro-Photoluminescence Measurements for Monitoring Defects in Low-Energy High-Dose As and B Implanted Silicon. Zsolt Zolnai, Ferenc Korsós, Anita Pongrácz, Victor Samu, Zoltán Kiss, Bálint Fodor, János Szívós, John Byrnes – Semilab Leonard Rubin, Edward Moore - Axcelis

3.5 AI Solution in Metro Recipe Automation. Congshu Zhou, Zheng Zou, Fang Li, Sengkeat Lim, Jason Khaw, Summer Boo, Heinmun Lam - GLOBALFOUNDRIES

3.6 Lattice Scale Inspection of Semiconductor Interfaces via Non-Destructive Camera-Less Terahertz 3D Imaging. Anis Rahman - Applied Research & Photonics

3.7 Imaging of Overlay and Alignment Markers under Opaque Layers Using Picosecond Laser Acoustic Measurements. Manjusha Mehendale, A. Antonelli, Robin Mair, Priya Mukundhan - Onto Innovation Janusz Bogdanowicz, Anne-Laure Charley, Philippe Leray, Farrukh Yasin, David Crotti - IMEC

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SESSION 4: ADVANCED EQUIPMENT PROCESSES AND MATERIALS

Co-Chairs: Armando Anaya, Northrup Grumman; Thirumalesh Bannuru, Applied Materials; Katie Lutker-Lee, TEL; Satyajit Shinde, Samsung Austin Semiconductor; Leonard Rubin, Axcelis Technologies

This session focuses on the optimization of processes, techniques, and materials for advanced technology nodes extending from the current 14nm technology to 7nm and beyond.

4.1 Width Walk Control in 3D NAND Staircase Structure Etching. Chinghung Hsiao, Chen-Yu Cheng, Hong-Ji Lee, Nan-Tzu Lian, Tzung-Ting Han, Tahone Yang, Kuang-Chao Chen - Macronix International 4.2 Study of Plasma Ash Rate Enhancement by Machine Learning Models for TAT Improvement. Shaolou Jheng, Zusing Yang, Yuan-Chieh Chiu, Ming-Tsung Wu, Hong-Ji Lee, Nan-Tzu Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu, Jyunhong Wu - Macronix International 4.3 Line Width Roughness (LWR) Improvement and Queue Time Elimination by a Chlorine-Based Process in Pitch Doubling for Improving Throughput. Jeff Ye, Benjamin Ye, Thomas Esry, Ketan Deshpande, Doug Chafe, Daniel Fedor, Jing Nie - Micron 4.4 High-Temperature-Stable, Spin-On Carbon Materials for High-Aspect-Ratio Gap-Fill Applications. Carissa Jones, Runhui Huang, Zing-Fu Zhong, Sean Simmons, Joyce Lowes - Brewer Science

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SESSION 5: DEFECT INSPECTION AND REDUCTION

Co-Chairs: Alex Joseph Varghese, IBM Research; Israel Ne'eman, Applied Materials; Oliver Patterson, Hermes Microvision; Ralf Buengener, Intel; Abhishek Vikram, Anchor Semiconductor

In-line inspection is critical for modern semiconductor processing. The session talks about defect inspection/review for yield and reliability improvement for a wide range of use cases. The session also discusses new applications/methodologies for process characterization and defect classification.

5.1 A Novel Deep Learning Architecture for Global Defect Classification: Self-Proliferating Neural Network (SPNet). Yang YuanFu – TSMC Sun Min - National Tsing Hua University

5.2 Multimodal Machine Learning for Display Panel Defect Layer Identification. Janghwan Lee - Samsung

5.3 Activation and Detection of Buried Defects by Negative Mode E-Beam Inspection. RalfBuengener, Rongwei Fan, Jianze Zhao – Intel Datong Zhang, Chih-Hung Wang, Junheng Wang - Hermes Microvision

5.4 An Active Deep Learning Method for the Detection of Defects in Power Semiconductors. Marco Bellini, Peter Kaspar, Luca De-Michielis, Lars Knoll - Hitachi ABB Power Grids Georges Pantalos - ETH Zurich

5.5 Missing Via Defect Capture Enhancement Using a Novel, High-Precision Array Segmentation Inspection Technique. Graham Jensen, Vidyasagar Anantha, Alexa Greer, Raghav Babulnath, Satya Kurada – KLA Brad Austin, Shravan Matham, Alex Joseph Varghese - IBM

5.6 A Holistic Characterization Methodology for Stochastic Printing Failures in EUV Contact Holes. Jennifer Church, Brad Austin, Luciana Meli, Alex Varghese – IBM Teresa Esposito, DukKyun Moon, Nathaniel Mowell, Paz Yabbo, Uri Smolyan, Omri Baum, Aner Avakrat - Felix Levitov Applied Materials

5.7 Process Enabler and Design Opportunities for Fully Safeguarding Massive Presence of Reliability Defects. Lieyi Sheng - ON Semiconductor

5.8 Non-Contact C-V and Photoluminscence Measurements for More-than-Moore SOI devices. Jeff Gambino - ON Semiconductor John Byrnes - Semilab

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SESSION 6: FACTORY AUTOMATION, INDUSTRIAL ENGINEERING

Co-Chairs: Paul Werbaneth, Ichor Systems; Stefan Radloff, Intel; Misty Thompson, TI; Thomas Beeg, Wolfspeed

The challenges of current and future semiconductor process technologies require an increased continuous focus in improvements in factory efficiency. Utilization of cross industry best practices and automated decision-making and execution can help improve this drive for enhanced efficiency.

Presentations in this session will discuss solutions to gain more out of existing factory equipment, planning, and AMHS assets.

6.1 Automated Material Handling Systems: System of Systems Architecture Examination Semiconductor Manufacturing and Standards Perspective. Mutaz Haddin, Intel 6.2 Automated and Optimized lot-to-order Matching in 300 mm Semiconductor Facilities. Christian Flechsig, Jacob Lohmer, Rainer Lasch - Technische Universität Dresden Benjamin Zettler, Germar Schneider, Dietrich Eberts - Infineon

6.3 Enhancing Utilization and Cycle Times at Clustered Etch Tools through Concurrent Dispatching Binay Dash, Tyler Fuerst, Karthik iyer, Shiladitya Chakravorty - GLOBALFOUNDRIES

6.4 Fully Automated Real-Time Recipe Verification. Robert,Barlovic - GLOBALFOUNDRIES

6.5 Auto Chamber Validation. Srikanth Ramakrishnan, Dinesh Balasubra Manian, Broc Stirton, Shiladitya Chakravorty, Sandar Kyaw - GLOBALFOUNDRIES

6.6 Eliminate Costly Component Out Of Pocket Defect Condition During Semiconductor IC Transport/Handling. Richard Rochford, Craig Blanchette - BAE Systems Darby Davis, Jennifer Nunes - Gel-Pak

6.7 Comparative Analyses Oof Control Charts in Studying Tool Efficiency in Semiconductor Fabrication. Atirek Wribhu – GLOBALFOUNDRIES

SESSION 7: EQUIPMENT OPTIMIZATION

Co-Chairs: Jean Wynne, IBM Research; Fred Bouchard, Sparetech; Bradley Wood, Entegris; Ankit Jain, KLA

Advanced manufacturing requires fine optimization of equipment parameters. This session will cover pulsed gas delivery, CMP and laser spike annealing.

7.1 A Study on the Real-Time Flow Rate Change Monitoring Methods of Mass Flow Controller in In-Situ Semiconductor Processing. Tae Min Kim, Jae Wook Jeon - Sungkyunkwan University

7.2 The Use of Cross-Section Haze Measurements to Monitor Laser Spike Anneal (LSA) Stage Alignment. Kay Wendt – GLOBALFOUNDRIES John Newby - KLA

7.3 Design Considerations for CMP Slurry Delivery Systems. Rahul Trivedi, Thayalan Kulasingam - GLOBALFOUNDRIES

7.4 Poly CMP Process Challenges for Embedded Array Devices. Siew Wan Liew, Leong Lup San, Chong Yew Siew, Hsu Rex - GLOBALFOUNDRIES

7.5 Elimination of Low Yield with 3-9 O’clock Signature through Optimization of CMP Cleaner unit Brush Gap. Gerry Dizon, Jack Lim, Vincent Ngo, Ho MingYao - GLOBALFOUNDRIES

7.6 A Holistic Approach Toward UHP Gas Delivery System Design Reduces Stochastic Variability Of Reactant Distribution In Plasma Etch And Deposition Equipment. Christopher Davis, Sean Penley, Steven Wozniak, Phil Barros - Ichor Systems

7.7 Case Study Of Batch Wafer Implanter Dose Uniformity Improvement. Yip Siew Wah, Marisinapen Sham Sagaria, Danny Tan, Tay Kwang – Infineon

SESSION 8: SMART MANUFACTURING, ADVANCED PROCESS CONTROL, DATA MANAGEMENT, FABLESS EXPERIENCE

Co-Chairs: Agnés Roussy, EMSE; Eric Eisenbraun, SUNY Poly; Marc Bergendahl, IBM Research; Raymond Van Roijen, GlobalFoundries; Rob Pearson, RIT

Today's data: extracted, remote, zoomed, useful(?) and big!

Leverage large scale data collection and other virtual or remote mediums as well as virtualized fab engagement for the monitoring of Manufactuing Processes, Facilites Infrastructure, and Fab productivity

8.1 SM: Enhanced Defect Detection in After Develop Inspection with Machine Learning Disposition Matthew McLaughlin, Andrew Stamper, Gabriel Barber, Janice Paduano, Petra Mennell, Emerson Benn, Michael Linnane, Chetan Khatumr, Robert Issacson, Nathan Hoffman, Clayton Menser - GLOBALFOUNDRIES

8.2 SM: Predictive Maintenance of Pump and Abatement Equipment in a 300mm Semiconductor Fab. Joshua LaRose, John Barker, Boyd Finlay, Alex Trinidad, Carment Guyer, Justin Weinstein, Brian Conerney, Dana Ray, John Perry, Walter Tarnawskyi, Jeremy Lansford - GLOBALFOUNDRIES

8.3 SM: Remote Video Collaboration During COVID-19. Joey Cavaleri, Tolentino Pena, Bill Swales, Lester Kirschbaum - Intel

8.4 APC: A Feature Selection Approach For Virtual Metrology: Application To CMP Process. Agnès,Roussy, Taki Eddine Korabi, Valeria Borodin - École des Mines de Saint-Etienne Michel Juge - ST Microelectronics

8.5 APC: Combining Feature Extraction-Based and Full Trace Analysis Capabilities in Fault Detection: Methods and Comparative Analysis. Fei Li, Haoshu Cai, Jay Lee - University of Cincinnati James Moyne - University of Michigan Jimmy Iskandar, Michael Armacost - Applied Materials

8.6 DM: Journey to a Big Data Analysis Platform: Are We There Yet? Raymond Goss, Lesh Subramany - GLOBALFOUNDRIES

8.7 FE: Fabless Semiconductor Challenge – Internal Stakeholder Alignment Improvements Salvin Macwan, Josephine Quek, Scott Rogers, Marc de Zwart – NXP Semiconductors

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SESSION 9: CONTAMINATION FREE MANUFACTURING

Co-Chairs: Jennifer Braggin, Entegris; Chris Long, IBM Research; Chris Ebert, Linde

Contamination in the form of particulates, surface impurities and volatile organic compounds can have a significant impact on semiconductor wafer fab yield and reliability. This session will feature papers focused on tool and process improvement to reduce overall on-wafer contamination in order to eliminate killer defects, drive yield improvement and minimize yield excursions.

9.1 CMP Defect Reduction and Mitigation: Practices and Future Trends. Wei-Tsu Tseng, Carol Boye, Claire Silvestre, James Chen, Fee Li Lie, Donald Canaperi - IBM

9.2 Controlling Nanoparticle Contamination in Ultrapure Water Systems, Dan Rodier - Particle Measuring Systems Glen Slayter - Intel

9.3 Characterization of Dilution Effect of Mix Acids on Rough Silicon Etching Irregularities. Tatt Wai Wan, Weei Kai Cheng, Yin Ying Tan, Meera Brhma Dava - Infineon

9.4 FOUP Contamination and Limitation of Cleaning Procedure. Raymond Van Roijen, Matthew Fields, Bruce Dyer, Brian Messenger, Ralph Deangelis - GLOBALFOUNDRIES

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SESSION 10: INNOVATIVE SILICON DEVICES AND PROCESSES, ADVANCED PATTERNING / DESIGN FOR MANUFACTURABILITY, NON-SILICON AND NON-CMOS, ADVANCED SEMICONDUCTOR DEVELOPMENTS

Co-Chairs: Jeanne Bickford, IEEE; Shubho Goswami, GE

Papers in this session address advances and concerns across the semiconductor industry, encompassing advanced patterning, design for manufacturability, innovative silicon, non-silicon, and non-CMOS devices. Advanced Semiconductor Developments

10.1 AP/DFM: Snapback Design Rules for Automotive Vstress Reliability Tests. Mazar Hoque, Mark Griswold, Martin Clark - On Semiconductor

10.2 AP/DFM: Quick Yield Impact Assessment Using Silicon-design Correlation to Address Design Systematics. Chenlong Miao, Deborah Ryan, Haizhou Yin, Monisa Babu, Shenghua Song, Shobbit Makik, Sriram Madhavan, Michael Wojtowecz, Peter Lin, William Wilkinson, CT Lim, Panneerselvam Venkatachalam - GLOBALFOUNDRIES

10.3 ISD: Fabrication of High Aspect-Ratio Si Pillar-Based Hybrid Plasmonic-Photonic Crystal Waveguides for Ultra-Sensitive Infrared Gas-Sensing Applications. Gerald Stocker, Thomas Grille, Thomas Ostermann, Elmar Aschauer - Infineon Technologies Austria AG Reyhaneh Jannesari, Gerald Puhringer, Parviz Saeidi, Bernhard Jakoby - Johannes Kepler University Jassmin Spettel, Anderas Tortschanoff, Thang Duy Dao, Florian Dubois - Silicon Austria Labs GmbH

10.4 ISD: Bi-Layer Lift-off Resist Process Optimization of Insulator Film for Neural Probe Fabrication. Bob Wadja, Dan Nawrocki, Lori Rattray - Kayaku Advanced Materials

10.5 NS/NC: Influence of Resist Profile on Deep Reactive Ion Etch (DRIE) Sidewall Morphology. Shubhodeep Goswami, Robert Macdonald, Renner Ruffalo, Matthew Edmonds, Charles Szymanski - GE Research

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Virtual ASMC 2021 PDF Agenda

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