UNIVERSITY OF CALIFORNIA College of Engineering

Department of Electrical Engineering and Computer Sciences

Jan M. Rabaey Homework #9 EECS 141

Due Friday, May 8, 5pm, box in 240 Cory 1. The following circuit realizes a sequential logic circuit:

Figure 1 A sequential logic.

(1) Assume that all the transistors have been sized such that the delay from any input to the immediate output equals tinv=100ps, and an external clock CLK operates at 1GHz with 50% duty cycle. Draw the waveforms at nodes CLK, CLKD, X, and Q for two clock cycles, with D equals 0 in one cycle and 1 in the other. Would the sequential circuit above be considered a latch, a master-slave pair, or a pulse-triggered latch? (20pts)

(2) Are the setup and hold time of this sequential circuit positive, negative, or approximately zero? Why? (20 pts)

(3) Calculate the propagation delay tclk-q for output high-to-low and low-to-high transitions. (10 pts)

(4) Can we reduce the number of inverter stage between CLK and CLKD from three to one? Why or Why not? (10 pts)

(5) Now let’s try to determine the setup up time of this sequential circuit by simulation (see Lecture #23 slides 12-22 for examples). Complete the table below and find the setup time of the circuit, tsu(the larger of the two cases: low-to-high and high-to-low). (15 pts) Use transistor sizes: M1 = M2 = M3 = M7 = M8 = M9 = 0.36µm/0.1µm, M4 = M5 = M6 = M10 = 0.24µm/0.1µm, M11 = 0.12µm/0.1µm. The inverters have unit size and VDD = 1V.

Hold time Setup time tclk-q,L-H tclk-q,H-L 200ps 200ps 200ps 100ps 200ps 50ps 200ps 10ps 200ps 5ps 200ps 0ps

(6) Repeat (5) but find the hold time of the circuit, tH instead. (15 pts)

Setup time Hold time tclk-q,L-H tclk-q,H-L

200ps 200ps 200ps 40ps 200ps 32ps 200ps 31ps 200ps 30ps 200ps 29ps

Solution:

(1)

This is a pulse-triggered latch.

(2) The setup time is negative because the delay from the data input to the output is smaller than the pulse width. The hold time is positive because the D input must be held stable to settle at node X and node Q.

(3)

(4) No. The pulse width must be wide enough for the input data to propagate to the Q output, which takes 2tinv in the worst case.

(5) Hold time Setup time tclk-q,L-H tclk-q,H-L

200ps 200ps 45ps 11ps 200ps 100ps 45ps 11ps 200ps 50ps 45ps 11ps 200ps 10ps 47ps 11ps 200ps 5ps 49ps 11ps 200ps 0ps 55ps 11ps

(6)

Setup time Hold time tclk-q,L-H tclk-q,H-L 200ps 200ps 45ps 11ps 200ps 40ps 45ps 11ps 200ps 32ps 46ps 11ps 200ps 31ps 48ps 11ps 200ps 30ps 167ps 11ps 200ps 29ps 333ps 11ps

2. In this problem, you are asked to analyze the following datapath structure with feedback. Assume the registers are edge triggered with tclk-q, max = 4ns, tclk-q, min = 2ns, tsetup = 1ns, and thold = 1ns:

Figure 2 A data path structure with feedback.

(1) What is the maximum operating frequency of this system if there is no skew and jitter? (10 pts)

(2) What is the maximum random clock skew that this system can tolerate? (10 pts) (3) Assume there is no random skew and you are able to introduce the clock skew into this

system. How do you route the clock and add the skew to maximize the system performance without sacrificing the functionality? What is the maximum operating frequency we can achieve? When operating at the highest speed, what is the maximum random clock jitter that this system can tolerate? (15 pts)

Solution:

(1)

(2)

(3) The positive skew in the feedforward path becomes negative skew in the feedback path.

As a result, we can only introduce a positive skew with Tskew=2.5ns along the feedforward path to maximize the overall performance: