Thirteenth Annual Analyst Day Event -...

Ultratech Thirteenth Annual

Analyst Day Event

Ultratech Corporate Headquarters

San Jose, CA

November 15, 2016

Industry Outlook &

Highlights

Art Zafiropoulo

Chairman & Chief Executive Officer

November 15, 2016

Welcome to the

2016 Analyst Day Meeting

8:30 a.m. – 9:00 a.m. Registration San Jose Office Headquarters

9:00 a.m. – 9:20 a.m. Industry Outlook and Highlights Arthur W. Zafiropoulo

Chairman and Chief Executive Officer

9:20 a.m. – 9:45 a.m. Key Changes in Environment of

Semiconductor Industry and Impact of

China

Handel H. Jones, Ph.D.

Founder and Chairman

International Business Strategies, Inc.

9:45 a.m. – 10:10 a.m. Laser Annealing Positioned for Growth

Scott Zafiropoulo

General Manager, Laser Products

and Senior Vice President, Marketing

10:10 a.m. – 10:30 a.m. LM7 - Laser Melt Annealing for the

7nm Node and Beyond

Andy Hawryluk, Ph.D.

Senior Vice President and

Chief Technology Officer

10:30 a.m. – 10:55 a.m. The Growing Market for

Advanced Packaging

E. Jan Vardaman

President and Founder

TechSearch International, Inc.

10:55 a.m. – 11:20 a.m. Advanced Packaging

Lithography Market Update

Rezwan Lateef

General Manager and Vice President,

Lithography Products

11:20 a.m. – 11:45 a.m. Superfast, Enabling 3D Manufacturing Eric Bouche


Inspection Systems

11:45 a.m. – 12:05 p.m. Advanced Process Control

With Superfast

David M. Owen, Ph.D.

Vice President and Chief Technologist,

Surface Metrology

12:05 p.m. – 12:10 p.m. Closing Remarks Arthur W. Zafiropoulo


12:10 p.m. – 12:30 p.m. Q&A Session

Agenda

250

275

300

325

350

375

400

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

2Q16 Forecast 3Q16 Forecast

Billions of Dollars and Revenue Growth

Worldwide Semiconductor 3Q16 Revenue Forecast: 2016 Improves, as Does the Rest of the Forecast

2Q16 Forecast

$350.1

5.5%

$301.5

31.8%

$307.8

2.1% $299.9

-2.6%

$315.4

5.2%

$342.6

8.6% $334.8

-2.3% $331.8

-0.9%

$365.1

4.3%

$372.6

2.1%

$325

-3.0%

$340

4.7%

$359

5.7%

$369

2.6%

$384.3

3.2%

$378

2.6%

Semiconductor Revenue

Milestones

$50b 1989

$100b 1994

$200b 2000

$300b 2010

Source: Gartner 10/16

0

10

20

30

40

50

2012 2013 2014 2015 2016 2017 2018 2019 2020

Rev

enu

e

(Bill

ion

s o

f D

olla

rs)

32.0%

-13.1%

7.0%

-21.5%

9.3%

33.2% -12.7%

CAGR

15-20

-7.0%

-3.3%

-11.3%

Megabytes Bn 3,837 4,716 6,156 7,403 9,334 11,717 15,559 19,630 24,214 CAGR 15-

20

Bit Growth 31.9% 22.9% 30.5% 20.3% 26.1% 25.5% 32.8% 26.2% 23.4% 26.7%

ASP 4Gb eqv. 3.50 3.79 3.83 3.08 2.13 1.85 1.49 0.93 0.66 -26.6%

ASP Change -32.7% 8.4% 1.1% -19.6% -31.1% -12.9% -19.4% -37.8% -29.2%

3Q16 DRAM Market Metrics – The Cycles Continue 2017 & 2018 Boom, 2019 & 2020 Bust

2Q16 forecast -20.0% 3.9% 17.7% -17.7% -13.7%


0

10

20

30

40

50

2012 2013 2014 2015 2016 2017 2018 2019 2020

3Q16 NAND Market Metrics – Cycles Persist Due to Investments

23.1% 3.1% 3.5% 7.2%

7.4%

11.7% 0.5%

12.9%

-3.7%

Megabytes Bn 30,466 43,359 61,065 87,222 123,250 172,355 247,127 337,110 451,019 CAGR 15-

20

Bit Growth 62.1% 42.3% 40.8% 42.8% 41.3% 39.8% 43.4% 36.4% 33.8% 38.9%

ASP 4Gb eqv. 0.73 0.64 0.46 0.34 0.26 0.20 0.14 0.12 0.09

CAGR 15-

20

ASP Change -40.6% -13.5% -26.8% -27.6% -24.1% -20.1% -29.9% -17.2% -19.8% -22.3%

Rev

enu

e

(Bill

ion

s o

f D

olla

rs)

CAGR

15-20

7.9%

2Q16 forecast 2.1% 9.0% 3.0% 14.7% 8.3%


3Q16 Foundry Revenue Forecast

0

10

20

30

40

50

60

70

80

2014 2015 2016 2017 2018 2019 2020

2Q16

3Q16

Billions of Dollars and Revenue Growth

2Q16 Forecast

$48.9

4.4%

$52.0

6.3%

$55.9

7.5%

$58.3

4.3%

$60.3

3.5%

$65.1

7.9%

$46.8

16.0%

$50.8

4.0%

$53.7

5.7%

$57.5

7.1%

$60.8

5.4%

$64.9

7.0%


3Q16 Capital Spending by Device Type

Logic

• Investment targeted at 16/14nm FinFet

capacity and 10nm volume production in

2017

• Initial 7nm capacity in 2018-19; volume

production in late 2019 – 20

• Slowing Moore's Law and uncertain end

market demand restrains logic growth

Memory

• Market weakness causes flat 2016

• Transition to 3D NAND drives longer

term memory growth

• China fabs push growth in 2017-2019

• Accounts for ~40% of total capex, 2016-

2020 0

5

10

15

20

25

30

35

40

45

50

2014 2015 2016 2017 2018 2019 2020

Logic/Mixed Signal Memory Other

Billions of Dollars


AP200/300 Series Steppers

• Superior on-wafer results and strong

global support structure

• Customer-configurable design that

supports flexible manufacturing

requirements as well as tool

extendibility for multiple device

generations

• 90%+ stepper installed base market

share

• Purchased IBM enabling bump patents

• AP300 has exclusive and preferred

agreements with 60% of the Flip Chip

market

Why Ultratech Wins Advanced Packaging

• 245 laser process patents and

applications

• 71 melt annealing patents and

applications

• Proprietary design reduces

reflectivity variations from 20%

typically to <2%

• Lowest wafer breakage

• Lowest consumable cost

• Lowest cost per wafer

Laser Processing

LSA 101

Why Ultratech Wins

• A leader in 3D patterned-wafer

shape measurement

• Highest throughput, lowest cost

and smallest footprint

• Comprehensive wafer mapping

• Measures 3 million data points per

300mm wafer

• Throughput of 150 wafers per hour

Superfast 4G+

3D Inspection

Why Ultratech Wins

Nanotech 160

BEFORE

Sapphire 100

AFTER

• Sapphire lithography stepper

platform offers smallest footprint

with the highest economic value

for HBLED MEMS production

• ALD

• More than 400 systems

shipped

• Strategic global technology

partners

• Largest referenced technical

papers >1,100

Nanotechnology

Why Ultratech Wins

Nanotech 160

BEFORE

Sapphire 100

AFTER

• Sapphire platform offers the smallest footprint

with the highest economic value for HBLED

production

• Smallest footprint stepper

• Non-contact lithography – zero masking

defects

• Superior overlay and CD control on warped

substrates

• Fine resolution capability enables brightness

enhancement

Stepper Technology for High Yield HBLED

Processes

Low Cost Stepper Designed for HBLED Lithography

Ultratech CNT/ALD Overview

• The world leader in atomic layer

deposition for the research community

• Over 400 Savannah thermal ALD tools

in 6 continents

• Over 80 Fiji plasma enhanced ALD

tools in use today

• More papers published on research

with Cambridge NanoTech tools than

any other: in excess of 1,100 papers

• Dedicated process support from an

experienced team of ALD experts

Chemical

• Fuel cells

• Batteries

Nanostructures

• Nanotubes

• Around particles

• Graphene

Optical

• Optical filters

• Transparent conductors

• Electroluminescence

MEMs

• Etch resistance

• Hydrophobic /

antistiction

Decorative, Luxury & Textiles

• Jewelry

• Coins

Semi / Nanoelectronics

• Flexible electronics

• Gate dielectrics

• Metal Interconnects

• Read heads

Medical

• Implantable devices

• Biomaterials

Wear Resistant

• Solid lubricants

• Anti corrosion

The ALD Market Today

8:30 a.m. – 9:00 a.m. Registration San Jose Office Headquarters

9:00 a.m. – 9:20 a.m. Industry Outlook and Highlights Arthur W. Zafiropoulo


9:20 a.m. – 9:45 a.m. Key Changes in Environment of

Semiconductor Industry and Impact of

China

Handel H. Jones, Ph.D.

Founder and Chairman

International Business Strategies, Inc.

9:45 a.m. – 10:10 a.m. Laser Annealing Positioned for Growth

Scott Zafiropoulo

General Manager, Laser Products

and Senior Vice President, Marketing

10:10 a.m. – 10:30 a.m. LM7 - Laser Melt Annealing for the

7nm Node and Beyond

Andy Hawryluk, Ph.D.

Senior Vice President and

Chief Technology Officer

10:30 a.m. – 10:55 a.m. The Growing Market for

Advanced Packaging

E. Jan Vardaman

President and Founder

TechSearch International, Inc.

10:55 a.m. – 11:20 a.m. Advanced Packaging

Lithography Market Update

Rezwan Lateef



11:20 a.m. – 11:45 a.m. Superfast, Enabling 3D Manufacturing Eric Bouche


Inspection Systems

11:45 a.m. – 12:05 p.m. Advanced Process Control

With Superfast


Vice President and Chief Technologist,

Surface Metrology

12:05 p.m. – 12:10 p.m. Closing Remarks Arthur W. Zafiropoulo


12:10 p.m. – 12:30 p.m. Q&A Session

Agenda


Analyst Day Event


San Jose, CA

November 15, 2016

IBS

© 2016 INTERNATIONAL BUSINESS STRATEGIES, INC. ALL RIGHTS RESERVED. RR-PRS11.1516 SLIDE 20

KEY STRATEGIC ISSUES IN SEMICONDUCTOR INDUSTRY

Semiconductor market will grow 0.2% in 2016 and 4.6% in 2017

Growth is due to increase in gigabyte prices for DRAM and NAND Flash and

impact of increase in bill of materials of Chinese smartphone vendors

16/14nm FinFETs have achieved high volume

Also have superior performance and power consumption to 28nm, but with

gate cost penalties

TSMC is planning to be in high-volume production of 10nm in H1/2017 and

7nm in H1/2018

7nm will be high-revenue and long lifetime technology node

Adoption of EUV could be postponed, which will slow down ramp-up of Intel’s

7nm and TSMC’s 5nm

Samsung Electronics is promoting 7nm with EUV in H2/2018, but this target

will be difficult to achieve

IBS

© 2016 INTERNATIONAL BUSINESS STRATEGIES, INC. ALL RIGHTS RESERVED.

KEY STRATEGIC ISSUES IN SEMICONDUCTOR INDUSTRY (CONTINUED)

3D NAND market is in high growth mode and will have high CAPEX in 2016

and 2017

Samsung is in initial volume production with 48 layers

Intel, Micron Technology, SK Hynix, and Toshiba (Western Digital) are

adding wafer capacity

There is wide variation in endurance levels of 3D NAND, which requires use

of better inspection technologies

3D NAND should have 100X higher endurance than 14nm planar TLC NAND

Wafer fan-out technology is widely used, with TSMC’s InFO being

mainstream

Advanced Semiconductor Engineering (ASE) is providing wafer fan-out

technology, but most activities will be done by foundry vendors

Fan-out is area of high growth

SEMICONDUCTOR MARKET HAS GROWTH IN NEAR TERM AND GOOD

POTENTIAL IN LONGER TERM RR-PRS11.1516 SLIDE 21

IBS


SEMICONDUCTOR MARKET BY PRODUCT

POSITIVE GROWTH IN 2016 AND 2017

$0B

$200B

$400B

$600B

2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Sem

iconducto

r M

ark

et

MCU

DSP

Standard Cell ASIC

FPGA

Special-Purpose Logic

General-Purpose Logic

Display Driver

Analog

MOS Memory

MPU

Other Semiconductor

IBS


FOUNDRY MARKET BY FEATURE DIMENSION

7nm WILL BE LONG LIFETIME TECHNOLOGY NODE

$0B

$25B

$50B

$75B

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Foundry

Mark

et

≥0.25µm

0.18/0.15µm

0.13µm

90nm

65nm

45/40nm

28nm

22/20nm

16/14nm

7nm

10nm

≤5nm

IBS


WAFER VOLUME TRENDS

28nm 16/14nm 10/7nm

28nm WILL BE HIGHEST WAFER VOLUME FOLLOWED BY 10/7nm

1,196

2,015

2,622

2,244

2,585

2,730

2,908

3,071

3,226 3,339 3,390 3,425 3,446 3,453

0

1,000

2,000

3,000

4,000

2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

28nm

Wafe

r V

olu

me (

KU

)

0

364

651

1,034

1,3421,273

1,524

1,797

2,028

2,200

0

1,000

2,000

3,000

4,000

2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

10/7

nm

Wafe

r V

olu

me (

KU

)

0

646

1,124 1,119 1,171 1,2091,267 1,308 1,330 1,335 1,337 1,331

0

1,000

2,000

3,000

4,000

2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

16/1

4nm

Wafe

r V

olu

me (

KU

)

IBS


TSMC’S REVENUES BY FEATURE DIMENSION (FY)

STRONG DEMAND FOR IPHONE 7, AND HIGH GROWTH IN 2016

($M) Q1 % Q2 % Q3 % Q4 % TOTAL Q1 % Q2 % Q3 % TOTAL

20/16nm 1,078 16 1,247 20 1,355 21 1,483 24 5,163 1,493 23 1,627 23 2,574 31 5,694

28nm 2,022 30 1,684 27 1,742 27 1,544 25 6,991 1,947 30 1,981 28 1,993 24 5,920

45/40nm 1,011 15 873 14 903 14 865 14 3,652 909 14 1,061 15 1,080 13 3,049

65nm 809 12 686 11 710 11 680 11 2,884 649 10 849 12 913 11 2,411

90nm 472 7 437 7 516 8 432 7 1,857 389 6 354 5 415 5 1,158

0.13/0.11µm 135 2 187 3 129 2 185 3 636 130 2 141 2 249 3 520

0.18/0.15µm 876 13 811 13 774 12 680 11 3,140 714 11 778 11 747 9 2,239

≥0.25µm 337 5 312 5 323 5 309 5 1,280 260 4 283 4 332 4 875

TOTAL 6,740 100 6,236 100 6,450 100 6,178 100 25,603 6,489 100 7,073 100 8,304 100 21,867

2016

2015

(Dec 31, 2015)

IBS


NAND FLASH MARKET

HIGH GROWTH POTENTIAL THROUGH 2025

$29.0B$30.8B

$33.8B

$36.9B

$40.3B

$44.0B

$48.5B

$53.0B

$57.9B

$62.7B

$67.9B7.1

%

15.8

%

35.9

%

50.4

%

63.8

%

74.3

%

83.5

%

89.8

%

93.7

%

96.4

%

98.1

%

$0B

$25B

$50B

$75B

2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

2D

and 3

D N

AN

D F

lash M

ark

et

2D

3D

RR-PRS11.1516 SLIDE 26

IBS


NAND FLASH MARKET SHARE

$M % $M % $M % $M % Comments

Samsung 8,045 29.19 9,397 30.85 11,039 34.60 14,520 41.87 Access to large financial resources

Dominating 3D NAND market to date

Toshiba 6,191 22.46 6,621 21.74 6,478 20.30 6,413 18.49 Ramping 3D NAND volume

Will need access to large financial resources

Western 6,170 22.39 6,628 21.76 5,565 17.44 4,986 14.38 Ramping 3D NAND with 48 layers

Digital* Will need to match Toshiba's CAPEX

Micron** 3,844 13.95 4,713 15.47 5,240 16.42 4,872 14.05 Must prioritize funding between DRAM and NAND

Intel will have own 3D NAND capacity

SK Hynix 3,211 11.65 3,040 9.98 3,528 11.06 3,881 11.19 DRAM emphasis, and large CAPEX for DRAM

Initial production of 3D NAND

Subtotal 27,461 99.63 30,398 99.80 31,850 99.82 34,672 99.97 Five companies and Intel dominate market

There could be some consolidation in future

Other 101 0.37 61 0.20 56 0.18 10 0.03 Some activities in Taiwan, but lagging in technology

TOTAL 27,562 100.00 30,459 100.00 31,906 100.00 34,682 100.00

Note:

* Revenues include discrete NAND products and multichip modules.

** Shows revenues reported from December to November, including Intel's NAND but not Intel's SSD.

2016E2013 20152014


IBS


CAPEX OF SELECTED COMPANIES

CAPEX CONTINUES TO BE HIGH IN 2016

$B % $B % $B % $B % $B % $B % $B %

Samsung 11.34 28.47 11.24 21.62 13.01 26.51 11.93 25.29 13.10 24.59 12.52 25.09 10.10 19.20

TSMC 5.94 14.90 7.29 14.02 8.32 16.95 9.64 20.43 9.13 17.12 8.12 16.27 9.50 18.06

Intel 5.21 13.07 10.76 20.70 11.03 22.46 10.71 22.71 10.11 18.96 7.33 14.68 9.50 18.06

Micron¹ 0.95 2.39 3.05 5.87 1.66 3.39 1.59 3.37 3.14 5.89 3.60 7.21 5.55 10.55

• Inotera 1.89 4.75 0.38 0.74 0.15 0.30 0.22 0.46 0.70 1.31 1.69 3.39 -- --

SK Hynix 2.50 6.28 3.00 5.76 3.06 6.23 2.49 5.28 4.20 7.88 4.68 9.37 5.10 9.70

SMIC 0.73 1.83 0.77 1.47 0.50 1.02 0.77 1.63 1.01 1.90 1.40 2.81 2.50 4.75

Globalfoundries 2.75 6.90 5.40 10.39 3.80 7.74 4.50 9.54 5.00 9.38 2.50 5.01 2.25 4.28

UMC 2.10 5.28 1.76 3.39 1.80 3.66 1.10 2.34 1.37 2.57 1.85 3.70 2.20 4.18

Toshiba² 0.87 2.18 2.28 4.39 1.78 3.63 1.00 2.12 1.94 3.64 1.83 3.67 1.08 2.05

Western Digital⁴ 1.05 2.64 1.37 2.63 0.98 1.99 0.86 1.82 1.15 2.16 1.46 2.93 0.50 0.95

Infineon³ 0.44 1.11 1.18 2.27 1.14 2.32 0.51 1.08 0.84 1.58 0.88 1.76 0.95 1.80

Nanya 0.79 1.98 0.36 0.69 0.07 0.14 0.19 0.40 0.18 0.34 0.12 0.23 0.78 1.48

STMicroelectronics 1.03 2.60 1.26 2.42 0.48 0.97 0.53 1.13 0.50 0.93 0.47 0.94 0.64 1.21

TI 1.20 3.01 0.82 1.57 0.50 1.01 0.41 0.87 0.39 0.72 0.55 1.10 0.56 1.07

ROHM² 0.32 0.81 0.48 0.93 0.62 1.26 0.46 0.97 0.31 0.58 0.41 0.82 0.50 0.96

Renesas 0.72 1.80 0.59 1.14 0.20 0.42 0.27 0.57 0.23 0.43 0.51 1.02 0.90 1.70

TOTAL 39.83 100.00 51.99 100.00 49.10 100.00 47.17 100.00 53.29 100.00 49.91 100.00 52.61 100.00

• Growth rate (%) NA -- 30.54 -- (5.57) -- (3.92) -- 12.97 -- (6.36) -- 5.41 --

Notes:

¹ 2010 data represents FY ending in August. From 2011 forward, data represents FYs ending in November. From 2012 forward, data includes Elpida.

Micron is acquiring Intera.

² Data represents FYs ending in March.

³ Data represents FYs ending in September.

⁴ Western Digital acquired SanDisk on May 12, 2016. Estimated CAPEX for 2016 and beyond is for NAND only.

2016E20152013 20142010 2011 2012

IBS


KEY FACTORS IMPACTING SEMICONDUCTOR MARKET

Semiconductor market will be $582B in 2025 compared to $337B in

2015

Foundry market will be $73B in 2025 compared to $47B in 2015

Revenues and wafer volume of foundry vendors will continue to

increase through 2025

Advanced process technologies for logic products are concentrated in

Intel, TSMC, Samsung, and Globalfoundries

Memory supply chain is concentrated in Samsung, Micron, Intel,

Toshiba (Western Digital), and SK Hynix

Intel is also starting to participate in 3D NAND with 30nm technology

It is becoming increasingly difficult to achieve high parametric and

systemic yields as feature dimensions are reduced

Stress reduction and stress measurement technologies are

becoming increasingly important

IBS


KEY FACTORS IMPACTING SEMICONDUCTOR MARKET (CONTINUED)

Deep learning and artificial intelligence (AI) will have very high growth

and will create new industries in 2020 to 2025

TensorFlow from Google is key capability

IoT will have high growth after connectivity into cloud becomes efficient

Time frame is 2019 to 2020

Will require ultra-low power consumption at 16/14nm, 10nm, and 7nm

China is building large wafer processing ecosystem but needs support

in generating high yield

China is becoming large user of semiconductors and shifting from using

low-complexity products to high-complexity products

LSA AND SUPERFAST ARE WELL POSITIONED TO ADDRESS

MARKET GROWTH OPPORTUNITIES RR-PRS11.1516 SLIDE 30

IBS


KEY ISSUES OF ELECTRONICS INDUSTRY IN CHINA

Chinese companies will supply approximately 60% global smartphone volume in 2020

Features will be competitive with global leaders in smartphones

Huawei Technologies is global leader in 5G infrastructure

China could have 1B 5G users in 2025 to 2028

Big data will be large business in China

Deep learning and AI will gain momentum rapidly

Alibaba Group, Tencent, and Baidu are becoming world-class companies

Fastest two supercomputers in world as of June 2016 are from China and include:

1. Sunway TaihuLight: Uses Sunway SW26010 processor at 1.45GHz

2. Tianhe-2 (MilkyWay-2): Uses Intel Xeon E5-2692v2 at 2.2GHz

Indicates increased competitiveness of China in high-performance systems

VR devices have high growth potential, but AR will be much bigger

Drones are growth market, and China is leader

Electric bikes are electric cars with autonomous driving will be large markets in China

EVOLVING TO BECOME HIGH TECHNOLOGY, AND SEMICONDUCTOR INDUSTRY WILL

NEED TO TRACK GROWTH RR-PRS11.1516 SLIDE 31

IBS


158

355

500

697

806

0

300

600

900

2012 2013 2014 2015 H1/2016

Active

User

Accounts

(M

U)

ACTIVITIES IN CHINA

WECHAT VOLUME SMARTPHONE VOLUME

UPSIDE POTENTIAL IS EXCELLENT

BROADBAND WIRELESS CONNECTIVITY 5G SMARTPHONES

148

346

693 769

863 894 923 954 991 1,033 1,081 1,128 1,176 1,224

581

624

669

746 721 714 710

716 728

744 771

797 823

847

729

970

1,362

1,515 1,584 1,608 1,633

1,670 1,719

1,777 1,852

1,925 1,999

2,071

0

800

1,600

2,400

2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Num

ber

of

Sm

art

phones (

MU

)

Other Supply

China Supply

100Mbps

10Mbps

1Mbps

0.1Mbps

0.01Mbps

0.001Mbps

Pe

ak B

an

dw

idth

1995

Year Available for Wide Range of Users

2000 2005 2010 20151990

1Gbps

2020

HIGH-DEFINITION VIDEO

STANDARD DEFINITION VIDEO

AUDIO AND MUSIC

DATA

VOICE

MULTIPLE STREAMS OF ULTRA-HIGH-DEFINITION VIDEO

We Are Here

2025

10Gbps

5G Era

MULTIPLE DATA FORMATS

1564

122

195

263312

366

10

32

57

126

174

224

262

25

96

179

321

437

536

628

0

250

500

750

2019 2020 2021 2022 2023 2024 2025

Num

ber

of

5G

Sm

art

phones (

MU

)

Other

China


IBS


WAFER FAB ACTIVITIES IN CHINA

Expenditures ($B)

Total 2016 Location Product Technology Comments

Yangtze

Memory

Technology

24.0 0.5 Wuhan 3D NAND 30nm Initial output of 100K WPM in H2/2018 or H2/2019

Plan to have 300K WPM in 2020 and 1M WPM (could be in multiple locations) by 2030

Could also establish DRAM capacity in Hefei

Tsinghua Unigroup has become lead investor

Will need strategic partners

SMIC 15.0 2.5 Beijing,

Shanghai

Logic 40nm, 28nm Acquiring LFoundry to get extra 200mm capacity

Also upgrading Shenzhen 200mm facility, and key product is image sensor

Main emphasis on Beijing and Shanghai 300mm facilities

Will continue to get strong demand from Chinese fabless companies and foreign

companies that want Chinese supply chain

UMC and

partners

6.2 0.1 Xiamen Logic 55nm,

40nm, 28nm

United Semiconductor joint venture with Xiamen municipal government and Fujian

Electronics & Information Group. UMC will invest total of $1.35B in Chinese facility and

provide process and management expertise

Capacity of 50K WPM, and output in H2/2018

Emphasis will likely be on 28nm

5.3 0.1 Fujian DRAM 32nm Capacity of 60K WPM, and output in H2/2018

UMC does not have expertise in DRAM and is hiring DRAM experts

Total investment in Fujian province is $11.5B

Samsung 7.5 0.4 Xi'an 3D NAND 30nm Wafer capacity at end of 2015 was 100K WPM. Has production volume in 32 and 48

layers. Developing 64 layers

Likely to increase wafer output from Xi’an in 2017 and emphasize 64-layer 3D NAND

Has also spent $1B on packaging and testing in Xi'an

Emphasis in 2016 is on upgrading 2D NAND wafer fab facilities in South Korea to 3D

NAND

IBS


WAFER FAB ACTIVITIES IN CHINA (CONTINUED)

Expenditures ($B)

Total 2016 Location Product Technology Comments

Intel 5.5 0.5 Dalian 3D NAND 30nm Initial CAPEX is $1.5B, and output in H2/2016

Could change from floating gate to charge trap

Could also manufacture 3D XPoint in China

High probability that China will become one of key wafer fab locations in longer term

Large packaging and testing facility in Chengdu

SK Hynix 5.5 0.1 Wuxi DRAM 20nm Emphasis in Wuxi is on DRAM to date

Could support foundry market from Wuxi in future

TSMC 3.0 0.5 Nanjing Logic 16nm Capacity of 20K WPM, and output in H2/2018

Large amount of land allows for wafer capacity expansion in future

Will build design enablement team of 500 and support wide range of technologies from

Nanjing location

Globalfoundries

and partners

2.0 to 3.0 0.01 Chongqing Logic 130/180nm

to 40nm

Initial capacity of 15K WPM in 2017

Targeting power management, battery management, audio amplifiers, MCUs, etc

Extension of capabilities in Singapore

Can allow Globalfoundries to establish strong presence in China

Powerchip and

partners

2.0 to 3.0 1.0 Hefei LCD

driver IC

90nm,

110nm,

150nm

Joint venture with Hefei Construction Investment and Holding, which is providing initial

investment of 13.53B CNY ($2.0B). Powerchip will put some capital in 2016, but

financial position of company is weak

Initial capacity of 40K WPM in 2017

Could also manufacture DRAM in future

HLMC 5.7 0.0 Shanghai Logic 28nm, 14nm Line 2 for HLMC

Needs partner for process technology

Advantageous to get key customer

IBS


$128B $130B $129B$139B

$159B$164B $169B

$182B

$196B

$212B

$230B

$248B

$268B

$289B

$313B

$338B

$0B

$90B

$180B

$270B

$360B

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Sem

iconducto

r C

onsum

ption i

n C

hin

a

Chinese ElectronicsEquipment Companies

Foreign Electronics Equipment Companies

SEMICONDUCTOR CONSUMPTION PATTERN IN CHINA

CHINESE COMPANIES CONSUMED 15.8% OF TOTAL SEMICONDUCTORS IN

CHINA IN 2010 BUT WILL BE 53.8% IN 2025 RR-PRS11.1516 SLIDE 35

IBS


CONCLUSION

Semiconductor and foundry markets are in relatively positive positions

in Q4/2016, with growth potential for 2017

Wafer capacity for 10nm and 7nm is being established, with high-

volume production in 2017 and 2018, respectively

There are some risks associated with adoption of EUV, which can slow

migration to TSMC’s 5nm (Intel’s 7nm)

Volume of NAND Flash consumption will have CAGR of 26.1% from

2015 through 2025

73.3% of product supply will be based on 3D NAND technology in 2020

There are concerns with wide range in endurance of 3D NAND due to

difficulties with inspection inside holes

IBS


CONCLUSION (CONTINUED)

Specialty packaging will become increasingly important

Samsung’s PM971-NVMe SSD has 16 48-layer 3D NAND, LPDDR4,

and controller with 512GB capacity in BGA form factor

DRAM market has positive growth, with key trend toward multichip

modules

HBM2 is used for high-performance applications

LSA is best technology for annealing, which can reduce leakage

Melt LSA will be increasingly adopted at 7nm

Overlay problems will have major impact on yield at 7nm (90 mask

steps)

Superfast is best candidate to address overlay problems

POSITIVE REGARDING LONGER-TERM AND NEAR-TERM GROWTH

OF SEMICONDUCTOR MARKET AND NEED FOR BETTER

TECHNOLOGIES


Analyst Day Event


San Jose, CA

November 15, 2016

Scott Zafiropoulo

General Manager, Laser Products &

Senior Vice President, Marketing

Laser Annealing Positioned

for Growth

Agenda

• LSA Performance in 2016

• Millisecond Anneal Market Drivers

• LSA Market Position

• New Melt Technology

• Summary

LSA Highlights in 2016

• Market leader with over 85 LSA systems shipped

• Strong 28nm capacity addition in multiple regions

• New devices adopting 14nm in 2H16

• Initial 10nm production underway

• Multiple customers using LSA for 7nm development

• Annual wafer volume forecast to exceed 4.5M passes

• LSA business positioned to grow ~3X over last year

LSA Production Volume Increasing

• Annual wafer volume on LSA

experienced strong growth in

2016

• Increased FinFET production at

14nm and second wave of

foundries expanding 40/28nm

capacity

• Expect wafer volume to

continue to increase in 2017

Source: Company Estimates, Nov 2016

0

1

2

3

4

5

6

2012 2013 2014 2015 2016

LSA Wafer Passes

Millions of wafers

Estimated passes in Q416

LSA Extendible for Multiple Technology Generations

• LSA used for FEOL and MOL

applications and is extendible

to multiple technology nodes

• Key productivity and

performance upgrades extend

the life of the LSA101 platform

for advanced nodes

• Below 10nm integration of

nanosecond melt process

expected

Technology Node

LSA Systems in Production*

45/40nm 35

32/28nm (Poly SiON)

42

32/28nm (HKMG)

42

22/20nm 4

16/14nm 28

10nm 7

*Exceeds shipment number due to allocation to multiple nodes concurrently

Agenda





• Summary

• Mobile phone shipments

exceeded 1.4B units in 2015

and are expected to reach

2 billion units in 2020

• PC and tablets volume

remain flat but will continue to

utilize high end devices

• Consumer devices driving

demand for both FinFET and

planer logic

Source: Gartner, Oct 2016

Consumer Driving Logic Market

0

500

1,000

1,500

2,000

2,500

3,000

2015 2016 2017 2018 2019 2020

Mobile Phones PC Tablet

Units in Thousands

Consumer Device Forecast

Leading Edge FinFET Growth

• Foundries continue to show

commitment to investing in

advanced nodes

• In 2017 expect continued ramp

of 16nm/14nm, introduction of

10nm production and significant

development for 7nm

• Capex spending among the top

Foundries expected to remain

strong in 2017

0

500

1,000

1,500

2,000

2,500

3,000

2016 2017 2018 2019 2020

16 / 14nm 10nm 7nm 5nm

300mm wafers (MSI)

Advanced Logic Device Forecast


$0

$1

$2

$3

$4

$5

Who Can Afford the Most Advanced Devices

• The cost of developing new

generations of process

technology is increasing rapidly

• The 28nm node still offers the

lowest cost per transistor and

designs can be transitioned

relatively easily from 40nm

• Foundries must choose strategy

to best navigate technology

node choices

Source: IBS, May 2016

Cost per Gate Trends

$ per 100M gates

Lowest cost per transistor

Continued Strength in 28nm Node

• The wafer volume for 28nm

planer devices is expected to

remain high through 2025

• Drivers include chipsets for

smartphones / tablets,

automotive, RF, nonvolatile

memory and other consumer

driven applications

• The Internet of Things (IoT) is

expected to represent $75B in

semiconductor value by 2025 0

500

1,000

1,500

2,000

2,500

3,000

3,500

2015 2016 2017 2018 2019 2020

28nm Wafer Production

Source: IBS, Aug 2016

300mm wafers (KU)


China Increasing Planer Capacity

• Government stimulus packages

will result in an increase of

Capex spending by $1.5 billion

a year by Chinese foundries

from 2018 through 2020

• Capacity addition expected at

SMIC, SMNC, USC and HLMC

• Companies strengthening

infrastructure across China to

support growth

2016 2020

300mm Capacity (WPM)

32% CAGR

415K

1270K

LSA is the tool of record at ALL major foundries for 28nm production

Millisecond Applications from Planar to FinFET • Junction Anneal

• Used for S/D and S/D-ext for dopant activation

to improve performance and reduce leakage

• SMT

• Strain engineering improves channel mobility

and device performance in advanced planer

applications

• HKMG

• Being investigated at 7nm node to improve

EOT scaling, reliability and leakage

• Silicide

• Used for silicide formation at

S/D contact for leakage reduction

• MOL

• Post silicide step for contact resistance

improvement and reactivation widely adopted

for FinFETs

Planer

FinFET

Agenda





• Summary

LSA Delivers Technology Leadership

• Long wavelength CO2 laser,

p-polarized and incident on wafer

at Brewster’s angle

• Minimizes pattern loading effect for

best in class within-die uniformity

• Pattern effects can cause degraded

electrical performance and yield loss

• Thermal emission temperature

feedback control die-to-die

repeatability

• Localized stress field, flexible

dwell time low stress

scan

q

10.6um

Lowest Thermal Budget Solution

High thermal budget can lead

to process issues

• Gate stack impact

• The extra thermal budget can allow

oxygen to diffuse from inside the

transistor to the high k film, which

slows the transistor

• Dopant de-activation

• Dopants can de-activate during the

long ramp down of Flash, also

resulting in a slower transistor

• LSA provides lowest millisecond

thermal anneal budget for optimal

MSA performance

T

~ 10 sec

Ti ~ 700-1000C

Tp ~ 1100-1250C Blue: LSA

Red: Flash

Slow ramp

up

Slow ramp

down

Millisecond Anneal Tool Landscape

LSA offers best technical performance and lowest cost per wafer with extendibility to future nodes

LSA101/201

TurboFLASH A FLASH B Laser Diode

Initial Tool Price ~ $5.5M ~ $4.0M ~ $5.0M ~ $4.0M

Consumable Cost $40K $150K $1,200K $350K

Pattern Effects 5-10oC (1s) 100-150

oC (1s) 100-150

oC (1s) 100-200

oC (1s)

Wafer StressLow stress,

low breakage

High stress,

high breakage

High stress,

high breakage

Silicide - low

stress process

Throughput 45wph 40wph 55wph 44wph

Wafer Cost

(US$)$3.22 $3.62 $7.63 $4.10

Agenda





• Summary

Thermal Annealing Evolution Reduced Diffusion

Batch

Furnace

Nsec

laser

MSA: laser

or flash

Single Wafer

RTP Spike

Incre

as

ed

Acti

va

tio

n

800

900

1000

1100

1200

1300

1400

Hours Minutes Seconds Milli

Seconds

Micro

Seconds

Nano

Seconds

An

ne

al

Pe

ak

Te

mp

era

ture

(o

C)

80%

85%

90%

95%

100%

Re

lati

ve

Ac

tiv

ati

on

(%

)

Junction Profile Comparison

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

1.E+22

0 20 40 60 80

Depth (nm)

Bo

ron

Co

nc. (c

m-3

)

Melt LTP

Nonmelt LSA

Spike RTA

Super-activation

Nsec Melt MSA RTA

Melt annealing results in ultra-shallow, abrupt junction, with above solid solubility activation better Rs-Xj than MSA

Melt Annealing Opportunities

Target Process Nanosecond Spike

Temperature oC

FEOL 1100-1400

High K +

MOL Silicide 1200-1350

Contact Anneal 800-1100

BEOL 800-1100

New Materials 600-900

• Advanced logic manufacturers

investigating melt annealing for

various applications at 7nm and

below

• Adopting a melt annealing

process should enable

increased performance and

improved battery life

• Pattern effects is a major

concern in inserting nsec

annealing due to the extremely

short thermal diffusion length

Junction Process Window: LM7 Melt vs Conventional Melt

cSi

aSi

• LM7 uses MSA as preheat

which minimizes thermal

pattern effects associated with

nsec anneal

• The process window should be

larger with the LM7 design

• Engaged with customer looking

at LM7 for 7nm production

• Signed JDA with strategic

partner for LM7 evaluation

targeted at 5nm development

for multiple applications

0

5

10

15

20

25

0.6 0.8 1 1.2 1.4

Normalized Fluence

Melt D

epth

(nm

)

Conventional Melt

LM7

Initial results in Ultratech Advanced LM7 Research has achieved a world record in the reduction of contact resistance

Agenda





• Summary

Laser Annealing Market Summary

• LSA has maintained the market and technology leadership

position for advanced annealing

• LSA provides lowest thermal budget for millisecond annealing

• LM7 melt reduces the temperature jump from the nsec laser

expanding the melt process window

• Engaged with key strategic partners to integrate LM7 melt into

production starting at 7nm


Analyst Day Event


San Jose, CA

November 15, 2016

Andrew M. Hawryluk, Ph.D.

Senior Vice President and CTO

LM7 Laser Melt Annealing For

The 7nm Node and Beyond

Agenda

• Differences between LSA and LM7

• Why Melt?

• Our Competitive Advantage

• Changes in Requirements

• Summary


• Why Melt?



• Summary

Agenda

LSA vs. Melt Technologies

nsec scan

beam

msec preheat

beam

400

600

800

1000

1200

1400

1600

-2 0 2 4 6 8

Time (ms)

Te

mp

era

ture

(oC

)

nsec (melt)

msec preheat

msec laser

beam LSA LM7

msec (<Si melt)

400

600

800

1000

1200

1400

1600

-2 0 2 4 6 8

Time (ms)

Te

mp

era

ture

(oC

)

msec anneal

Overview of Flying Spot Melt (LM7)

• Pre-heat is accomplished by a red laser

• Pre-heat by red-beam is adjustable

• The pre-heat beam scans across the wafer

• “Flying Spot” uses sub-micron

wavelength laser

• Focused to an elliptical spot at wafer

• Spot is scanned across red laser beam

• Can very melt exposure time

• Dwell time of scanned beam is adjustable

• Provides process flexibility

• Maintains Unity platform

Red

beam

Scanning

Laser beam

Wafer

movement

LM7 Architecture Builds on the Standard Unity Platform

Red Laser

Wafer

“Flying Spot”

nsec Laser

Standard chuck

Red

beam

Scanning

Laser beam

Wafer

movement

The “Flying Spot” is moving at roughly ½ km/sec

Hardware Implementation: Step and Scan “Flying Spot” LM7

“Step and Scan” Flying Spot

Rotating Mirror

Red laser beam

Submicron Laser

“Flying Spot” Beam

“Step and Scan” Flying Spot

Hardware Implementation: Step and Scan “Flying Spot” LM7

Advantages:

1) Less temperature variations

from beam profile

2) More stable laser intensity

3) Fewer pattern effects

4) Real-time temperature

corrections are possible

LM7 offers better uniformity and repeatability.

LM7 offers greater process flexibility.

Agenda


• Why Melt?



• Summary

Advantages of Melt Annealing

• Melt annealing can reduce device leakage and

extend battery life

• Both of these are desirable in mobile devices

Preferred Annealing Processes

Process Comparison

Sub-melt Melt

Device Node 407 nm 7 nm ?

Peak Temperature < 1300oC > 1412oC (for Si)

Anneal Time 0.1 ~ 10 msec 10 nsec ~ 1 msec

Heated depth ~ 100 mm ~ 1 mm

Molten Layer

Thickness none 1 ~ 100 nm

Activation mid 1e20 cm-3 > 1e21 cm-3

Dopant Diffusion Near diffusionless

Uniform dopant distribution

in molten Si; near atomic

abrupt

Melt Annealing Improves the Junction Profile Key to Device Performance

Junction Profiles

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

1.E+22

0 20 40 60 80

Depth (nm)

Bo

ron

Co

nc

. (c

m-3

)

Melt LTP

Nonmelt LSA

Spike RTA

Super-activation

nsec Melt MSA RTA

nsec melt results in super-activated, shallow,

abrupt junction lower resistance, high device performance

Agenda


• Why Melt?



• Summary

Issues with Melt Annealing

Temperature uniformity must be maintained to

achieve device performance uniformity

• Pattern effects lead to temperature non-uniformities

variations in device performance and reduction in

yield

• Two types of pattern effects:

• Optical induced non-uniformities

• Material induced non-uniformities

Optical Pattern Effects are Larger with Conventional Melt Approaches

Tpeak

Tchuck

Conventional melt approaches spike

the wafer from the chuck temperature

to the material melt temperature.

DT ~ 1000oC

Temperature variation ~ 300oC

nsec

laser

heating

Optical pattern effects produce temperature variations that are

roughly 1/3 the “spike” temperature

Optical Pattern Effects are Smaller with the LM7 Approach

1200

1300

1400

1500

0 200 400

Time (ns)

Tem

pera

ture

(K

)

Tpk

400

600

800

1000

1200

1400

1600

-2 0 2 4 6 8

Time (ms)

Te

mp

era

ture

(oC

)

Tpeak

Tchuck

nsec

laser

heating

Preheat laser

(uniform temperature)

The nsec temperature spike is much smaller, resulting

to less device temperature variations more uniform

devices and higher yields

Material Differences also Induce Temperature Variations

The Flying Spot melt laser provides only small amount of

“spike” heating and minimizes the non-uniformity due to

the pattern effects

1400

1600

1800

2000

2200

No LSA Preheating With LSA Preheating

Max S

urf

ace T

em

pera

ture

(K

)

Gate on silicon

Gate on field oxide

Gate

OxideSi-substrate

Gate Gate

OxideSi-substrate

Gate

T1 T2

Conventional Melt LM7

Agenda


• Why Melt?



• Summary

• New applications require lower chuck substrate

temperatures (down to room temperature)

• Back-end applications require a different wavelength

for the flying spot resulting in a change in optics and

system configuration

Changes in Requirements

• Removed CO2 laser and replaced with a red diode laser

(for room temperature absorption)

• Replace original flying spot with a submicron flying spot

(for back end applications)

• Targeted throughput (application specific): 50-100 wph

Modifications To Meet Customer Requirements

Agenda


• Why Melt?



• Summary

Summary

• Most advanced melt tool available

• High throughput

• Lowest cost of ownership

• Developed using more than two decades of experience

• Over 250 patents and applications in the laser melt

technology


Analyst Day Event


San Jose, CA

November 15, 2016

© 2016 TechSearch International, Inc. w w w . t e c h s e a r c h i n c. c o m

The Growing Market for Advanced Packaging:

E. Jan Vardaman, President and Founder

© 2016 TechSearch International, Inc. www.techsearchinc .com

Advanced Packaging Changes Assembly Models

• Traditional assembly model:

– Wafer is processed in fab

– Wafer sent to assembly facility for singulation, assembly, and test

– Typically most was wire bonded

• Today’s model:

– Increasing use of FC, fan-in WLP, fan-out WLP

– Some wafers stay at the foundry for packaging and assembly

– Many OSATs install wafer processing equipment to create package on the wafer


Demand for Thin Smartphones Drives Advanced Packaging Developments

• Smartphones volumes remain largest volume application in units

• Smartphones drive thinner packages

– WLP

– FO-WLP

– FC-CSP

Cu Pillar Bump


Advanced Packaging Share of iPhone’s Total Die Area

• Increasing use of advanced packaging (FC and WLP)

• In iPhone 7, approximately 49% is assembled and packaged using WLP and flip chip packaging technologies

• The remaining 51% uses wire bond-type packages


WLP Key Package for Thin Smartphones

• WLP meets system packaging needs

– Small form factor

– Need for low profile packages

– Lower cost (less material)

• Form Factor is key

– Low profile

– Limited space on PCB

– Thinner packages provide more room for battery

• Both Fan-in and Fan-out WLP

Source: iFixIT.


FO-WLP Shows Big Growth

• Device types include RF including transceiver, switch, NFC, GPS, PMIC, CODEC, automotive radar, connectivity modules, future application processors from TSMC and others

• Many multi-die products in future

• Projecting a CAGR of 80% in unit shipments from 2015 to 2020

2015 2016 2017 2018 2019 2020

Source: TechSearch International, Inc.


The TSMC’s InFO Has Arrived….

• Apple’s iPhone 7 is shipping with TSMC’s InFO

• Bottom package for the application processor in the package-on-package (PoP)

• Top package contains memory


Why FO-WLP?

• Smaller form factor, lower profile package

• Thinner than flip chip package (no substrate)

– Can enable a low-profile PoP solution as large as 15mm x 15mm body or greater

• Support increased I/O density

– Fine L/S (10/10µm) in production today

– Roadmaps for <5/5µm L/S, future 2/2µm L/S

• Allows use of WLP with advanced semiconductor technology nodes with die shrinks

• Split die package or multi-die package/SiP

– Multiple die in package possible

– Die fabricated from different technology nodes can be assembled in a single package

– Can integrate passives

• Excellent electrical and thermal performance (board level)

– TSMC has demonstrated with InFO for Apple’s A10 processor

– Die-first, face-up process with small Cu bump

Source: TSMC.

InFO is 20% thinner than FC-PoP


Amkor’s SWIFT™ High Yield FO-WLP with Chip Last

• Target Markets

– Mobile, Networking

– BB, AP, Logic + Memory, Deconstructed SoC

• Utilizes Existing Bump and Assembly

Capability

– Polymer based

– Flexible

• Multi-die and large die capability

• Large package body capability

– Advanced die integration

• Stepper capability down to 2um line/space

• Die shift / orthogonal rotation elimination

• Down to 30um in-line copper pillar pitch

– 3D capability

• Package stack capability

using Cu pillars or TMV

SWIFTTM Single Die Overmold

SWIFTTM 2 Die Overmold

SWIFTTM 2 Die Exposed

SWIFTTM 2 Die TMV PoP Overmold

SWIFTTM 2 Die Fan-in PoP


eWLB Process: Developed by Infineon


FO-WLPs in Many Smartphones with eWLB Process

• Qualcomm Audio CODEC (below)

– Package is 4.25 mm x 3.90 mm

• Qualcomm RF transceiver (right)


• Qualcomm PMIC


Source: ChipWorks.


Growing Number of FO-WLP Applications

• Baseband processors (in production many years)

• Application processor

• RF transceivers, switch, etc.

• Power management integrated circuits (PMIC)

• Connectivity modules

• Radar module (77GHz) for automotive

• Audio CODEC

• Microcontrollers

• Memory (future)

• Many multi-die configurations

NXP Radar Module

Source: NXP.

Marvell PMIC & Audio CODEC

Source: Nanium.


Migration to FO-WLP

FO-WLP

FC-CSP

Fan-in WLP


Why is FO-WLP A Disruptive Technology?

• No substrate

– Thin-film metallization used for substrate (can go below 5µm L/S)

– No traditional laminate substrate (most application processors had been using laminate substrate with flip chip bump interconnect)

– No traditional underfill

– Removes substrate supplier as design partner

• Infrastructure changes

– All packaging can take place at the foundry

– Assembly can also take place at OSAT but uses a non-traditional OSAT assembly line

– Requires IC/package co-design

Source: Nanium.


What’s the Impact of Growth in FO-WLP?

•Flip chip bumping

•Laminate substrates

Cu Pillar Bump


Flip Chip Bumping: Small Impact

• High Density FO-WLP typically uses flip chip bump in form of a Cu pillar or post

– TSMC’s InFO used for FO-WLP still has a small Cu post

– Deca process still has a small Cu post

• eWLB process does not use a bump

• Many PMIC, RF, and CODEC

• Migrating from fan-in WLP where there was no bump

Source: Deca.


Laminate Flip Chip CSP Substrates: Big Impact

• Substrate is the highest cost segment of the FC-CSP

• FO-WLP removes the substrate

• TSMC’s InFO represents the loss of the laminate substrate business

• FO-WLP such as eWLB process do not use a laminate substrate

– Some PMICs, RF IC, and audio CODECs were already in WLP

• Substrate suppliers developing coreless or thin-core substrates to compete with FO-WLP

– Lower margin than traditional high density build-up substrates results in lower revenue for substrate makers

– Use of substrate still requires a bumped die


Copper Pillar Demand Continues Expansion

• Industry continues move to Cu pillar

– Cu pillar for many PoPs for application processor in bottom package, even TSMC’s InFO has Cu small Cu pillar

– High volume for many wireless products

– Many designs moving to Cu pillar at 28nm and beyond

– 130µm bump pitch may be limit for solder bump

2014 2015 2016 2017 2018 2019Source: TechSearch International, Inc. Chipworks, Micron, SKHynix


Flip Chip: Growth in Cu Pillar

• Flip chip growth strong

– Many high-end, high performance packages

– Low-end packages for diodes, filters

• Trends toward copper pillar

• QFNs with flip chip interconnect

• Micro bumps for 3D IC w/ TSV

– DRAM

• Future flip chip growth in mobile devices

– Driven by form factor and performance

– Baseband processors in flip chip

– Application processors in flip chip

– Many small die in SiP modules

• Wire bond remains less expensive, but limited by performance and form factor

• FC-CSP impacted by growth in WLP and FO-WLP

Source: TPSS.

Source: SKHynix


AMD’s “Fiji” with Silicon Interposer and HBM

• AMD’s “Fiji” solution for the graphics market

• Features a logic device (ASIC) mounted in the center of a silicon interposer

• There are approximately 200,000 interconnects in the module including Cu pillar microbumps and C4 bumps

• The interposer has 65,000 TSVs with 10µm-diameter vias

Source: AMD.


Conclusions

• Advanced packaging continues to grow

– High-performance markets for 3D memory with TSV and silicon interposers

– Mobile products increasingly using wafer level packaging including fan-in WLP and FO-WLP

• Increased use of fan-in WLP and FO-WLP

• FO-WLP is a disruptive technology

– Introduction with have impact similar to Intel’s introduction of Cu pillar bump

– Many versions use Cu pillar

– Negative impact on the organic substrate business

• Dynamic nature of our industry means continued change

TechSearch International, Inc. 4801 Spicewood Springs Road, Suite 150

Austin, Texas 78759 USA +1.512.372.8887

[email protected]

www.techsearchinc .com © 2016 TechSearch International, Inc.

Thank you!


Analyst Day Event


San Jose, CA

November 15, 2016

Rezwan Lateef

General Manager & Vice President


Advanced Packaging Lithography

Market Update

Agenda

• Market Update

• Roadmap

• Summary

Advanced Packaging Drivers

Source: Cisco VNI Global Mobile Traffic Forecast 2015-2020

Advanced Packaging growth driven by continued mobile

phone functionality requirements:

− Greater Miniaturization

− Better Performance

− More Heterogeneous Integration

− Lower Cost

Advanced Packaging Superior Growth

Wire Bond: 82%

of total

WLP Trends in iPhones

Source: TechSearch International, Inc. 2016

iPhone

2007

2 WLPs

iPhone 3GS

2009

4 WLPs

iPhone 4s

2011

7 WLPs

iPhone 5

2012

15 WLPs

iPhone 5s

2013

22 WLPs

iPhone 6

2014

29 WLPs

iPhone 6s

2015

25 WLPs

iPhone 7

2016

44 WLPs

iPhone 5, 5s, 6, and 6s includes WLPs in Lightning Charge & Sync cable

iPhone 7 includes WLPs in Lightning cable and Lightning-to-3.5mm adapter

0

5

10

15

20

25

30

35

40

45

WL

Ps

pe

r P

ho

ne

iPhone Model/Year

iPhone 7 InFO & Cu Pillar

Apple

Application Processor

TSMC InFO-PoP

Cu Pillar in bottom package

A10 die

DRAM die

(x4)

Baseband Processor

Copper Pillar at 100µm pitch

Source: TechSearch International, Inc. & TPSS

Images from iFixit and eWiseTech

Cu Pillar Expansion

• Cu pillar is the dominant flip chip technology with typical pitches of 60µm to 100µm

• 28% 5-Year CAGR for 300mm Cu pillar from 2015 to 2020

• Main Benefits:

• Finer pitch capable down to

60μm in-line and 40μm /

80μm staggered

• Higher current capability

(3x higher than solder)

• Reduced signal impedance

• Better thermal conductivity

• Lower chemistry cost

Source: TechSearch International, Inc. 2016

AP300 Cu Micro Bump Extendibility (current production 60-100µm)

12.5µm 6.5µm 4.2µm 3.5µm

Decreasing Micro Bump Diameter

Pre-reflow results exhibit excellent critical dimension control

Definition:

Reconstituted wafer and perimeter mold compound allows for redistribution of I/O beyond current chip footprint

Benefits:

• Smaller form factor, lower profile package: similar to conventional WLP in profile

• Increased I/O density

• Excellent electrical and thermal performance

• Multiple die in a low-profile package

• Multi layer RDL with FO-WLP

Fan-out WLP Expansion

Source: (TR) TechSearch International, Inc. 2016

Fan-in Fan-out

±4mm Warped Wafer Chuck

AP300 Production Warped Wafer Chuck

Wafer Warpage: ~ 3.8mm before chucking

No Warpage After Chucking

Focus

offset: -4 mm +4 mm +10 mm 0 mm +6 mm -10 mm -6 mm

Cross sectional SEM images of 2 µm line/space through focus

AP300 Production Performance Window

Focus

offset: -2 mm +4 mm 0 mm -6 mm

Cross sectional SEM images of 1.5 µm line/space through focus

-4 mm +2 mm

InFO Production

Source: 2016 IEEE 66th Electronic Components and Technology Conference “InFO (Wafer Level Integrated Fan-Out) Technology” Douglas Yu, Ph.D. TSMC R&D, & SystemPlus Consulting

Fan-out wafer starts are increasing

dramatically in 2016

TSMC increased their integrated

fanout WLP (InFO) capacity ramp for

Apple’s A10 processor

It is estimated that InFO provides:

• 20% reduction in thickness

• 20% better performance

• 10% better thermal efficiency

CMOS Image Sensors Market

• CMOS image sensor (CIS) market is expected to reach $19B (based on 5 year 11% CAGR)

• Sony projected to maintain ~35% of the CIS market

• Advanced Packaging utilized for both improved signal integrity and size reduction

0

500

1,000

1,500

2,000

2,500

3,000

2015 2016 2017 2018 2019 2020

300mmW

aferDemand(Thousands)

©2016TechSearchInternational,Inc.

5-YearCAGR:6%

Source: TechSearch International, ChipWorks & Yole

CMOS Image Sensors Packaging

Source: TechSearch International, ChipWorks & Yole

Agenda

• Market Update

• Roadmap

• Summary

AP300 Production 1µm Features

Focus offset

155 mJ/cm2

150 mJ/cm2

145 mJ/cm2

140 mJ/cm2

0 um +3 um -3 um -4.5 um

Exp

osu

re

AP300 0.8µm Upgrades Available

Vertical 0.8 µm space

Horizontal 0.8 µm space

0 µm focus +1.5 µm focus +3 µm focus +4.5 µm focus

Lithography Product Roadmap

Re

so

luti

on

O

ve

rla

y

Th

rou

gh

pu

t W

arp

ag

e

2mm ghi-line Wide Field




2mm ghi-line Quad Field

0.5mm 0.5mm 0.35mm 0.35mm 0.25mm

Full Wafer Mapping

High Performance

Wafer Stage Quad Field Lens

+/- 2.25mm +/- 4.0mm +/- 7.0mm +/- 7.0mm +/- 7.0mm

De

pth

of

Fo

cu

s 20mm ghi-line 20mm ghi-line

10mm i-line 10mm i-line 10mm i-line

1.0mm i-line Wide Field (variable NA)

0.8mm i-line Wide Field (Demo)

0.8mm i-line Wide Field

i-line

only

i-line

only

20mm ghi-line 20mm ghi-line 20mm ghi-line

system to

itself

1mm system to

system 1mm 0.5mm 0.5mm 0.4mm

1.5mm i-line Wide Field

1.0mm i-line Wide Field (Demo)

10mm i-line

Agenda

• Market Update

• Roadmap

• Summary

Summary

Advanced Packaging Market Remains Strong

• Smartphones forecasted to account for 95% of all phones by 2019

• Advanced Packaging continues strong 5-year CAGR of 11%

• Wide variety of advanced packaging platforms (Fan-Out,

interposers and 3DIC)

Ultratech Lithography Products Continue Technical &

CoO Leadership

• AP products maintain dominant market position (>80%)

• Projected record sales in 2016

• AP products well positioned to take advantage of 2017 Fan-Out

applications growth

• Roadmap developed to provide extendibility


Analyst Day Event


San Jose, CA

November 15, 2016

Eric Bouche

General Manager & Vice President

Inspection Systems

Superfast

Enabling 3D Manufacturing

Agenda

• Superfast Leadership

• Growth Opportunities

• Market Update

• VNAND

• TOR for 48L pilot production

• Selected for 64L development

• DRAM

• TOR for 20nm pilot production

• Foundry

• Selected for N10/N7/N5 R&D

• TOR for N28 production

Superfast Leadership

Superfast 3D Drivers 3D distortion 3D planarization

2015 Distortion

VNAND 48L pilot production

2016 Planarization

VNAND 64L in development

Superfast CMP for 3D CMOS

10/23/16 44

Within Wafer Planarity

Histogram (r < 140mm)3-sigma = 45.81 nm

Range = 240.89 nm

Developing the inspection algorithms for

VNAND 64L qualification

Advantages over current metrology

No surface contact

Much higher throughput

Much higher density

Improving on-product overlay using Ultratech

Superfast 4G wafer shape metrologyLeon van Dijk, David Laidler (IMEC), Jeffrey Mileham (Ultratech),

Ronald Otten, Michael Kubis, Richard van Haren

APC Technical Day, May 31st, 2016

COMPANY SECRET

Introduction

More and more ASML customers are exploring the benefit of offline wafer shape measurements for

improving On-Product Overlay (OPO). The (unclamped) shape of wafers is typically changed by thin film

stress and variations in there. Feed-forward overlay control based on wafer shape metrology can be enabled

when a relationship between the wafer shape and the resulting In-Plane Distortion (IPD) after clamping is

established. At IMEC, we are currently investigating improved IPD feed-forward corrections in close

collaboration with Ultratech using their Superfast 4G inspection system.

Experimental setup and wafer processing

Wafer shape metrology Wafer processing: SiN deposition and etch

Scanner measurements

BMMO

wfrs (20)

Nitride deposited to create

warped wafers (4 groups):

Additional splits per 6-wafer group by SiN etch:

Memory

use case

Intrafield

stress

Wafer shape metrology

Scanner measurements

• Observed in-plane distortions (IPD) and wafer shape measurements are understood qualitatively from the applied processing

• Various IPD models are currently under evaluation for predicting IPD from the measured wafer shapes for the various use cases

• More details on background, experiment and results can be provided upon request ([email protected])

Main conclusions and next steps

Bowl

100 μm

Umbrella

50 μm

Main results

Umbrella

100 μm

Bowl

50 μm

Homogeneous processing

Apply self-referencing method: isolate process fingerprint by subtracting pre- and post processing measurements

Wafer shape change induced by SiN deposition and resulting IPD:

• Homogeneous processing results in 2nd order wafer shape

changes à mainly scaling (correctable by 6-par alignment)

• Wafer warp induces overlay errors towards wafer edge

Memory use case (initially 100 μm umbrella) Intrafield stress (100 μm umbrella)

Discard

edge fields

Wafer shape change (deviation from 2nd order shape)

induced by SiN deposition & etch and resulting IPD:

Wafer shape change (deviation from 2nd

order shape) and resulting IPD:

Local stress change

affects also inner fields

Homogeneous

processing

6/22/16 7

Joint collaboration since 2015Abstract

Lithography overlay and wafer topography control is becoming increasingly difficult, particularly at the wafer edge.

This study is a collaborative effort to evaluate the suitability of Coherent Gradient Sensing (CGS) interferometry technology in a manufacturing environment on advanced planar NAND and Bit Column Stacked (BiCS) 3D NAND flash memory devices.

Currently the system is proven for: Displacement Feed Forward (DFF), quality control, and high throughput at 126 WPH, with a roadmap to >150 WPH

Displacement Feed Forward

Yield sum percent for wafers run with and without DFF showing an improvement in both the total yield and the yield components related to overlay.

Yield improvement is possible with the combination of an intelligent overlay sampling scheme that includes DFF.

Mass Production

DFF is currently ramping for mass production and requires reproducible displacement results across a fleet of CGS metrology tools.

Background

Process-induced non-uniform stresses translate to in-plane displacement of the wafer surface. Traditional APC, with feedback control, cannot always account for large distortion variability in 3D structures.

CGS interferometric technology illuminates the whole wafer at once and rapidly determines per-wafer topography and in-plane displacement.

The Use of CGS Technology in a 3D Manufacturing EnvironmentJeffrey Mileham*, David M. Owen*, Doug Anberg*, and Yasushi Tanaka†

Ultratech Inc.* and Toshiba Corp.†

a.u.

Additional Collaborations

Reproducibility: Displacement reproducibility deviation from averaged value shows the variability within 0.1 nm (above).

Matching: Wafer-level displacement matching between two tools shows displacement deltas below 7.5 Å (3-s of point-by-point displacement difference over a 2 2 mm grid).

Applications: Future collaborations include: topography control, CMP planarization, and improved edge yield.

Conclusion

As semiconductor processing shifts to the 3rd dimension one of the most significant challenges is distortion. CGS technology is capable of measuring stress induced displacement, and when combined with traditional overlay corrections, can significantly improve critical layer overlay in a high volume manufacturing environment

Contact Information

[email protected]

ConditionTPUT

(WPH)

Pilot Production 81

BiCS wafer with new algorithm 126

Current production tool capability >150

Superfast 3D Inspection Leader

Superfast 3D Inspection Leader

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

2013 2014 2015 2016(YTD)

$ Market Share

Ultratech Competitor

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

2013 2014 2015 2016(YTD)

Inspection Passes

Ultratech Competitor

Agenda



• Market Update

While 3D

Manufacturing Matures

Superfast Growth Opportunities

Superfast Growth

Opportunities

3D Planarization Requirements

Chip Planarization Edge Topography

High aspect ratio structures

Topography residuals variability

Edge process non uniformity

Very low edge yield

2017

28nm Foundries

Yield Ramp

2018 Integrated

Inspection Module

Superfast 28nm Foundry TOR

Wafer-shape metrics based foundry lithography Sean Lee1, Albert Huang1, CF Hua1, Ming Sheng Wei1, Kennes Chen2, Eric Bouche2

1. United Microelectronics Corporation, UMC (Taiwan)

2. Ultratech inc. (United States of America)

Wafer shape process control in Foundry Lithography Sean Lee1, Albert Huang1, CF Hua1, Ming Sheng Wei1, Kennes Chen2, Eric Bouche2



Chamber Distortion Control in a High Volume Manufacturing

Foundry Environment Sean Lee, MT Lee, Tony Chen, Maddux Chen, Frida Liang, Kennes Chen,

Jeffrey Mileham, David M. Owen



Superfast 28nm Yield Improvement

2017 28nm Foundries Opportunity

Manufacturing Yield Loss

Superfast Process Flow Scan

Variability Inflections Detected

Engineering SPC Fix

3D Advanced Process Control

Scanner

CMP

Diffusion

Thin Film

Measure Upstream Process Provide Actionable Output

Feedback

Excursion Control

Process Tuning Parameters

Feedforward

Displacement Correctables

Planarity / Flatness

Defects

CMP Diffusion

+

CoO Driving Integrated Metrology

0

0.2

0.4

0.6

0.8

1

1.2

Superfast 3G Superfast 3G+ Superfast 4G Superfast 4G+

Superfast 4GTurbo Superfast 4GT_L Superfast 4GT_B

Superfast Stand Alone Integrated Modules

Small

Form

Factor

@

High

Speed

2018 Ultratech patented high speed CGS module

Agenda



• Market Update

Superfast 3D Inspection TAM

0

10

20

30

40

50

60

70

2015 2016 2017 2018 2019

Normalized Sampling Volume

Engineering

Lithography

CMP

Diffusion

CVD

Integrated

Summary


• Planarization for 64L Development

• >70% Market Share in 2016


• 2017 28nm Foundry

• 2018 Integrated Module

• Market Update

• Growing TAM use cases


Analyst Day Event


San Jose, CA

November 15, 2016


Chief Technologist, Surface Metrology

Advanced Process Control

with Superfast

• Technology Overview

• Shape-based Process Fingerprinting

• CMP Control in 3D NAND

• Summary

Agenda

Superfast 4G+ System Overview

• 3D patterned inspection

for wafer topography,

distortion and stress

• Unique CGS Technology • Comprehensive Wafer Mapping

• Lowest CoO

• Best-in-class performance

• Key Applications • Planarization

• Process Fingerprinting

• Chamber Excursion Control

Topography Distortion Stress

+

Grating 1 Grating 2

Collimated Laser

Beam Takes

Optical Imprint of

Wafer Surface

Gratings Create

‘Copies’ of

Reflected Beam

From Diffraction

Interference

Generated from

Double-Image of

Two Copies

Wafer

High-Speed Interferometer

Dy

Du3

Dy

Du3 slope =

Full-Wafer, Self-Referencing, Common Path: Few Moving Parts

Acquisition & Analysis

New high-accuracy algorithms

Wafer Handling

Simple, high speed, repeatable

Optics & System

Improved measurement

range, temp control

Superfast Manufacturing Advantage

Best-in-Class

Highest Precision

Highest Throughput

Smaller Footprint

Lowest Cost

+

New Topography Fingerprinting

• Evaluate topography ‘fingerprints’ to quickly

understand sources of process variability

• Process-to-process fingerprints

• Chamber-to-chamber fingerprints

• Relate fingerprints to downstream issues

• Yield

• Lithography de-focus

• Lithography overlay control

Multi-Process Analysis

Quickly identify

source of edge

topography

Process-induced Edge Topography

Fingerprint > 30 process in the flow

• Comprehensive process

fingerprinting with Superfast

can be used to quickly identify

out-of-control processes

• Analysis process

• Acquire data at numerous

processes (>30 in sequence

shown to left)

• Identify critical segment of

process flow (e.g. process 21)

• Relate topography & stress of

critical process to yield loss (see

subsequent slide)

CMP Diagnostics

Pre-Deposition Post-Deposition Post-Plating Post-CMP

~34 microns ~34 microns ~139 microns ~32 microns

Post-Pre Deposition Post-Pre Plating Post-Pre CMP

~2 microns ~105 microns ~107 microns

Defocus & Yield Correlation Post-CMP minus Pre-Deposition Die-by-Die Local Topography

0

1

2

3

4

5

6

Fai

lure

Pro

bab

ilit

y (%

)

Local Topography

0 0.15 0.20 0.25 1.00

Local Topography Variation

Die

Fa

ilure

•Fingerprint quickly identifies critical

process steps

•Superfast die-to-die variation can be

related to defects and yield

•Highest local topography values are

related to a >5% failure rate

compared to baseline of <1%

Chamber Matching

Chamber 1 Chamber 2

Chamber 3 Chamber 4

Different Chambers May Have Different Displacement Fingerprints

3D NAND Overlay Control

• Chamber matching will

influence subsequent down-

stream processes

• Superfast displacement

reveals sources of process-

induced overlay errors

• Chamber matching and

process control (feed-back) or

lithography corrections (feed-

forward) can be implemented

CMP Variation for 3D NAND

Measured Topography Global Wafer Shape Pattern Topography = +

Topography Range

~150 microns

Topography Range

~150 microns

Topography Range

~20 nanometers

Separation of Wafer Shape and Pattern Topography

Within-Wafer Variations in Pattern Topography Quantifies CMP Uniformity

Examples of CMP Variability Different Process CMP Parameters (A-F) Lead to Varying Pattern Uniformity

A B C

D E F

Roadmap for Process Control

Full-Wafer Topography

>3M Data Points

Field-Level Topography

>10,000’s Data Points

Scanner

CMP

SUPERFAST APC

Diffusion

Thin

Film

ALGORITHMS

Modeling Accuracy & Precision

Efficiency (High Throughput)

Hybrid Inspection

New Applications

Rapid Development

Enabling New Use Cases

Summary

• Superfast provides comprehensive data for process

monitoring and control

• Process flow characterization provides rapid issue

identification and resolution

• Emerging applications driven by algorithm

development for high resolution, high accuracy process

control for HVM


Analyst Day Event


San Jose, CA

November 15, 2016

Closing Remarks

Art Zafiropoulo

Chairman & Chief Executive Officer

November 15, 2016

Projections 2016 Significant Recovery

Advanced Packaging

Record Sales

Dominant Market Share

LSA

Sharp increase in LSA orders

Laser melt future impact

Superfast

Initial acceptance in volume production for VNAND

Penetration at multiple fabs

New applications

Nanotechnology

Increased Sales for ALD

Harvesting mode for HBLED Lithography

Overall terrific 2016 transitional year leading into a projected

continuation of strong growth for 2017

Thank You!

Thirteenth Annual Analyst Day Event -...

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