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Wafer-to-Wafer Bonding and Packaging

Dr. Thara SrinivasanLecture 25

Picture credit: Radant MEMS

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Lecture Outline• Reading

• Senturia, S., Chapter 17, “Packaging.”• Schmidt, M. A. “Wafer-to-Wafer Bonding for

Microstructure Formation,” pp. 1575-1585. • Tummala, R.R. “Fundamentals of Microsystems

Packaging,” pp. 556-66.

• Today’s Lecture• MEMS Packaging: Why a Whole Lecture?• Wafer Bonding Methods for MEMS• Bonding Tools and Characterization• Packaging: Die-Level, Wafer-Level…

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5MEMS and the Package

• Packaging electronics• Provide electrical interconnects, protect electronics• Dice up wafer, assemble into ceramic/plastic package• Single package, many chips

• Packaging MEMS• Provide electrical (and other, i.e., fluidic, optical) interconnects,

protect micromechanical elements, interface with outside environment

• Dicing cannot be done after release unless precautions taken• Environment inside package important• Package should not mechanically stress MEMS

• Single chip, many packages

• Packaging, test and calibration important to MEMS design

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Current MEMS PackagesDie Level Wafer Level

Bosch Gyroscope

Wafer bonded package with glass frit seal and lateral feedthroughs

Cronos Relay

Die level release and ceramic package

Motorola Accelerometer

Wafer bonded package with glass frit seal and lateral feedthroughs(sealed MEMS is then placed into ceramic package)

Partial Hexsil cap assembled onto Sandia iMEMS chip

using wafer-to-wafer transfer

MEMS region

CMOS region

BSAC/Sandia

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5Lecture Outline

• MEMS Packaging• Wafer Bonding Methods for MEMS• Bonding tools and characterization• Packaging: die-level, wafer-level…

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MIT microturbine

Wafer Bonding in MEMS

Motorola pressure sensor

• Wafer-level packaging• MEMS device construction

• Sealed structures, i.e., pressure sensors and fluidic channels

• Multiwafer structures, i.e., µTAS, microturbines, optical devices, inkjet print heads

Jensen group, MIT

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5Sealed Structures

• Microfluidic channel structures• Pressure sensors and valves

Redwood Microsystems MEMS valve

Caliper Technologies

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Wafer Bonding Methods

• Surface bonding• Metallic layer bonding• Insulating layer bonding

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5Fusion Bonding

• Two ultra-smooth (<10 Å roughness) wafers are bonded without adhesives or applied external forces

• Technique• Surface preparation: O2 plasma, hydration, or HF dip• Room temperature contacting leads to hydrogen bonding, van

der Waals forces• Annealing at 600-1200°C brings bond to full strength• Low temperature fusion bonding also possible using Ziptronix

surface preparation

• Mechanism • Hydrophilic ~ Si – O – Si• Hydrophobic ~ Si – Si

Ziptronix

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Anodic Bonding• Bonds an electron conducting material, Si, to an ion conducting material,

e.g. sodium glass (Pyrex)

• Technique• Voltage applied ~ 200-1500 V• Elevated temperature ~ 180-500°C• Positive ions in glass migrate, creating

depletion layer near Si surface; voltage drop creates large E-field pulling surfaces into contact

• Pro and con– CTE mismatch concerns+ Hermetic sealing

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5Anodic Bonding

1. after 5 sec 2. after 20 sec

ø100 mm,Pyrex® -500 µm,430 °C,800 V,N2 - 1000 mbar

3. after 2,5 min 4. after 8 min

Only center bond pin active All bond pins active

Bond front spreads Bond 98% completed

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Metal Layer Bonding• Pattern seal rings and bond pads photolithographically

• Eutectic bonding • Uses eutectic point in metal-Si phase diagrams to form silicides• Au and Si have eutectic point at 363°C+ Low-T process, can bond slightly rough surfaces– Au contamination of CMOS

• Solder bonding• PbSn (183°C), AuSn (280°C) + Lower-T process, can bond really rough surfaces

• Thermocompression• Commonly done with electroplated Au, other soft metals• T ~ room temperature to 300°C• P ~ 1-2 MPa+ Lowest-T process, can bond rough surfaces, topography

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5Thermocompression Bonding

Angad Singh, et al., Transducers ‘97

• Transfer of hexsil actuator onto CMOS wafer

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Bonding with Insulating Layers

• Adhesives, i.e. epoxies, BCB

• Glass frit bonding• Stencil or screen

printed glass paste• 350-450°C: glass

flows• Hermetic• Wide sealing layer

required (500 µm)

Cap Wafer

Screen Glass Paste

Cap Wafer

Device Wafer

Glass Frit Frame

DeviceP: 1000 mbar

T: 425°C

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Glass Frit Bonding

Suss MicroTEC

Packaged switch by Radant MEMS

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Wafer Bonding Methods

non-hermeticversatileAdhesive

solder flow possibleself-aligningSolder

high forcenon-flat surface okThermocompression

variesvariesSurface-activated

high tempstrong bondFusion (Direct)

Non-flat surface ok Varies

Specific metals requiredHermeticNon-flat surface ok

Flat surface requiredHermetic

large areamedium-hi temp

hermeticcommon in MEMS

Glass frit

flat surface req’dstrong bondEutectic

high-voltagestrong bondAnodic

Insulating interlayer

Metallic interlayer

“Surface” bonding

DrawbacksAdvantagesTechniques

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5Lecture Outline

• MEMS Packaging• Wafer Bonding Methods for MEMS• Bonding Tools and Characterization• Packaging: Die-Level, Wafer-Level…

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Bonding Tool

Suss SB 6e Bonder

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5Wafer Bonding Considerations

• Topography: planar or textured?• Material: insulating or conducting?• Hermeticity required?• Maximum temperature or force allowed?• Biocompatibility?

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Bond Characterization• Nondestructive

• Visual inspection• Imaging ~ IR transmission, ultrasonic, X-ray

topography

• Destructive • Cross-sectional analysis using SEM or TEM• Defect etching a cross-sectioned sample• Bond strength measurement techniques

• Pressure burst test• Tensile-shear test• Knife-edge test

X-ray

Acoustic

IR

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5Lecture Outline

• MEMS Packaging• Wafer Bonding Methods for MEMS• Bonding Tools and Characterization• Packaging: Die-Level, Wafer-Level…

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Issues Specific to MEMS Packaging

• MEMS are micromechanical structures• Damaged during dicing step?• Package environment important: hermeticity required?

• Considerations• Bonding method• Stack thickness• Mechanical stress of package• Coefficient of thermal expansion mismatch• Thermal management• Electrical feedthrough method

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5Packaging Approaches

• Die-level vs. wafer level

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Die Level Packaging• Conventionally, MEMS have been

diced, then released to protect them from the sawing process.• But die-level release is expensive

and slow

• Die are then packaged in ceramic cavity packages.• Ceramic packages are large and

expensive

Fabricate Singulate Release Package

Ceramic Cavity

Package

Cronos Relay

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5Dicing After Release?

Texas Instruments’ fabrication and packaging

for DMD chip

Analog Devices’ upside-down-saw

process

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Wafer Level Packaging• Alternately, do the MEMS release at the wafer level

• Release seal dice• Wafer level packaging must follow the wafer level release, to

avoid damaging the MEMS.• Much smaller packages are possible.

Fabricate Release Wafer bond

Singulate

Chip Scale Package (CSP)

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5Wafer-level packaged MEMS

Packaged gyroscope by IMEC, Bosch and STS

Packaged switch by Radant MEMS

Clarisay surface acoustic wave filters

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Wafer-Level MEMS Package Types

• Bulk wafer caps• Current Industry

standard

• Micro-assembledhexsil caps• Berkeley

• In situ caps• Toyota• Berkeley

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Bulk Wafer Caps

• Industry standard, examples:• Motorola accelerometers• Bosch gyroscopes• Clarisay SAW filter• Radant MEMS switch

• Pros and cons+ Robust+ Hermetic+ Wafer-level– Large on-chip area required for

seal ring

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Micro-Assembled Caps• Fabricate microcaps on donor

wafer• Transfer microcaps to target

wafer by wafer bonding and separation

• Thin seal ring requires little real estate (~1% of bulk cap)• Potentially much less expensive

than wafer-bonded caps

Align Bond Separate

M. Cohn PhD, J. Heck PhD, Howe group

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5Micro-Assembled Cap Fabrication

Recess etch

Deposit & pattern sacrificial, structural layers

Deep trench etch

Electroplate gold bumps & seal ring

Release etch

Thermocompression-bond to target wafer

• The hexsil process makes “honeycomb” type, high-aspect-ratio structures from thin film deposition

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Microcap Assembly

Several hexsil caps assembled onto bare gold die

Partial Hexsil cap assembled onto Sandia iMEMS chip

MEMS region

CMOS region

Heck PhD, Howe group, Sandia Labs

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In Situ Sealing• Seal MEMS devices on wafer scale post-

release• Microshells fabricated over MEMS• Release etch frees MEMS through access

holes• Access holes are sealed using film deposition,

possibly at low pressure+ Simplifies packaging process– Adds development to fabrication process

shell

MEMSLebouitz et al., BSAC Toyota

T. Corman et al.

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Hermeticity• Hermetic package has internal cavity with acceptable level of

gas-tightness• Metals, glasses, semiconductors are considered hermetic

materials; plastic seals are not• Getters (certain metal alloys) can absorb and react with gases in

package to keep pressure low

T. Corman et al

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5Wafer Level Package Interconnects

wafer

cap

• Through-silicon vias+ Small area required+ True chip scale package (BGA-ready)– Expensive processing

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• Lateral surface feedthroughs+ Simplest fabrication– Larger on-chip area required – Not a true chip scale package

(substrate required)– Wire bonding required

Wafer Level Package Interconnects

wafer

T. Corman

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5Wafer Level Package Interconnects

• Hybrid approach, e.g., Shellcase“T” contact, ChipScale• Feedthroughs on MEMS wafer are

contacted by sawing through wafer backside

+ Small area required+ True chip scale package (BGA-

ready)– Shellcase proprietary

MEMS waferTop cover wafer

Bottom cover wafer

MEMS waferTop cover wafer

Bottom cover wafer

MEMS waferTop cover wafer

Bottom cover wafer

MEMS wafer

Top cover wafer

Contact pad on the die

External lead

MEMS wafer

Top cover wafer

Contact pad on the die

External lead

ChipScale

Shellcase

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Packaging Testing and Failure

• Failure mechanisms • Delamination, e.g. due to temperature cycling• Environmental exposure and loss of hermeticity

• Testing hermeticity• Helium leak detection• Radioisotope method• IR method

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5Packaging for Fluidics

• In addition to electronic interfaces…• Fluidic interface for

sample introduction• Optical interface for

detection

• Implantable devices• Biocompatibility • Don’t shock the patient

Cepheid