Tampere 01 Course 4

7/30/2019 Tampere 01 Course 4

1/81

Enabling Technologies for

Reconfigurable Computing

Enabling Technologies for

Reconfigurable Computing

Part 4:

FPGAs: recent developments

Wednesday, November 21, 16.00 17.30 hrs.

Reiner Hartenstein

University ofKaiserslautern

November 21, 2001, Tampere, Finland


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2001,[email protected] http://www.fpl.uni-kl.de

University of Kaiserslautern

XputerLab

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Schedule

time slot

08.30 10.00 Reconfigurable Computing (RC)

10.00 10.30 coffee break

10.30 12.00 Stream-based Computing for RC

12.00 14.00 lunch break

14.00 15.30 Resources for RC

15.30 16.00 coffee break16.00 17.30 FPGAs: recent developments


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>> Configware Market

Configware Market FPGA Market

Embedded Systems (Co-Design)

Hardwired IP Cores on Board

Run-Time Reconfiguration (RTR)

Rapid Prototyping & ASIC Emulation

Evolvable Hardware (EH)

Academic Expertise

ASICs dead

Soft CPU

HLLs

Problems to be solved


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Configware heading for mainstream

Configware market taking off for mainstream FPGA-based designs more complex, even SoC No design productivity and quality without good

configware libraries (soft IP cores) from various

application areas. Growing no. of independent configware houses

(soft IP core vendors) and design services AllianceCORE & Reference Design Alliance

Currently the top FPGA vendors are the keyinnovators and meet most configware demand.


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bleeding edge designs

Infinite amount of gates not yet available on a chip 3 mio gates (10 mio in 2003 ?) far away from "infinite"

Bleeding edge designs only with sophisticated EDA tools

Excessive optimization needed Hardware epertise is inevitable for the designer.

improve and simplify the design flow the user

provide rich configware libraries of soft IP cores,

control appl., networking, wireless telecommunication, datacommunication, embedded and consumer markets.


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Configware (soft IP Products)

For libraries, creation and reuse of configware To search for IPs see: List of all available IP

The AllianceCORE program is a cooperationbetween Xilinx and third-party core developers

The Xilinx Reference Design Alliance Program

The Xilinx University Program

LogiCORE soft IP with LogiCORE PCI Interface. Consultants


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EDA as the Key Enabler (major EDA vendors)

Select EDA quality / productivity, not FPGA architectures EDA often has massive software quality problems

Customer: highest priority EDA center of excellence collecting EDA expertise and EDA user experience

to assemble best possible tool environments for optimum support design teams

to cope with interoperability problems

to keep track with the EDA scene as a rapidly moving target

being fabless, FPGA vendors spend most qualified manpowerin development of EDA, IP cores, applications , support

Xilinx and Altera are morphing into EDA companies.


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OS for FPGAs

separate EDA software market, comparable tothe compiler / OS market in computers,

Cadence, Mentor, Synopsys just jumped in.

< 5% Xilinx / Altera income from EDA SW

Changing EDA Tools Market Major configwareEDA vendors Altera Cadence

Mentor Graphics Synopsys Xilinx


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EDA Software for Xilinx

Full design flow from Cadence, Mentor, & SynopsysXilinx Software AllianceEDA Program:

Alliance Series Development System.

Foundation Series Development Systems.

Xilinx Foundation Series ISE (Integrated Synthesis Environment)

free WebPOWERED SW w. WebFitter & WebPACK-ISE

StateCAD XE and HDL Bencher

Foundation Base ExpressFoundation ISE Base Express


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Foundation ISE Base Express

ModelSim Xilinx Edition(ModelSim XE)

Forge Compiler

Modular Design Chipscope ILA

The Xilinx SystemGenerator

XPower

JBits SDK

The Xilinx XtremeDSPInitiative

MathWorks / XilinxAlliance

System Generator

Wind River / Xilinxalliance


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Altera EDA

Altera was founded in June 1983

EDA: synthesis, place & route, and, verification

Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families

MAX+PLUS II: FLEX, ACEX & MAX families

Flow with Quartus II: Mentor Graphics, Synopsys, Synplicitydeliver a design design software to support Altera SOPC solutions.

Mentor: only EDA vendor w. complete design environment f. APEXII incl. IP, design capture, simulation, synthesis, and h/s co-verification

Configware: Altera offers over a hundred IP cores

Third party IP core design services and consultants


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Cadence

FPGA Designer: top-down FPGA design system, high-level mapping, architecture-specific optimization,

Verilog,VHDL, schematic-level design entry.

Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer

FPGAs simulated by themselves using Cadence's Verilog-XL or Leapfrog VHDL simulators and

simulated w. rest of the system design w. Logic

Workbench board/system verification envment. Libraries for the leading FPGA manufacturers.


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Mentor Graphics

System Design and Verification.

PCB design and analysis:

IC Design and Verification

shifts ASIC design flow to FPGAs (Altera, Xilinx) by FPGA Advantage with IP support by ModuleWare, Xilinx CORE Generator Altera MegaWizard integration,


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Synopsys

FPGA Compiler II

Version of ASIC Design Compiler Ultra

Block Level Incremental Synthesis (BLIS)

ASIC FPGA migration

Actel, Altera, Atmel, Cypress, Lattice,Lucent, Quicklogic, Triscend, Xilinx


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>> FPGA Market

Configware Market

FPGA Market




Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH)

Academic Expertise

ASICs dead

Soft CPU

HLLs



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Top 4 PLD Manufacturers 2000

Xilinx42%

Altera

37%

Lattice15%

Actel6%

Top 4 PLD Manufacturers 2000

$3.7 Bio


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FPGA market 1998 / 1999

3832Atmel84030Quicklogic7

4341Cypress6

120100Lucent5

172154Actel4 410206Lattice3

837654Altera2

899629Xilinx119991998

global sales (mio $)

1999 rankSource:IC Insights Inc.

Meanwhile,

Xilinx acquiredPhilips' MOS PLDbusiness,

Latticepurchased Vantis.

.


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.... into every application

[Dataquest] PLD market > $7 billion by 2003.

fastest growing segment of semiconductormarket.

IP reuse and "pre-fabricated" components forthe efficiency of design and use for PLDs

FPGAs are going into every type of application.


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.... going into every type of application[Gordon Bell]


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Xilinx

fabless FPGA semi vendor, San Jose, Ca, founded 1984

key patents on FPGAs (expiring in a few years)

Fortune 2001: No. 14 Best Company to work for in (intel:no. 42, hp no. 64, TI no. 65).

DARPA grant (Nov99) to develop Jbits API tools forinternet reconfigurable / upgradable logic (w. VT)

Less brilliant early/mid 90ies (president Curt Wozniak):1995 market share from 84% down to 62% [Dataquest]

As designs get larger, Xilinx losed its advantage (bugfixesdid not require to burn new chips)

meanwhile, weeks of expensive debug time needed


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Xilinx Flexware

Virtex, Virtex-II, first w. 1 mio system gates.

Virtex-E series > 3 mio system gates. Virtex-EM on a copper process & addit. on chip memory f. network switch appl. The Virtex XCV3200E > 3 million gates, 0.15-micron technology,

Spartan, Spartan-XL, Spartan-II for low-cost, high volume applications as ASIC replacements Multiple I/O standards, on-chip block RAM, digital delay lock loops eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers

XC4000XV, XC4000XL/XLA, CPLD: low-cost families rapid development, longer system life, robust field upgradability support In-System Programming (ISP), in-board debugging, test during manufacturing, field upgrades, full JTAG compliant interface

CoolRunner: low power, high speed/density, standby mode. Military & Aerospace: QPRO high-reliability QML certified Configuration Storage Devices


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Altera Flexware

Newer families: APEX 20KE, APEX 20KC, APEX II, MAX7000B, ACEX 1K, Excalibur, Mercury families.

Apex EP20K1500E (0.18-), up to 2.4 mio system gates,

APEX II (all-copper 0.13-) f. data path applications, supportsmany I/O standards. 1-Gbps True-LVDS performance

wQ2001, an ARM-based Excalibur device

Altera mainstream: MAX 7000A, 3000A; FLEX 6000,10KA, 10KE; APEX 20K families.

Mature and other : Classic, MAX 7000, 7000S, 9000;FLEX 8000, 10K families.


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Triscend CSoC

Digital Filter Display Interface

Viterbi A/D Interface

CSI Socket

ARM

Configurable system logic

Configurable System Interconnect (CSI) Bus

Other System ResourcesMemory

[Kean]


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>> Embedded Systems (Co-Design)

Configware Market

FPGA Market





Academic Expertise

ASICs dead

Soft CPU

HLLs



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Goal: away from complex design flow

Placeand

RouteNetlist

Schematics/

HDL Netlister

Bitstream

CompilerHLL

[ la S. Guccione]


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Overcome traditional separate design flow

UserCode

Compiler Executable

Netlister NetlistPlace

and

Route..

Bitstream

Schematics/

HDL

HLL Compiler

[ la S. Guccione]


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Overcome traditional co-processing designseparate flow -> JBitsDesign Flow

User

Java

Code

Java

Compiler

JBits

API

Executable

UserCode

Compiler Executable

Netlister Netlist

Place

andRoute..

Bitstream

Schematics/

HDL

[ la S. Guccione]

E b dd d h d CPU &


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Embedded hardw. CPU & memory coreson chip.

HLL Compiler

CPUcore

FPGA core

Memorycore

HLL Compiler

[ la S. Guccione]

d l d l


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new directions in application development

new directions in application development. aut. partitioning compilers: designer productivity

like CoDe-X (Jrgen Becker, Univ. of Karlsruhe),

supports Run-Time Reconfiguration (RTR), a keyenabler of error handling and fault correction bypartial re-routing the FPGA at run time, as well asremote patching for upgrading, remote debugging,

and remote repair by reconfiguration - even overthe internet.

R Ti R fi ti (RTR)


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>> Run-Time Reconfiguration (RTR)

Configware Market

FPGA Market





Academic Expertise

ASICs dead

Soft CPU

HLLs


CPU f fi ti t


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CPU use for configuration management

on-board microprocessor CPU is availableanyhow - even along with a little RTOS

use this CPU for configuration management

CompilerHLL

RTR System Design

h d CPU & hi


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hard CPU & memory core on same chip

CPUcore

FPGA core

MemorycoreCompilerHLL

CompilerHLL

RTR System Design

C nver in fact rs f r RTR


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Converging factors for RTR

User

JavaCode

Java

Compiler

JBits

API

Executable

Converging factors make RTR based system design viable 1) million gate FPGA devices and co-processing withstandard microprocessors are commonplace

direct implementation of complex algorithms in FPGAs.This alone has alreadyrevolutionized FPGA design.

2) new tools like Xilinx Jbitssoftware tool suite directlysupport coprocessing and RTR.

RTR


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RTR

divides application into a series of sequentially executed stages, each

implemented as a separate execution module. Partial RTR partitions these stages into finer-grain sub-modules to be

swapped in as needed. Without RTR, all conf. platforms just ASIC emulators. needs a new kind of application development environments.

directly support development and debugging of RTR appl. essential for the advancement of configurable computing will also heavily influence the future system organization Xilinx, VT, BYU work on run-time kernels, run-time support, RTR

debugging tools and other associated tools. smaller, faster circuits, simplified hardware interfacing, fewer IOBs;

smaller, cheaper packages, simplified software interfaces.

Run time Mapping


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Run-time Mapping

run-time reconfigurable are: Xilinx VIRTEX FPGA familyRAs being part of Chameleon CS2000 series systemsUsing such devices changes many of the basic assumptionsin the HW/SW co-design process:

host/RL interaction is dynamic, needs a tiny OS like eBIOS,also to organize RL reconfiguration under host control

typical goal is minimization of reconfiguration latency(especially important in communication processors), to hideconfiguration loading latency, and,

Scheduling to find best schedule for eBIOS calls (C~side).

>> Rapid Prototyping & ASIC Emulation


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>> Rapid Prototyping & ASIC Emulation

Configware Market

FPGA Market





Academic Expertise

ASICs dead

Soft CPU

HLLs


ASIC emulation: a new business model ?


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ASIC emulation: a new business model ?

ASIC emulation / Rapid Prototyping: to replace simulation

Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)

from rack to board to chip (from other vendors, e. g.

Virtex and VirtexE family (emulate up to 3 million gates)

Easy configuration using SmartMedia FLASH cards

ASIC emulators will become obsolete within years

By RTR: in-circuit execution debugging instead of emulation

>> Evolvable Hardware (EH)


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>> Evolvable Hardware (EH)

Configware Market

FPGA Market





Academic Expertise

ASICs dead

Soft CPU

HLLs


EH EM


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EH, EM, ...

"Evolvable Hardware" (EH), "Evolutionary Methods" (EM),

digital DANN, "Darwinistic Methods", and biologicallyinspired electronic systems

new research area, also a new application area of FPGAs

revival of cybernetics or bionics: stimulated by technology

evolutionary and DNA metaphor create awareness

EM sucks, also thru mushrooming funds in the EU, inJapan, Korea, and the USA

EM-related international conference series are in theirstormy visionary phase, like EH, ICES, EuroGP, GP, CEC,GECCO, EvoWorkshops, MAPLD, ICGA

EH EM


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EH, EM, ...

Shake-out phenomena expected, like in the past withArtificial Intelligence

should be considered as a specialized EDA scene,focusing on theoretical issues.

Genetic algorithms suck - often replacable by moreefficient ones from EDA

It is recommendable to set-up an interwoven competencein both scenes, EM scene and the highly commercialized

EDA sceneEH should be done by EDA people, rather than EM freaks.

>> Academic Expertise


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>> Academic Expertise

Configware Market

FPGA Market





Academic Expertise

ASICs dead

Soft CPU

HLLs


BRASS (1)


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BRASS (1)

UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek

The Pleiades Project, Prof. Jan Rabaey, ultra-low power highperformance multimedia computing through reconfigurationof heterogeneous system modules, reducing energy byoverhead elimination, programmability at just right

granularity, parallellism, pipelining, dynamic voltage scaling. Garp integrates processor and FPGA; dev. in parallel w.compiler - software compile techniques (VLIW SWpipelining): simple pipelining schema f. broad class of loops.

SCORE, a stream-based computation model - a unifyingcomputational model. Fast Mapping for Datapaths: by a treeparsing compiler tool for datapath module mapping

BRASS (2)


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BRASS (2)

HSRA. new FPGA (& related tools) supports pipelining, w.retiming capable CLB architecture, implemented in a 0.4umDRAM process supporting 250MHz operation

OOCG. Object Oriented Circuit-Generators in Java

MESCAL (GSRC), the goal is: to provide a programmer'smodel and software development environment for efficientimplementation of an interesting set of applications onto afamily of fully-programmable architectures /

microarchitectures.

Berkeley claiming (1)


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SCORE, a stream-based computation model: the BRASS group claims

having solved the problem of primary impediment to wide-spreadreconfigurable computing, by a unifying computational model.

Remark: clean stream-based model introduced ~1980: Systolic Array

1995: Rainer Kress. Introduces reconfigurable stream-based model

Fast Mapping for Datapaths (SCORE): BRASS claims havingintroduced 1998 the first tree-parsing compiler tool for datapathmodule mapping ." Further, it is the first work to integrate

simultaneous placement with module mapping in a way that preserveslinear time complexity."



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Remark: The DPSS (Data Path Synthesis System) usingtree covering simultanous datapath placement and routinghas been published in 1995 by Rainer Kress

Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Brodersonsradical rethink of the ASIC design flow aimed atshortening design time, relying on stream-based DPUarrays. [published in 2000]

Remark: the KressArray, a scalable rDPU array [1995] isstream-based

.... Stream Processors -MSP-3


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.... m M

3rd Workshop on Media and Stream Processors (MSP-3)

http://www.pdcl.eng.wayne.edu/msp01 in conj. w. 34th Intl Symp. on Microarchitecture (MICRO-34)

http://www.microarch.org/micro34

Austin, Texas, December 1-2, 2001 Topics of interest include, but are not limited to:

Hardware/Compiler techniques for improving memoryperformance of media and stream-based processing

Application-specific hardware architectures for graphics, video,audio, communications, and other media and streamingapplications

System-on-a-chip architectures for media & stream processors Hardware/Software Co-Design of media and stream processors and others ....

Berkeley: Chip-in-a-Day Bee Project


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y p y j

Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting

a radical rethink of the ASIC design flow aimed at shorteningdesign time. Relying on stream-based DPU arrays (not rDPU andrelated EDA tools. Davis: ... 50x decrease in power requ. overtypical TI C64X design.

New design flow to break up the highly iterative EDA process,allowing designers to spend more time defining the device andfar less time implementing it in silicon. ... developers to start bycreating data flow graphs rather than C code,

It is stream-based computing by DPU array (hardwired DPA)

For hardwired and reconfigurable DPU array and rDPU array

Stanford thru BYU


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Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Lab

no activities seen other than YAFA (yet another FPGA application) UCLA: Prof. Jason Cong, expert on FPGA architectures and R& Palgorithms. 9 projects, mult. sponsors under California MICRO Progra

Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs, a nerouting architecture, architecture-aware CAD, IP-aware SPS compiler

USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurablecomputing: MAARC project, DRIVE project and Efficient Self-Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulationscalable multiprocessors.

DEFACTO proj.: compilation - architecture-independent at all levels MIT.MATRIX web pages removed `99. RAW project: a conglomerat VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA).

Prof. Brad Hutchings, BYU on programming approaches for RTR Syste BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware

Description Language) and compilation of JHDL sources into FPGAs.

Toronto thru Karlsruhe


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U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg.

The group has dev. Transmogrifier C, a C compiler creating netlist forXilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.

Founder of Right Track CAD Corporation acquired by Altera in 1999

Los Alamos National Laboratory, Los Alamos, New Mexico (JeffArnold) Project Streams-C: programming FPGAs from C sources.

Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins,methods for MPEG-4 like multimedia applications on dynamicallyreconfigurable platforms, & on reconf. instruction set processors.

University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker:

hardware/software co-design, reconfigurable architectures & rel.synthesis for future mobile communication systems & synthesis w.

distributed internet-based CAD methods, partitioning co-compilers

>> ASICs dead ?


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Configware Market

FPGA Market






Academic Expertise

ASICs dead ?

Soft CPU

HLLs


X t L b

(When) Will FPGAs Kill ASICs?


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[Jonathan Rose]

ASICs Are Already Dead

They Just Dont Know It Yet!

My Position[Jonathan Rose]

X t L bWhy? [Jonathan Rose]


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y [ ]

1. You have to fabricate an ASIC Very hard, getting harder

2. An FPGA is pre-fabricated A standard part

immense economic advantages

Xputer Lab

Making ASICs is Damn Difficult


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[Jonathan Rose]

Testing Yield Cross Talk Noise Leakage Clock Tree Design Horrible very deep submicron effects we

dont even know about yet

Xputer Lab

Did I Mention Inventory? [Jonathan Rose]


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ASIC users must predict # parts 2 or 3 months in advance!

Never guess the Right Amount Make Too Many You Pay holding costs

Make Too Few Competitor gets the Sale

[Jonathan Rose]

Xputer Lab

[Jonathan Rose] FPGAs Give You


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Instant Fabrication Get to Market Fast Fix em quick

Zero NRE Charges Low Risk

Low Cost at good volume

Xputer LabFPGAs: Too Pricey & Too Slow ?


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[Jonathan Rose]

Custom IC Designer Can Make Logic 20x Faster,

20x Smaller than Programmable

9 Times Out of 10 You make can the thing fast by breaking it

into multiple parallel slower pieces

Xputer Lab

Whats Wrong with This Picture?


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1. Still Have to Make the Chip2. Need Two Sets of Software to Build It

The ASIC Flow

The PLD Flow

3. Have No Idea What to Connect the PLD Pins to Chances Are, You Are Going to Get It Wrong!

EmbeddedFPGA Fabric

[Jonathan Rose]

What About PLDCores on ASICs ?

XputerLab

Whats Right with This Picture!


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1. Pre-Fabricated

2.One CAD Tool Flow!

3.Can Connect Anything to Anything PLDs are built for general connectivity

Embedded

CPU Serial Link,Analog, etc.

[Jonathan Rose]

XputerLab

>> Soft CPU


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p

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Configware Market

FPGA Market






Academic Expertise

ASICs dead

Soft CPU

HLLs Problems to be solved

XputerLab

Free 32 bit processor core


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XputerLab

Processors in PLDs: Excalibur


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High-Speed

ProcessorsIntegratedwith PLDs

ARM 922TCore

General PurposePLD

Dual-PortRAM

Single-PortRAM

[Jonathan Rose]

U i it f K i l t

XputerLab

Soft CPU: new job for compilers


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softCPU

FPGA

MemorycoreFPGA

CompilerHLL


XputerLab

Some soft CPU core examples


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Spartan-II16 bit DSPDSPuva16

FLEX10K30or EPF6016

i8080AMy80

32-bitgr1050

16-bitgr1040

Altera Mercury

8 bitNios

Altera22 D-MIPS

32-bitinstr. setNios50 MHz

Altera

Mercury

16-bitinstr. set

Nios

Xilinx up to

100 on oneFPGA

32 bit

standard RISC32 reg. by 32LUT RAM-based reg.

MicroBlaze

125 MHz 70D-MIPS

platformarchitecturecore

SpartanXLRISC integer Cxr16

old Xilinx FPGABoard

16-bit RISC,2 opd. Instr.

YARD-1A

1 Flex 10K20Acorn-1

Altera, Lattice,Xilinx

8 bit CISC1Popcorn-1

Lattice4 isp30256,4 isp1016

12 bit DSPReliance-1

2 XILINX3020 LCA

8 bits Instr. +ext. ROM

REGIS

200 XC4000ECLBs

CISC, 32 reg.uP1232 8-bit

ARMARM7 clone

SPARCLeon

25 Mhz

platformarchitecturecore


XputerLab

Nios Architecture (Altera)


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free DSP or Processor Cores


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VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

Mentor GraphicsVHDLanother i8051 clonei8051

Synopsys8-bit micro-controlleri8051

AMD 2910 bit sliceAMD 2910

AMD 2901 4-bit sliceAMD 2901

i8085 cloneGL85

Generic 32-bit RISC CPUDLX2

SynopsysGeneric 32-bit RISC CPUDLX

6502 compatible coreFree-6502

Xilinx XC4000A 16-bit Harvard DSP with5 pipeline stages.

16-bit DSP

Max2PlusII+ 1 Altera 10k20small 8 bit CISCAcorn 1

1 Lattice CPLD isp3256-90Verilogsmall 8 bit CISCPopCorn 1

Viewlogic 7 Lattice CPLDsSchematic12bit DSP and peripheralsReliance 1

ImplementationLanguageDescriptionCPU core


XputerLab

FPGA CPUs in teaching andacademic research


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academic research

UCSC: 1990! Mraldalen University,

Eskilstuna, Sweden Chalmers University,

Gteborg, Sweden Cornell University Gray Research Georgia Tech

Hiroshima CityUniversity, Japan

Michigan State Universidad de

Valladolid, Spain Virginia Tech

WashingtonUniversity, St. Louis New Mexico Tech UC Riverside

Tokai University,Japan


XputerLab

Xilinx 10Mg, 500Mt, .12 mic


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XputerLab

Soft rDPA feasible ?


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2001,[email protected] http://www.fpl.uni-kl.de68

[ la S. Guccione]


XputerLab

Array I/O examples


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data streams, or, from/toembedded memory banks

datastreams,

or,from/to

embedded

memorybanks

1

10

100

1000Performance

1980 1990 2000

Proc60%/yr..

DRAM7%/yr..

Processor-MemoryPerformance Gap:(grows 50% / year)

DRAM

CPU

[ la S. Guccione]


XputerLab

HLL 2 Soft Array


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Memorysoft CPU

miscellanous

HLL Compiler

[ la S. Guccione]


XputerLab

HLL 2 flex rDPA


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MemoryCPU

miscellanous

HLL Compiler

[ la S. Guccione]


XputerLab

>> HLLs


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Configware Market

FPGA Market Embedded Systems (Co-Design)





Academic Expertise

ASICs dead

Soft CPU



XputerLab

HLLs for Hardware Design vs.System Design vs. RTR System


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y g yDesign

HLL Compiler

System Design

CompilerHLL

RTR System Design[ la S. Guccione]


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y g yDesign

HLL Compiler

System Design

CompilerHLL

RTR System Design

CompilerHLL

[ la S. Guccione]


XputerLab

CPU and memory on Chip


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CPU

core

FPGA core

Memory

coreCompilerHLL

CompilerHLL

RTR System Design

[ la S. Guccione]


XputerLab

Jbit Environment


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RTP Core

Library

JRoute

API

DeviceSimulator

UserCode

BoardScope

Debugger

XHWIF

JBits

API

TCP/IP

[ la S. Guccione]


XputerLab



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Design

CompilerHLL

HLL Compiler

System Design

[ la S. Guccione]


XputerLab

Embedded System Design


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HLL Compiler

CPUcore

FPGA core

Memorycore

HLL Compiler

softCPU FPGA

MemorycoreFPGA

[ la S. Guccione]


XputerLab

>> Problems to be solved


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Configware Market

FPGA Market Embedded Systems (Co-Design)





Academic Expertise

ASICs dead

Soft CPU



XputerLab

Why Cant Reconfig. Software Survive?


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Resource constraints/sizes are exposed: to programmer

in low-level representation (netlist)

Design revolves around device size

Algorithmic structure Exploited parallelism


XputerLab

Schedule


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time slot

08.30 10.00 Reconfigurable Computing (RC)10.00 10.30 coffee break

10.30 12.00 Stream-based Computing for RC

12.00 14.00 lunch break14.00 15.30 Resources for RC

15.30 16.00 coffee break

16.00 17.30 FPGAs: recent developments

17.30 end of seminar: thank you for attending

Tampere 01 Course 4

Documents

Transcript of Tampere 01 Course 4