Software Defined Radio Hbk43

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Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: in [email protected] • http://www.pentek.com

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Software Defined Radio Handbook Eighth Edition

Pentek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 • Fax: (201) 818-5904Email: [email protected] • http ://www.pentek.com

Copyright © 1998, 2001, 2003, 2006, 2008, 2009, 2010 Pentek Inc.Last updated: January 2010

All right s reserv ed.Contents of this publication may not be reproduced in any form without written permission.

Specifications are subject to change without notice.Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.

Sampling

Principles of SDR

Technology

Products

Applications

Summary Links

by

Rodger H. Hosking Vice-President & Cofounder of Pentek, Inc.

®


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Software Defined Radio Handbook

Preface

SDR (Software Defined Radio) has revolutionized electronic systems for a variety of applications including communications, data acquisition and signal processing.

This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),the fundamental building blocks of SDR, can replace conventional analog receiver designs,

offering significant benefits in performance, density and cost.

In order to fully appreciate the benefits of SDR, a conventional analog receiver system will be compared to its digital receiver counterpart, highlighting similarities and differences

The inner workings of the SDR will be explored with an in-depth description of the internal structure and the devices used. Finally, some actual board- and system-level implementations and avail

off-the-shelf SDR products for embedded systems will be described.


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Before we look at SDR and its various implementa-tions in embedded systems, we’ll review a theoremfundamental to sampled data systems such as thoseencountered in software defined radios.

Nyquist’s Theorem:

“ Any signal can be represented by discrete samples if the sampling frequency is at least twice

the bandwidth of the signal.”

Notice that we highlighted the word bandwidthrather than frequency. In what follows, we’ll attempt toshow the implications of this theorem and the correctinterpretation of sampling frequency, also known assampling rate.

Sampling

A Simple Technique to Visualize Sampling

To visualize what happens in sampling, imaginethat you are using transparent “fan-fold” computerpaper. Use the horizontal edge of the paper as thefrequency axis and scale it so that the paper folds lineup with integer multiples of one-half of the sampling frequencyƒs. Each sheet of paper now represent what we

will call a “Nyquist Zone”, as shown in Figure 1.

Figure 1

Nyquist’s Theorem and Sampling

fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/20

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Frequency


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5


fs/20

Folded signalsstill fall on top of each other - but

now there isenergy in

only one sheet !

Undersampling

Figure 5

Sampling

Figure 6

fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/20

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

No Signal EnergyNo Signal Energy

Undersampling allows us to use aliasing to ouradvantage, providing we follow the strict rules of theNyquist Theorem.

In our previous IF signal example, suppose we try a sampling rate of 40 MHz.

Figure 5 shows a fan-fold paper plot with Fs = 40 MHz. You can see that zone 4 extends from 60 MHz to 80 MHz,nicely containing the entire IF signal band of 65 to 75 MHz.

Now when you collapse the fan fold sheets as shownin Figure 6, you can see that the IF signal is preservedafter sampling because we have no signal energy in any other zone.

Also note that the odd zones fold with the lowerfrequency at the left (normal spectrum) and the evenzones fold with the lower frequency at the right (reversedspectrum).

In this case, the signals from zone 4 are frequency reversed. This is usually very easy to accommodate inthe following stages of SDR systems.

Summary

Baseband sampling requires the sample frequency tobe at least twice the signal bandwidth. This is the sameas saying that all of the signals fall within the firstNyquist zone.

In real life, a good rule of thumb is to use the 80%relationship:

Bandwidth = 0.8 x ƒs/2

Undersampling allows a lower sample rate even thougsignal frequencies are high, PROVIDED all of thesignal energy falls within one Nyquist zone.

To repeat the Nyquist theorem: The sampling frequency must be at least twice the signal bandwidth — not thesignal frequency.

The major rule to follow for successful undersamplinis to make sure all of the energy falls entirely in oneNyquist zone.

There two ways to do this:1. Insert a bandpass filter to eliminate all signals

outside the one Nyquist zone.2. Increase the sampling frequency so all signals

fall entirely within one Nyquist zone.


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Figure 7

The conventional heterodyne radio receiver shownin Figure 7, has been in use for nearly a century. Let’sreview the structure of the analog receiver so comparisonto a digital receiver becomes apparent.

First the RF signal from the antenna is amplified,typically with a tuned RF stage that amplifies a regionof the frequency band of interest.

This amplified RF signal is then fed into a mixerstage. The other input to the mixer comes from the localoscillator whose frequency is determined by the tuning control of the radio.

The mixer translates the desired input signal to theIF (Intermediate Frequency) as shown in Figure 8.

The IF stage is a bandpass amplifier that only letsone signal or radio station through. Common centerfrequencies for IF stages are 455 kHz and 10.7 MHzfor commercial AM and FM broadcasts.

The demodulator recovers the original modulating signal from the IF output using one of several different

schemes.For example, AM uses an envelope detector and FM

uses a frequency discriminator. In a typical home radio,the demodulated output is fed to an audio poweramplifier which drives a speaker.

Figure 8

Analog Radio Receiver Block Diagram Analog Radio Receiver Mixer

The mixer performs an analog multiplication of thetwo inputs and generates a difference frequency signal.

The frequency of the local oscillator is set so thatthe difference between the local oscillator frequency anthe desired input signal (the radio station you want toreceive) equals the IF.

For example, if you wanted to receive an FMstation at 100.7 MHz and the IF is 10.7 MHz, you wouldtune the local oscillator to:

100.7 - 10.7 = 90 MHzThis is called “downconversion” or “translation”

because a signal at a high frequency is shifted down to lower frequency by the mixer.

The IF stage acts as a narrowband filter which onlypasses a “slice” of the translated RF input. The band-

width of the IF stage is equal to the bandwidth of thesignal (or the “radio station”) that you are trying toreceive.

For commercial FM, the bandwidth is about100 kHz and for AM it is about 5 kHz. This is consis-tent with channel spacings of 200 kHz and 10 kHz,respectively.

Principles of SDR

ANALOGLOCAL

OSCILLATOR

IFAMP(FILTER)

SPEAKER ANTENNA

DEMODULATOR(Detector)

ANALOGMIXER

AUDIO AMP

RF AMP

0

RF INPUT SIGNALFROM ANTENNAMIXER TRANSLATESINPUT SIGNAL BAND

to IF FREQUENCY

ANALOG LOCALOSCILLATOR

FRFF IF

Signal


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0 F SIG

MIXER TRANSLATESINPUT SIGNAL

BAND to DC

DIGITAL LOCALOSCILLATOR

FLO = FSIG

CHANNELBANDWIDTH

IF BWSignal

DIGITALMIXER

DIGITALLOCAL

OSC

DSP

DDCDigital Downconverter

RFTUNER

AnalogIF Signal

AnalogRF Signal A/D

CONV

Digital IFSamples LOWPASS

FILTER

DigitalBasebandSamples

SDR Receiver Block Diagram

Figure 9

Principles of SDR

Figure 10

SDR Receiver MixerFigure 9 shows a block diagram of a softwaredefined radio receiver. The RF tuner converts analog RFsignals to analog IF frequencies, the same as the first threestages of the analog receiver.

The A/D converter that follows digitizes the IF signalthereby converting it into digital samples. These samplesare fed to the next stage which is the digital downconverter(DDC) shown within the dotted lines.

The digital downconverter is typically a singlemonolithic chip or FPGA IP, and it is a key part of the

SDR system. A conventional DDC has three major sections:

• A digital mixer • A digital local oscillator • An FIR lowpass filter

The digital mixer and local oscillator translate thedigital IF samples down to baseband. The FIR lowpassfilter limits the signal bandwidth and acts as a decimat-ing lowpass filter. The digital downconverter includes a

lot of hardware multipliers, adders and shift registermemories to get the job done.

The digital baseband samples are then fed to a block labeled DSP which performs tasks such as demodulation,decoding and other processing tasks.

Traditionally, these needs have been handled withdedicated application specific ICs (ASICs), and program-mable DSPs.

At the output of the mixer, the high frequency wideband signals from the A/D input (shown in Figure10 above) have been translated down to DC as complex Iand Q components with a frequency shift equal to thelocal oscillator frequency.

This is similar to the analog receiver mixer exceptthere , the mixing was done down to an IF frequency.

Here , the complex representation of the signal allows uto go right down to DC.

By tuning the local oscillator over its range, any portion of the RF input signal can be mixed down to DC.

In effect, the wideband RF signal spectrum can be“slid” around 0 Hz, left and right, simply by tuning thelocal oscillator. Note that upper and lower sidebands arpreserved.


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DIGITALMIXER

DIGITALLOCAL

OSC

A/DCONV

Digital IFSamples LOWPASS

FILTER


Translat ion Fil tering

Tuning Freq Decimation

DDC Signal Processing

Figure 12

Principles of SDR

Figure 11A Local Oscillator Frequency Switching

DDC Local Oscillator and Decimation

F1 F2 F3

90 O

A/D Sample Rate(before decimation)

Sample Rate: Fs

DecimatedFilter Output

Sample Rate: Fs/N

Figure 11B FIR Filter Decimation

Because the local oscillator uses a digital phaseaccumulator, it has some very nice features. It switchesbetween frequencies with phase continuity, so you cangenerate FSK signals or sweeps very precisely with notransients as shown in Figure 11A.

The frequency accuracy and stability are determinedentirely by the A/D clock so it’s inherently synchronousto the sampling frequency. There is no aging, drift orcalibration since it’s implemented entirely with digital logic.

Since the output of the FIR filter is band limited, theNyquist theorem allows us to lower the sample rate. If

we are keeping only one out of every N samples, as shownin Figure 11B above, we have dropped the sampling rateby a factor of N.

This process is calleddecimationand it means keeping one out of every N signal samples. If the decimatedoutput sample rate is kept higher than twice the outputbandwidth, no information is lost.

The clear benefit is that decimated signals can beprocessed easier, can be transmitted at a lower rate, orstored in less memory. As a result, decimation candramatically reduce system costs!

As shown in Figure 12, the DDC performs twosignal processing operations:

1. Frequency translation with the tuning controlledby the local oscillator.

2. Lowpass filtering with the bandwidth controlledby the decimation setting.

We will next turn our attention to the SoftwareDefined Radio Transmitter.


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DUC Signal Processing

Figure 14

Principles of SDR

SDR Transmitter Block Diagram

Figure 13

The input to the transmit side of an SDR system isa digital baseband signal, typically generated by a DSPstage as shown in Figure 13 above.

The digital hardware block in the dotted lines is a DUC (digital upconverter) that translates the basebandsignal to the IF frequency.

The D/A converter that follows converts the digitalIF samples into the analog IF signal.

Next, the RF upconverter converts the analog IFsignal to RF frequencies.

Finally, the power amplifier boosts signal energy tothe antenna.

Inside the DUC shown in Figure 14, the digitalmixer and local oscillator at the right translate basebansamples up to the IF frequency. The IF translationfrequency is determined by the local oscillator.

The mixer generates one output sample for each ofits two input samples. And, the sample frequency atthe mixer output must be equal to the D/A sample

frequencyƒ

s.Therefore, the local oscillator sample rate and the

baseband sample rate must be equal to the D/A samplefrequencyƒs.

The local oscillator already operates at a sample raof ƒs, but the input baseband sample frequency at theleft is usually much lower. This problem is solved withthe Interpolation Filter.


Fs/N

DIGITALMIXER

DIGITALLOCAL

OSC

DUCDigital UpConverter

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs


AnalogIF

SignalD/ACONV

AnalogRF

SignalRFUpconverter

Power Amplifier DSP


Fs/N

DIGITALMIXER

DIGITALLOCAL

OSC

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs


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Interpolation Filter: Time domain

Figure 15 Figure 16

Interpolation Filter: Frequency Domain

Principles of SDR

INTERPOLATINGLOW PASSFIR FILTER

Fs/N

IQ

INTERPOLATIONFACTOR = N

BASEBANDINPUT

InterpolatingFilter OutputSample Rate: Fs

Baseband InputSample Rate: Fs/N

Fs

INTER-POLATEDOUTPUT

IQ

0 IF Freq

LOCALOSCILLATOR

F = IF Freq

MIXER

INTERPOLATEDBASEBAND INPUT TRANSLATED OUTPUT


Fs/NDIGITALMIXER

DIGITALLOCAL

OSC


INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs

The interpolation filter must boost the basebandinput sample frequency of ƒs/N up to the required mixer

input and D/A output sample frequency of ƒs.The interpolation filter increases the sample frequency

of the baseband input signal by a factor N, known asthe interpolation factor.

At the bottom of Figure 15, the effect of theinterpolation filter is shown in the time domain.

Notice the baseband signal frequency content iscompletely preserved by filling in additional samples inthe spaces between the original input samples.

The signal processing operation performed by theinterpolation filter is the inverse of the decimation filter

we discussed previously in the DDC section.

Figure 16 is a frequency domain view of the digitaupconversion process.

This is exactly the opposite of the frequency domaview of the DDC in Figure 10.

The local oscillator setting is set equal to therequired IF signal frequency, just as with the DDC.


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DIGITALMIXER

DIGITALLOCAL

OSC¸ N

A/DCONV

LOWPASSFILTER

Translation Filtering

DSP

Fs Fb

Tuning

Freq uency

Bandwidth

Deci mation

DIGITALMIXER

DIGITALLOCAL

OSC

´ N

INTERPOLATEFILTER

TranslationFiltering

D/ACONVDSP

Fb Fs

Tuning

Freq uencyInter polation

Bandwidth

DDC Processing DUC Processing

Figure 17 Figure 18

Principles of SDR

Figure 17 shows the two-step processing performedby the digital downconverter.

Frequency translation from IF down to baseband isperformed by the local oscillator and mixer.

The “tuning” knob represents the programmability of the local oscillator frequency to select the desiredsignal for downconversion to baseband.

The baseband signal bandwidth is set by setting decimation factor N and the lowpass FIR filter:

● Baseband sample frequencyƒb = ƒs/N

● Baseband bandwidth = 0.8 xƒbThe baseband bandwidth equation reflects a typical

80% passband characteristic, and complex (I+Q) samples.

The “bandwidth” knob represents the program-mability of the decimation factor to select the desiredbaseband signal bandwidth.

Figure 18 shows the two-step processing performedby the digital upconverter:

The ratio between the required output sample rateand the sample rate input baseband sample rate deter-mines the interpolation factor N.

● Baseband bandwidth = 0.8 xƒb● Output sample frequency ƒs = ƒb x N

Again, the bandwidth equation assumes a complex(I+Q) baseband input and an 80% filter.

The “bandwidth” knob represents the programma-bility of the interpolation factor to select the desiredinput baseband signal bandwidth.

Frequency translation from baseband up to IF isperformed by the local oscillator and mixer.

The “tuning” knob represents the programmability of the local oscillator frequency to select the desired IF

frequency for translation up from baseband.


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Key DDC and DUC Benefits SDR Tasks

Figure 19

Here we’ve ranked some of the popular signalprocessing tasks associated with SDR systems on a twoaxis graph, with compute Processing Intensity on thevertical axis and Flexibility on the horizontal axis.

What we mean by process intensity is the degree ofhighly-repetitive and rather primitive operations. At theupper left, are dedicated functions like A/D convertersand DDCs that require specialized hardware structuresto complete the operations in real time. ASICs are usuallychosen for these functions.

Flexibility pertains to the uniqueness or variabilityof the processing and how likely the function may haveto be changed or customized for any specific application

At the lower right are tasks like analysis and decisionmaking which are highly variable and often subjective.

Programmable general-purpose processors or DSPs

are usually chosen for these tasks since these tasks can easily changed by software.

Now let’s temporarily step away from the softwareradio tasks and take a deeper look at programmablelogic devices.

Figure 20

DIGITALMIXER

DIGITALLOCAL

OSC

A/DCONV

Digital IFSamples

Fs

LOWPASSFILTER


Fs/N


D/ACONV


Fs/N

DIGITALMIXER

DIGITAL

LOCALOSC

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs

DUCDigital Down

Converter

Think of the DDC as a hardware preprocessor forprogrammable DSP or GPP processor. It preselects only the signals you are interested in and removes all others.This provides an optimum bandwidth and minimumsampling rate into the processor.

The same applies to the DUC. The processor only needs to generate and deliver the baseband signalssampled at the baseband sample rate. The DUC thenboosts the sampling rate in the interpolation filter,performs digital frequency translation, and deliverssamples to the D/A at a very high sample rate.

The number of processors required in a system isdirectly proportional to the sampling frequency of input and output data. As a result, by reducing thesampling frequency, you can dramatically reduce thecost and complexity of the programmable DSPs orGPPs in your system.

Not only do DDCs and DUCs reduce the processor workload, the reduction of bandwidth and sampling ratehelps save time in data transfers to another subsystem. Thishelps minimize recording time and disk space, and reducestraffic and bandwidth across communication channels.

Principles of SDR


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Early Roles for FPGAs Legacy FPGA Design Methodologies

Figure 21 Figure 22

Technology

As true programmable gate functions becameavailable in the 1970’s, they were used extensively by hardware engineers to replace control logic, registers,gates, and state machines which otherwise would haverequired many discrete, dedicated ICs.

Often these programmable logic devices were one-time factory-programmed parts that were soldered downand never changed after the design went into production.

These programmable logic devices were mostly thedomain of hardware engineers and the software tools

were tailored to meet their needs. You had tools foraccepting boolean equations or even schematics to helpgenerate the interconnect pattern for the growing number of gates.

Then, programmable logic vendors started offeringpredefined logic blocks for flip-flops, registers andcounters that gave the engineer a leg up on popularhardware functions.

Nevertheless, the hardware engineer was stillintimately involved with testing and evaluating thedesign using the same skills he needed for testing discrete logic designs. He had to worry about propaga-tion delays, loading, clocking and synchronizing—alltricky problems that usually had to be solved the hard

way—with oscilloscopes or logic analyzers.

Used primarily to replace discrete digitalhardware circuitry for:

Control logic Glue logic Registers and gates State machines Counters and dividers

Devices were selected by hardware engineers Programmed functions were seldom changedafter the design went into production

Tools were oriented to hardware engineers Schematic processors Boolean processors Gates, registers, counters, multipliers

Successful designs required high-levelhardware engineering skills for:

Critical paths and propagation delays Pin assignment and pin locking Signal loading and drive capabilities Clock distribution Input signal synchronization and skew analysis


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FPGAs: New Device Technology FPGAs: New Development Tools

Figure 23 Figure 24

Technology

It’s virtually impossible to keep up to date on FPGA technology, since new advancements are being madeevery day.

The hottest features are processor cores inside thechip, computation clocks to 500 MHz and above, andlower core voltages to keep power and heat down.

About five years ago, dedicated hardware multipliersstarted appearing and now you’ll find literally hundredsof them on-chip as part of the DSP initiative launchedby virtually all FPGA vendors.

High memory densities coupled with very flexiblememory structures meet a wide range of data flow strategies. Logic slices with the equivalent of over tenmillion gates result from silicon geometries shrinking down to 0.1 micron.

BGA and flip-chip packages provide plenty of I/Opins to support on-board gigabit serial transceivers andother user-configurable system interfaces.

New announcements seem to be coming out every day from chip vendors like Xilinx and Altera in a never-ending game of outperforming the competition.

To support such powerful devices, new design toolsare appearing that now open up FPGAs to both hard-

ware and software engineers. Instead of just accepting logic equations and schematics, these new tools acceptentire block diagrams as well as VHDL and Verilog definitions.

Choosing the best FPGA vendor often hingesheavily on the quality of the design tools available tosupport the parts.

Excellent simulation and modeling tools help toquickly analyze worst case propagation delays andsuggest alternate routing strategies to minimize them

within the part. This minimizes some of the tricky timing work for hardware engineers and can save onehours of tedious troubleshooting during design verification and production testing.

In the last few years, a new industry of third party IP (Intellectual Property) core vendors now offerthousands of application-specific algorithms. These areready to drop into the FPGA design process to help beathe time-to-market crunch and to minimize risk.

500+ MHz DSP Slices and Memory Structures Over 1000 dedicated on-chip hardware multipliers On-board GHz Serial Transceivers Partial Reconfigurability MaintainsOperation During Changes

Switched Fabric Interface Engines Over 330,000 Logic Cells Gigabit Ethernet media access controllers On-chip 405 PowerPC RISC micro-controller cores Memory densities approaching 15 million bits Reduced power with core voltages at 1 volt Silicon geometries to 65 nanometers High-density BGA and flip-chip packaging

Over 1200 user I/O pins Configurable logic and I/O interface standards

High Level Design Tools Block Diagram System Generators Schematic Processors

High-level language compilers for VHDL & Verilog

Advanced simulation tools for modeling speed,propagation delays, skew and board layout

Faster compilers and simulators save time Graphically-oriented debugging tools

IP (Intellectual Property) Cores FPGA vendors offer both free and licensed cores FPGA vendors promote third party core vendors Wide range of IP cores available


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FPGAs for SDR FPGAs Bridge the SDR Application Space

Figure 25 Figure 26

Technology

As a result, FPGAs have significantly invaded theapplication task space as shown by the center bubble inthe task diagram above.

They offer the advantages of parallel hardware tohandle some of the high process-intensity functions likDDCs and the benefit of programmability to accommodate some of the decoding and analysis functions of DSPs

These advantages may come at the expense of increased power dissipation and increased product costHowever, these considerations are often secondary to thperformance and capabilities of these remarkable device

Like ASICs, all the logic elements in FPGAs canexecute in parallel. This includes the hardware multipli-ers, and you can now get over 1000 of them on a singleFPGA.

This is in sharp contrast to programmable DSPs, which normally have just a handful of multipliers thatmust be operated sequentially.

FPGA memory can now be configured with thedesign tool to implement just the right structure fortasks that include dual port RAM, FIFOs, shift registersand other popular memory types.

These memories can be distributed along the signalpath or interspersed with the multipliers and mathblocks, so that the whole signal processing task operatesin parallel in a systolic pipelined fashion.

Again, this is dramatically different from sequentialexecution and data fetches from external memory as in a programmable DSP.

As we said, FPGAs now have specialized serial andparallel interfaces to match requirements for high-speedperipherals and buses.

Parallel Processing Hardware Multipliers for DSP

FPGAs can now have over 500 hardware multipliers

Flexible Memory Structures Dual port RAM, FIFOs, shift registers, look up tables, etc.

Parallel and Pipelined Data Flow Systolic simultaneous data movement

Flexible I/O Supports a variety of devices, buses and interface standards

High Speed Available IP cores optimized for special functions


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ModelModel

FeatureFeature 7141-4307141-430 7141-4207141-420 7142-4287142-428 71517151 71527152 71537153

125 MHz125 MHzMax Sample RateMax Sample Rate 125 MHz125 MHz 125 MHz125 MHz 200 MHz200 MHz 200 MHz200 MHz 200 MHz200 MHz

14-Bit14-BitInput ResolutionInput Resolution 14-Bit14-Bit 14-Bit14-Bit 16-Bit16-Bit 16-Bit16-Bit 16-Bit16-Bit

11Input ChannelsInput Channels 22 44 44 44 44

256256DDC ChannelsDDC Channels 2 or 42 or 4 44 256256 3232 2 or 42 or 4

1K-10K1K-10KDecimation RangeDecimation Range Core: 2,4,8,16,32,64GC4016: 32to 16kCore: 2,4,8,16,32,64GC4016: 32to 16k

2 to 64KSteps of 12 to 64K

Steps of 1128 to 1024Steps of 64

128 to 1024Steps of 64



2 Ch: 2 to 655364 Ch: 2 to 256

2 Ch: 2 to 655364 Ch: 2 to 256

24*DEC/51224*DEC/512No. of Filter TapsNo. of Filter Taps Core: 28*DECCore: 28*DEC 28*DEC28*DEC 24*DEC/6424*DEC/64 28*DEC/828*DEC/8 28*DEC28*DEC

Normal I/QNormal I/QOutput FormatOutput Format I/Q, Offset,Inverse, RealI/Q, Offset,

Inverse, RealI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, InverseI/Q,

Offset, Inverse

16-Bit16-BitOutput ResolutionOutput Resolution 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit

32-bits - 0 to Fs32-bits - 0 to FsTuning FrequencyTuning Frequency 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs

--Phase OffsetPhase Offset 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg

32 bits32 bitsGain ControlGain Control 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits

NoneNoneDAC InterpolationDAC Interpolation 2 - 327682 - 32768 2 - 327682 - 32768 NoneNone NoneNone NoneNone

NoneNonePower MetersPower Meters NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneThresh DetectorsThresh Detectors NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneChannel SummersChannel Summers NoneNone NoneNone NoneNone 32 channels32 channels 2 or 4 channels2 or 4 channels

The above chart shows the salient characteristics forsome of Pentek’s SDR products with IP cores installedin their FPGAs. The chart provides information regard-ing the number of input channels, maximum sampling frequency of their A/Ds, and number of DDC channelsin each one. This information is followed by DDC

characteristics regarding the decimation range and availablesteps along with the output format and resolution.

Technology

Typical Pentek Products with Installed SDR IP Cores

Other information that’s specific to each core isincluded as well as an indication of the Models thatinclude an interpolation filter and output D/A. As shownin the chart, some of these Models include power metersthreshold detectors, and gain along with phase offsetcontrol for optimizing results in applications such as

direction-finding and beamforming. All the Models shown here are PMC or PMC/XMC

modules. These products are also available in PCI, cPCand PCIe formats as well.

Figure 27


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Technology

FPGA Resource Comparison

Figure 28

The above chart compares the available resources inthe four Xilinx FPGA families that are used in most of the Pentek products.

● Virtex-II Pro: VP50 and VP70● Virtex-4: FX, LX and SX ●

Virtex-5: FXT, LXT and SXT● Virtex-6: LXT and SXT

The Virtex-II family includes hardware multipliersthat support digital filters, averagers, demodulatorsand FFTs—a major benefit for software radio signalprocessing. The Virtex-II Pro family dramatically increased the number of hardware multipliers and alsoadded embedded PowerPC microcontrollers.

The Virtex-4 family is offered as three subfamiliesthat dramatically boost clock speeds and reduce powerdissipation over previous generations.

The Virtex-4 LX family delivers maximum logicand I/O pins while the SX family boasts of 512 DSPslices for maximum DSP performance. The FX family isa generous mix of all resources and is the only family tooffer RocketIO, PowerPC cores, and the newly addedgigabit Ethenet ports.

*Virtex-II Pro and Virtex-4 Slices actually require 2.25 Logic Cells; Virtex-5 and Virtex-6 Slices actually require 6.4 Logic Cells

Virtex-II Pro Virtex-4 Virtex-5 Virtex-6 VP50, VP70 FX, LX, SX FXT, LXT, SXT LXT, SXT

Logic Cells 53K–74K 41K–152K 46K–156K 128K–476K Slices* 24K–33K 18K–68K 7K–24K 20K–74K CLB Flip-Flops 47K–66K 49K–93K 150K–207K 160K–595K Block RAM (kb) 4,176–5,904 1,728–6,768 2,160–8,784 9,504–38,304DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48EDSP Slices 132–328 64–512 48–640 480–2,016Serial Gbit Transceivers – 0–20 12–16 20PCI Express Blocks – – – 2

SelectIO – 448–768 480–640 600

The Virtex-5 family LXT devices offer maximumlogic resources, gigabit serial transceivers, and Ethernemedia access controllers. The SXT devices push DSPcapabilities with all of the same extras as the LXT. TheFXT devices follow as the embedded system resource devic

The Virtex-5 devices offer lower power dissipationfaster clock speeds and enhanced logic slices. They alsoimprove the clocking features to handle faster memory and gigabit interfaces. They support faster single-endedand differential parallel I/O buses to handle fasterperipheral devices.

The Virtex-6 devices offer higher density, moreprocessing power, lower power consumption, andupdated interface features to match the latest technologyI/O requirements including PCI Express. Virtex-6supports PCI Express 2.0 in x1 through x8 configurations

The ample DSP slices are responsible for themajority of the processing power of the Virtex-6 familyIncreases in operating speed from 500 MHz in V-4 to550 MHz in V-5 to 600 MHz in V-6 and increasing density allows more DSP slices to be included in thesame-size package. As shown in the chart, Virtex-6 topout at an impressive 2016 DSP slices.


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18


PMC, PMC/XMC, CompactPCI, PCI, PCI Express and VMEbus Software Radio

The Pentek family of board-level software radioproducts is the most comprehensive in the industry.Most of these products are available in several formatsto satisfy a wide range of requirements.

In addition to their commercial versions, many software radio products are available in ruggedized andconduction-cooled versions.

All of the software radio products include input A/Dconverters. Some of these products are software radioreceivers in that they include only DDCs. Others aresoftware radio transceivers and they include DDCs as

well as DUCs with output D/A converters. These come with independent input and output clocks.

All Pentek software radio products include multiboardsynchronization that facilitates the design of multichannelsystems with synchronous clocking, gating and triggering

Pentek’s comprehensive software support includesthe ReadyFlow ® Board Support Package, the GateFlow ®FPGA Design Kit and high-performance factory-installed IP cores that expand the features and rangeof many Pentek software radio products. In addition,

Pentek software radio recording systems are supported with SystemFlow ® recording software that features a graphical user interface.

A complete listing of these products with activelinks to their datasheets on Pentek’s website is includedat the end of this handbook.

PMC/XMC Module

Products

Figure 29

CompactPCI Board

PCI Board

VMEbus Board Full-length PCI Express Board

Half-length PCI Express Board


19/53


19


Multiband Receivers

The unit supports the channel combining mode of the 4016s such that two or four individual 2.5 MHzchannels can be combined for output bandwidths of 5 MHz or 10 MHz, respectively.

The sampling clock can be sourced from an internal100 MHz crystal oscillator or from an external clock suppliedthrough an SMA connector or the LVDS clock/sync bus onthe front panel. The LVDS bus allows multiple modules to besynchronized with the same sample clock, gating, triggering and frequency switching signals. Up to 80 modules can besynchronized with the Model 9190 Clock and Sync Genera-

tor. Custom interfaces can be implemented by using the 64user-defined FPGA I/O pins on the P4 connector.

Versions of the 7131 are also available as a PCIboard (Model 7631A), 6U cPCI (Models 7231 and7231D dual density), or 3U cPCI (Model 7331). Allthese products have similar features.

Products

The Model 7131, a 16-Channel Multiband Receiver,is a PMC module. The 7131 PMC may be attached to a wide range of industry processor platforms equipped with PMC sites.

Two 14-bit 105 MHz A/D Converters accepttransformer-coupled RF inputs through two front panelSMA connectors. Both inputs are connected to fourTI/GC4016 quad DDC chips, so that all 16 DDCchannels can independently select either A/D.

Four parallel outputs from the four DDCs deliverdata into the Virtex-II FPGA which can be either the

XC2V1000 or XC2V3000. The outputs of the two A/Dconverters are also connected directly to the FPGA tosupport the DDC bypass path to the PCI bus and for directprocessing of the wideband A/D signals by the FPGA.

Model 7131 PMC ●●●●● Model 7231 6U cPCI ●●●●● Model 7331 3U cPCI ●●●●● Model 7631A PCI

Figure 30

Model 7231D 6U cPCI

Model 73313U cPCI

Model 7631A

PCI

Model 7131PMC


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20


Multiband Transceivers with Virtex-II Pro FPGA

Products

Figure 31

Model 7140 PMC/XMC●●●●●

Model 7240 6U cPCI●●●●●


Model 7640 PCI

Model 7140 PMC/XMC

The Model 7140 PMC module combines both

receive and transmit capability with a high-performanceVirtex II-Pro FPGA and supports the VITA 42 XMCstandard with optional switched fabric interfaces forhigh-speed I/O.

The front end of the module accepts two RF inputsand transformer-couples them into two 14-bit A/Dconverters running at 105 MHz. The digitized outputsignals pass to a Virtex-II Pro FPGA for signal process-ing or routing to other module resources.

These resources include a quad digital down-converter, a digital upconverter with dual D/A convert-ers, 512 MB DDR SDRAM delay memory and the PCIbus. The FPGA also serves as a control and statusengine with data and programming interfaces to each of the on-board resources. Factory-installed FPGA functionsinclude data multiplexing, channel selection, data packing,gating, triggering, and SDRAM memory control.

In addition to acting as a simple transceiver, the

module can perform user-defined DSP functions on thebaseband signals, developed using Pentek’s GateFlow and ReadyFlow development tools.

The module includes a TI/GC4016 quad digitaldownconverter along with a TI DAC5686 digitalupconverter with dual D/A converters.

Each channel in the downconverter can be set withan independent tuning frequency and bandwidth. Theupconverter translates a real or complex baseband signal tany IF center frequency from DC to 160 MHz and candeliver real or complex (I + Q) analog outputs throughits two 16-bit D/A converters. The digital upconvertercan be bypassed for two interpolated D/A outputs withsampling rates to 500 MHz.

Versions of the 7140 are also available as a PCIboard (Model 7640), 6U cPCI (Models 7240 and7240D dual density), or 3U cPCI (Model 7340). Allthese products have similar features.

VIRTEX-II Pro FPGAXC2VP50

DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.Control/Status

GC40164-CHANNEL

DIGITALRECEIVER

1616

1614

24

FLASH16 MB

16

DDRSDRAM256 MB

DDRSDRAM128 MB

DDRSDRAM128 MB

32 32 32

PCI 2.2 INTERFACE(64 Bits / 66 MHz)

PCI BUS(64 Bits / 66 MHz)

64

TIMING BUSGENERATORA

XTLOSCA

SYNCINTERRUPTS& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

SampleClock B In

SampleClockA In

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

Clock/Sync/GateBus A

Clock/Sync/GateBus B

ToAllSections

32

RF XFORMR RF XFORMR

RF Out RF Out

DAC5686DIGITAL UPCONVERTER

16-bi t D/A 16-bi t D/A

14

RFXFORMR

RFXFORMR

RF In RF In

14

AD6645105 MHz

14-bitA/D

AD6645105 MHz

14-bitA/D

P15 XMCVITA 42.0

(Serial RapidIO,PCI-Express, etc.)

P4 PMCFPGA I/O

(Option –104)

648X


21/53


22/53


22


Model 7140-430 PMC/XMC ●●●●● Model 7240-430 6U cPCIModel 7340-430 3U cPCI ●●●●● Model 7640-430 PCI

Transceivers with 256-Channel Narrowband DDC Installed Core

Products

Figure 33

For applications that require many channels of narrowband downconverters, Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank.Factory installed in the Model 7140 FPGA, Core 430creates a flexible, very high-channel count receiver systemin a small footprint.

Unlike classic channelizer methods, the Pentek 430core allows for completely independent programmabletuning of each individual channel with 32-bit resolutionas well as filter characteristics comparable to many conventional ASIC DDCs.

Added flexibility comes from programmable globaldecimation settings ranging from 1024 to 8192 in stepsof 256, and 18-bit user programmable FIR decimating filter coefficients for the DDCs. Default DDC filtercoefficient sets are included with the core for all possibledecimation settings.

Core 430 utilizes a unique method of channelization.It differs from others in that the channel center frequen-

cies need not be at fixed intervals, and are independentlprogrammable to any value.

Core 430 DDC comes factory installed in theModel 7140-430. A multiplexer in front of the coreallows data to be sourced from either A/D converter

A or B. At the output, a multiplexer allows the 7140-430 to route either the output of the GC4016 or theCore 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from both A/D channels are presented to the PCI Bus at a rateequal to the A/D clock rate divided by any integer valubetween 1 and 4096. A TI DAC5686 digital upconverterand dual D/A accepts baseband real or complex data streamfrom the PCI Bus with signal bandwidths up to 40 MHz.

Versions of the 7140-430 are also available as a PCboard (Model 7640-430), 6U cPCI (Models 7240-430and 7240D-430 dual density), or 3U cPCI (Model7340-430). All these products have similar features.

.

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

AD6645105 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX

GC4016 DIGITALDOWNCONVERTR

DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

PCI 2.2

INT

MEM WFIFO

MEM WFIFO

D/AAFIFO

D/A BFIFO

CH ARF In

CH BRF In

CH ARF Out

CH BRF Out

SampleClock A In

Clock/SyncBus

SampleClock B In

A B C D

A B C D

DDC 1Local Oscillator, Mixer, Filter

MUX

1

2

255

256

MUXMUX

DDC AFIFO

DDC BFIFO

DDC CFIFO

DDC DFIFO

OUT ADDC A

OUT BDDC B

OUT CDDC C

OUT DDDC D

PCI BUS64 bit /66 MHz

256 CHANNEL DIGITAL DOWNCONVERTER BANKCORE

XC2VP50

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

AD6645105 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX


DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

PCI 2.2

INTERFACE





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23


Multiband Transceivers with Virtex-II Pro FPGA

Products

Figure 34

Model 7141PMC/XMC

AD6645105 MHz

14-BIT A/D

AD6645105 MHz

14-BIT A/D

TIMING BUSGENERATOR A

XTLOSCA


TIMING BUS

GENERATOR B

XTL

OSC B

RFXFORMR

RFXFORMR

GC40164-CHANNEL

DIGITALRECEIVER

VIRTEX-II Pro FPGAXC2VP50

DSP – Channelizer– Digital Delay– Demodulation – Decoding– Control – etc.

FLASH16 MB

DDRSDRAM256 MB

DDRSDRAM128 MB

DDRSDRAM128 MB

PCI 2.2 INTERFACE(64 Bits / 66 MHz)

SampleClock B In

SampleClockA In

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

RF In RF In



ToAllSections Control/

Status


P15 XMCVITA42.0

(Serial RapidIO,PCI-Express, etc.)

P4 PMCFPGAI/O

(Option –104)

14 14

1616

1614

24

32

16

32 32 32 64 64

RF XFORMR RF XFORMR

RF Out RF Out

DAC5686DIGITAL UPCONVERTER

16-bit D/A 16-bit D/A

LTC2255125 MHz

14-bit A/D

LTC2255125 MHz

14-bit A/D

FRONTPANEL

CONNECTOR

The Model 7141 PMC/XMC module combines

both receive and transmit capabilities with a high-performance Virtex II-Pro FPGA and supports theVITA 42 XMC standard with optional switched fabricinterfaces for high-speed I/O.

The front end of the module accepts two RF inputsand transformer-couples them into two 14-bit A/Dconverters running at 125 MHz. The digitized outputsignals pass to a Virtex-II Pro FPGA for signal process-ing or routing to other module resources.

These resources include a quad digital down-converter, a digital upconverter with dual D/A converters,512 MB DDR SDRAM delay memory and the PCIbus. The FPGA also serves as a control and statusengine with data and programming interfaces to each of the on-board resources. Factory-installed FPGA functionsinclude data multiplexing, channel selection, data packing,gating, triggering, and SDRAM memory control.

In addition to acting as a simple transceiver, themodule can perform user-defined DSP functions on the

baseband signals, developed using Pentek’s GateFlow

and ReadyFlow development tools.The module includes a TI/GC4016 quad digital

downconverter along with a TI DAC5686 digitalupconverter with dual D/A converters.

Each channel in the downconverter can be set withan independent tuning frequency and bandwidth. Theupconverter translates a real or complex baseband signal tany IF center frequency from DC to 160 MHz and candeliver real or complex (I + Q) analog outputs throughits two 16-bit D/A converters. The digital upconvertercan be bypassed for two interpolated D/A outputs withsampling rates to 500 MHz.

Versions of the 7141 are also available as a PCIefull-length board (Models 7741 and 7741D dual density),PCIe half-length board (Model 7841), PCI board(Model 7641), 6U cPCI (Models 7241 and 7241Ddual density), and 3U cPCI (Model 7341).

Model 7141-703 is a conduction-cooled version.



Model 7341 3U cPCIModel 7641 PCI ●●●●● Model 7741 Full-length PCIe ●●●●● Model 7841 Half-length PCIe


24/53


24


Products

Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores

Figure 35

.

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

AD6645105 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX


DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

128 MB DDRSDRAM

128 MB DDRSDRAM

256 MB DDRSDRAM

PCI 2.2INTERFACE

MEMORYCONTROL

&DATA ROUTING

MEM WFIFO

MEM WFIFO

A/D AFIFO

A/D BFIFO

DDC A

FIFODDC BFIFO

DDC CFIFO

DDC DFIFO

D/AAFIFO

D/A BFIFO

MUX

MUX

CFIRFILTER

CICFILTER

MUX

WIDEBANDDIGITAL

DOWNCONVERTR ADECIMATION: 2 – 64

WIDEBANDDIGITAL

DOWNCONVERTR ADECIMATION: 2 – 64

MUX

MUX

MUX

CH ARF In

CH BRF In

CH ARF Out

CH BRF Out

SampleClock A In

Clock/SyncBus

Sample

Clock B In

A B C D

A B C D

MEMORYMEMORY

DDC CDDC DD/AAD/A B

A/D AA/D B

A/D AA/D BDDC ADDC B

A/D AA/D BDDC ADDC B

WB DDC A

DDC AWB DDC B

DDC B

MEMORYD/AA FIFOMEMORYD/A B FIFO


WIDEBAND DDC CORE

INTERPOLATION CORE

XC2VP50

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

LTC2255125 MHz

14-bit A/D

LTC2255125 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX


DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

128 MB DDRSDRAM

128 MB DDRSDRAM

256 MB DDRSDRAM

PCI 2.2INTERFACE

Model 7141-420 PMC/XMC ●●●●● Model 7241-420 6U cPCI ●●●●● Model 7341-420 3U cPCIModel 7641-420 PCI ●●●●● Model 7741-420 Full-length PCIe ●●●●● Model 7841-420 Half-length PCIe

The Pentek IP Core 420 includes a dual high-performance wideband DDC and an interpolation filter.Factory-installed in the Model 7141 FPGA, they extendthe range of both the GC4016 ASIC DDC and theDAC5686 DUC.

Each of the core 420 DDCs translates any frequency band within the input bandwidth range down to zerofrequency. A complex FIR low pass filter removes any out-of-band frequency components. An output decimator andformatter deliver either complex or real data. An input gainblock scales both I and Q data streams by a 16-bit gain

term.The mixer utilizes four 18x18-bit multipliers to

handle the complex inputs from the NCO and thecomplex data input samples. The FIR filter is capable of storing and utilizing up to four independent sets of 18-bit coefficients for each decimation value. Thesecoefficients are user-programmable by using RAMstructures within the FPGA.

The decimation settings of 2, 4, 8, 16, 32, and 64provide output bandwidths from 40 MHz down to 1.25MHz for an A/D sampling of 100 MHz. A multiplexerin front of the Core 420 DDCs allows data to be sourcedfrom either the A/Ds or the GC4016, extending themaximum cascaded decimation range to 1,048,576.

The interpolation filter included in the 420 Core,expands the interpolation factor from 2 to 32,768programmable in steps of 2, and relieves the hostprocessor from performing upsampling tasks. Includingthe DUC, the maximum interpolation factor is 32,768

which is comparable to the maximum decimation of theGC4016 narrowband DDC.

Versions of the 7141-420 are also available as a PCIefull-length board (Models 7741-420 and 7741D-420 dualdensity), PCIe half-length board (Model 7841-420), PCIboard (Model 7641-420), 6U cPCI (Models 7241-420 and7241D-420 dual density), or 3U cPCI (Model 7341-420).

Model 7141-703-420 is a conduction-cooled version.


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25


Transceivers with 256-Channel Narrowband DDC Installed Core

Products

Figure 36

.

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

AD6645105 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX


DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

PCI 2.2INT

MEM WFIFO

MEM WFIFO

D/AAFIFO

D/A BFIFO

CH ARF In

CH BRF In

CH ARF Out

CH BRF Out

SampleClock A In

Clock/SyncBus

Sample

Clock B In

A B C D

A B C D


MUX

1

2

255

256

MUXMUX

DDC AFIFO

DDC BFIFO

DDC CFIFO

DDC DFIFO

OUT ADDC A

OUT BDDC B

OUT CDDC C

OUT DDDC D


256 CHANNEL DIGITAL DOWNCONVERTER BANKCORE

XC2VP50

RFXFORMR

RFXFORMR

RFXFORMR

RFXFORMR

LTC2255125 MHz

14-bit A/D

LTC2255125 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

MUX


DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

16-bit500 MHZ

D/A

PCI 2.2INTERFACE



DDC 256

Local Oscillator, Mixer, Filter

Model 7141-430 PMC/XMC●●●●●

Model 7241-430 6U cPCI●●●●●

Model 7341-430 3U cPCIModel 7641-430 PCI ●●●●● Model 7741-430 Full-length PCIe ●●●●● Model 7841-430 Half-length PCIe

For applications that require many channels of narrowband downconverters, Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank.Factory installed in the Model 7141 FPGA, Core 430creates a flexible, very high-channel count receiversystem in a small footprint.

Unlike classic channelizer methods, the Pentek 430core allows for completely independent programmabletuning of each individual channel with 32-bit resolutionas well as filter characteristics comparable to many conventional ASIC DDCs.

Added flexibility comes from programmable globaldecimation settings ranging from 1024 to 8192 in stepsof 256, and 18-bit user programmable FIR decimating filter coefficients for the DDCs. Default DDC filtercoefficient sets are included with the core for all possibledecimation settings.

Core 430 utilizes a unique method of channelization.It differs from others in that the channel center frequen-

cies need not be at fixed intervals, and are independentlprogrammable to any value.

Core 430 DDC comes factory installed in the Model7141-430. A multiplexer in front of the core allows data to besourced from either A/D converter A or B. At the output, a multiplexer allows the 7141-430 to route either the output of the GC4016 or the Core 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from both A/D channels are presented to the PCI Bus at a rate equalto the A/D clock rate divided by any integer value betwee1 and 4096. A TI DAC5686 digital upconverter and dualD/A accepts baseband real or complex data streams fromthe PCI Bus with signal bandwidths up to 50 MHz.

Versions of the 7141-430 are also available as a PCIefull-length board (Models 7741-430 and 7741D-430 dualdensity), PCIe half-length board (Model 7841-430), PCIboard (Model 7641-430), 6U cPCI (Models 7241-430 and7241D-430 dual density), or 3U cPCI (Model 7341-430).Model 7141-703-430 is a conduction-cooled version.


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26


DDR 2SDRAM256 MB

DDR 2SDRAM256 MB

DDR 2SDRAM256 MB

32 32 32

32

RFXFORMR

RF Out

DAC5686DIGITAL

UPCONVERTER

16-bit D/A

RFXFORMR

LTC2255125MHz

14-bitA/D

RF In

14

RFXFORMR

LTC2255125MHz

14-bitA/D

RF In

14

RFXFORMR

LTC2255125MHz

14-bitA/D

RF In

14

RFXFORMR

LTC2255125MHz

14-bitA/D

RF In

14

P15 XMCVITA 42.0

P4 PMCFPGAI/O

(Option –104)

64

64 LOCALBUS

VIRTEX-4 FPGAXC4VFX60 or XC4VFX100


PCI 2.2INTERFACE

SERIALINTERFACE

32 32 32 HI-SPEEDBUSES

VIRTEX-4 FPGA

XC4VSX55DSP – Channelizer – Digital Delay– Demodulation – Decoding– Control – etc.

Control/Status

TIMING BUSGENERATOR A

XTLOSCA


TIMING BUS

GENERATOR B

XTL

OSC B

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B



ToAllSections

SampleClock In

Multichannel Transceivers with Virtex-4 FPGAs

Products

Model 7142 PMC/XMC

Figure 37




The Model 7142 is a Multichannel PMC/XMCmodule. It includes four 125 MHz 14-bit A/D convert-ers and one upconverter with a 500 MHz 16-bit D/A converter to support wideband receive and transmitcommunication channels.

Two Xilinx Virtex-4 FPGAs are included: an XC4VSX55 or LX100 and an XC4VFX60 or FX100.The first FPGA is used for control and signal processing functions, while the second one is used for implement-ing board interface functions including the XMC interface.

It also features 768 MB of SDRAM for implementing up to 2.0 sec of transient capture or digital delay memory for signal intelligence tracking applications at 125 MHz.

A 16 MB flash memory supports the boot code forthe two on-board IBM 405 PowerPC microcontrollercores within the FPGA.

A 9-channel DMA controller and 64 bit / 66 MHz PCIinterface assures efficient transfers to and from the module.

A high-performance 160 MHz IP core wideband digitadownconverter may be factory-installed in the first FPGA.

Two 4X switched serial ports, implemented with th Xilinx Rocket I/O interfaces, connect the second FPGAto the XMC connector with two 2.5 GB/sec data linksto the carrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichanneapplications where the relative phases must be preserve

Versions of the 7142 are also available as a PCIe fulllength board (Models 7742 and 7742D dual density),PCIe half-length board (Model 7842), PCI board(Model 7642), 6U cPCI (Models 7242 and 7242D dualdensity), and 3U cPCI (Model 7342).


27/53


27


Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores

Products

Figure 38

.

RFXFORMR

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

PCI 2.2INTERFACE

MEMORYCONTROL &

DATA ROUTING

D/AFIFO

MUXCFIRFILTER

CICFILTER

MUX

DIGITALDOWNCONVERTR A

STAGE 1DECIMATION: 2 – 256

CH ARF In

CH BRF In

RF Out

SampleClock In

Clock/SyncBus

A/D A

A/D AA/D B

A/D A

MEMORYD/A FIFO


DIGITAL DOWNCONVERTER CORE

INTERPOLATION CORE XC4VSX55

RFXFORMR

RFXFORMR

RFXFORMR

LTC2255125 MHz

14-bit A/D

CLOCK &SYNC

GENERATOR

XTALOSC A

XTALOSC B

DAC 5686DIGITAL

UPCONVERTER

16-bit500 MHZ

D/A

PCI 2.2INTERFACE

LTC2255125 MHz

14-bit A/D

RFXFORMR

CH CRF In

RFXFORMR

LTC2255125 MHz

14-bit A/D

RFXFORMR

CH DRF In

RFXFORMR

LTC2255125 MHz

14-bit A/D

A/D BA/D CA/D D

A/D CA/D D

DIGITALDOWNCONVERTR A


DIGITALDOWNCONVERTR B


A/D AA/D BA/D CA/D D

DIGITALDOWNCONVERTR B


DIGITALDOWNCONVERTR C


A/D AA/D BA/D C

A/D D

DIGITALDOWNCONVERTR C


DIGITALDOWNCONVERTR D



DIGITALDOWNCONVERTR D


DDC A

MUXA/D B

DDC B

MUXA/D C

DDC C

MUXA/D D

DDC D

D/A

MUX

MUX

MU

X

MUX

MEM WFIFO

MEM WFIFO

A/D AFIFO

A/D BFIFO

A/D CFIFO

A/D DFIFO

256 MB DDRSDRAM

256 MB DDRSDRAM

256 MB DDRSDRAM

Model 7142-428 PMC/XMC ●●●●● Model 7242-428 6U cPCI ●●●●● Model 7342-428 3U cPCIModel 7642-428 PCI ●●●●● Model 7742-428 Full-length PCIe ●●●●● Model 7742-428 Half-length PCIe

The Pentek IP Core 428 includes four high-performance multiband DDCs and an interpolationfilter. Factory-installed in the Model 7142 FPGA,they add DDCs to the Model 7142 and extend therange of its DAC5686 DUC.

The Core 428 downconverter translates any frequency band within the input bandwidth range down to zerofrequency. The DDCs consist of two cascaded decimat-ing FIR filters. The decimation of each DDC can be setindependently. After each filter stage is a post filter gainstage. This gain may be used to amplify small signalsafter out-of-band signals have been filtered out.

The NCO provides over 108 dB spurious-freedynamic range (SFDR). The FIR filter is capable of storing and utilizing two independent sets of 18-bitcoefficients. These coefficients are user-programmable by using RAM structures within the FPGA. NCO tuning frequency, decimation and filter coefficients can bechanged dynamically.

Four identical Core 428 DDCs are factory installedin the 7142-428 FPGA. An input multiplexer allowsany DDC to independently select any of the four A/Dsources. The overal decimation range from 2 to 65,536,programmable in steps of 1, provides output bandwidthsfrom 50 MHz down to 1.52 kHz for an A/D sampling rate of 125 MHz and assuming an 80% filter.

The Core 428 interpolation filter increases thesampling rate of real or complex baseband signals by afactor of 16 to 2048, programmable in steps of 4, andrelieves the host processor from performing upsamplintasks. The interpolation filter can be used in series withthe DUC’s built-in interpolation, creating a maximuminterpolation factor of 32,768.

Versions of the 7142-428 are also available as a PCIefull-length board (Models 7742-428 and 7742D-428 dualdensity), PCIe half-length board (Model 7842-428), PCIboard (Model 7642-428), 6U cPCI (Models 7242-428 and7242D-428 dual density), or 3U cPCI (Model 7342-428).


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256-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D

Products

Figure 39

.

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

PCI 2.2INTERFACE

MUXDIGITAL

DOWNCONVERTRBANK 1: CH 1 - 64

DECIMATION: 128 - 1024

CH ARF In

CH BRF In

SampleClock In

Sync Bus

A/D AA/D B

I & Q



XC5VSX95T

RFXFORMR

RFXFORMR

ADS5485200 MHz

16-bit A/D

TIMING BUSGENERATOR

Clock / Gate /Sync / PPS

XTALOSC

PCI 2.2INTERFACE

ADS5485200 MHz

16-bit A/D

RFXFORMR

CH CRF In

RFXFORMR

ADS5485200 MHz

16-bit A/D

RFXFORMR

CH DRF In

RFXFORMR

ADS5485200 MHz

16-bit A/D

A/D CA/D D

DDC BANK 1

MUX

MUX

MUX

MUX

MUX

MUX

MUX

A/D AFIFO

A/D BFIFO

A/D CFIFO

A/D DFIFO

PPS In

TTL In




DIGITALDOWNCONVERTR

BANK 2: CH 65 - 128DECIMATION: 128 - 1024

DIGITALDOWNCONVERTR


DIGITALDOWNCONVERTR


A/D BDDC BANK 2

A/D CDDC BANK 3

A/D DDDC BANK 4

I & Q

I & Q

I & Q

The Model 7151 PMC module is a 4-channel high-speed digitizer with a factory-installed 256-channelDDC core. The front end of the module accepts fourRF inputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7151 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical64-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as the

input source for each DDC bank. Each of the 256 DDCshas an independent 32-bit tuning frequency setting.

All of the 64 channels within a bank share a commondecimation setting that can range from 128 to 1024,programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidthsrange from 156.25 kHz to 1.25 MHz. Each 64-channelbank can have its own unique decimation setting

supporting as many as four different output bandwidthsfor the board.

The decimating filter for each DDC bank accepts aunique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8* ƒ s/N,

where N is the decimation setting. The rejection of adjacent-band components within the 80% output band-

width is better than 100 dB.

Each DDC delivers a complex output streamconsisting of 24-bit I + 24-bit Q samples. Any number

of channels can be enabled within each bank, selectablefrom 0 to 64. Each bank includes an output sampleinterleaver that delivers a channel-multiplexed stream foall enabled channels within the bank.

Versions of the 7151 are also available as a PCIefull-length board (Models 7751 and 7751D dual density),PCIe half-length board (Model 7851), PCI board(Model 7651), 6U cPCI (Models 7251 and 7251D dualdensity), or 3U cPCI (Model 7351).

Model 7151 PMC●●●●●




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32-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D

Products

Figure 40

.

RFXFORMR

RFXFORMR

AD6645105 MHz

14-bit A/D

PCI 2.2INTERFACE

MUXDIGITALDOWNCONVERTRBANK 1: CH 1 - 8DEC: 16 - 8192

CH ARF In

CH BRF In

SampleClock In

Sync Bus

A/DAA/D B

I & Q



XC5VSX95T

RFXFORMR

RFXFORMR

ADS5485200 MHz

16-bit A/D

TIMING BUSGENERATOR

Clock / Gate /Sync / PPS

XTALOSC

PCI 2.2INTERFACE

ADS5485200 MHz

16-bit A/D

RFXFORMR

CH CRF In

RFXFORMR

ADS5485200 MHz

16-bit A/D

RFXFORMR

CH DRF In

RFXFORMR

ADS5485200 MHz

16-bit A/D

A/D CA/D D

BANK 1

MUX

MUX

MUX

MUX

MUX

MUX

MUX

A/DAFIFO

A/D BFIFO

A/D CFIFO

A/D DFIFO

PPS In

TTL In

A/DAA/D BA/D CA/D D

A/DAA/D BA/D CA/D D

A/DAA/D BA/D CA/D D

DIGITALDOWNCONVERTRBANK 2: CH 9 - 16

DEC: 16 - 8192


DEC: 16 - 8192


DEC: 16 - 8192

A/D BBANK 2

A/D CBANK 3

A/D DBANK 4

8 x 4CHANNEL

SUMMATION

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

A/D B

I & Q

I & Q

I & Q

SUM

Model 7152 PMC●●●●●



The Model 7152 PMC module is a 4-channel high-speed digitizer with a factory-installed 32-channel DDCcore. The front end of the module accepts four RFinputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7152 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical8-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as the

input source for each DDC bank. Each of the 32 DDCshas an independent 32-bit tuning frequency setting.

All of the 8 channels within a bank share a commondecimation setting that can range from 16 to 8192,programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths rangefrom 19.53 kHz to 10.0 MHz. Each 8-channel bank can

have its own unique decimation setting supporting asmany as four different output bandwidths for the board

The decimating filter for each DDC bank accepts a uniqueset of user-supplied 18-bit coefficients. The 80% default filtersdeliver an output bandwidth of 0.8* ƒ s/N, where N is thedecimation setting. The rejection of adjacent-band components

within the 80% output band-width is better than 100 dB.

Each DDC delivers a complex output stream consist-ing of 24-bit I + 24-bit Q samples. Any number of channelscan be enabled within each bank, selectable from 0 to 8.

Each bank includes an output sample interleaver thatdelivers a channel-multiplexed stream for all enabledchannels within the bank. Gain and phase control, powermeters and threshold detectors are included.

Versions of the 7152 are also available as a PCIe fulllength board (Models 7752 and 7752D dual density), PCIehalf-length board (Model 7852), PCI board (Model 7652),6U cPCI (Models 7252 and 7252D dual density), or 3UcPCI (Model 7352).


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4-Channel Beamformer Installed Core with four 200 MHz, 16-bit A/Ds

Products

Figure 41

Model 7153 is a 4-channel, high-speed software radiomodule designed for processing baseband RF or IF signals.It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter)installed core and a complete set of beamforming functions.

With built-in multiboard synchronization and an Aurora gigabit serial interface, it provides everything needed forimplementing multichannel beamforming systems.

The Model 7153 employs an advanced FPGA-basedDDC engine consisting of four identical multiband banks.Four independently controllable input multiplexers select

one of the four A/Ds as the input source for each DDCbank. Each of the 4 DDCs has an independent 32-bittuning frequency setting.

All four DDCs have a decimation setting that canrange from 2 to 256, programmable independenly insteps of 1. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients.The 80% default filters deliver an output bandwidth of

0.8* ƒ s/N, where N is the decimation setting. Therejection of adjacent-band components within the 80%output band-width is better than 100 dB.

In addition to the DDCs, the 7153 features a com-plete beamforming subsystem. Each channel containsprogramable I & Q phase and gain adjustments followedby a power meter that continuously measures the individuaaverage power output. The time constant of the averaginginterval for each meter is programmable up to 8 ksamplesThe power meters present average power measurements foeach channel in easy-to-read registers. Each channel also

includes a threshold detector that sends an interrupt tothe processor if the average power level of any DDCfalls below or exceeds a programmable threshold.

Versions of the 7153 are also available as a PCIefull-length board (Models 7753 and 7753D dual density),PCIe half-length board (Model 7853), PCI board(Model 7653), 6U cPCI (Models 7253 and 7253Ddual density), or 3U cPCI (Model 7353).




DDC 1DEC: 2 - 256

Gain & Phase Adj

A/D AA/D B I & Q

PCI-XI/F

A/D CA/D D

MUX

200 MHz16-bit A/D

200 MHz16-bit A/D

200 MHz16-bit A/D

200 MHz16-bit A/D

CH BRF In

CH ARF In

CH DRF In

CH CRF In

SampleClock

Clock& SYNC

Bus

TimingClockSync

Gate /Trigger

PPS

XTALOSC

DDC 2DEC: 2 - 256

Gain & PhaseAdj

DDC 3DEC: 2 - 256

Gain & Phase Adj

DDC 4DEC: 2 - 256

Gain & Phase Adj

MUX

MU

X

MUX

MUX

A/D A


MU

X

A/D A

A/D BA/D CA/D D

MUX


MUX

PCI-XBus

64-bits100 MHz

I & Q

I & Q

I & Q

POWER METER& THRESHOLD

DETECTOR


DETECTOR


DETECTOR


DETECTOR

SUMMER


XC5VSX50T FPGA


A/D B

A/D C

A/D D

AuroraGigabitSerial

Interface

Sum In

Sum Out

P15XMC

4X

4X


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Products

Dual SDR Transceivers with 400 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs

Model 7156 PMC/XMC

RF In

14

ADS5474400 MHz14-bit A/D

RFXFORMR

RF In

14

ADS5474400 MHz

14-bit A/D

RFXFORMR

TIMING BUSGENERATOR

Clock/ Sync /Gate / PPS

Sample Clock In

TTL Gate / Trig

A/D Clock Bus

TTL Sync / PPS

Sample ClkSync Clk

Gate AGate B

Sync

PPS

PPS In

PROCESSING FPGAVIRTEX –5: LX50T, SX50T, SX95T or FX100TTo All

Sections

Control/Status

VCXOGTP GTP GTP

INTERFACE FPGAVIRTEX-5: LX30T, SX50T or FX70T

PCI-X BUS(64 Bits

100 MHz)

P15 XMCVITA 42.x

(PCIe, etc.)

P4 PMCFPGA

I/O

64

32

4X

4X

4X4X

GTP

PCI-X GTP

1632 32DDR 2SDRAM512 MB

DDR 2SDRAM512 MB

FLASH32 MB

32

LVDS

LVDS

Timing Bus

D/A Clock Bus

32

RFXFORMR

RFXFORMR

RF Out RF Out

DIGITAL UPCONVERTER

800 MHz16-bit D/A

800 MHz16-bit D/A

64

Model 7156 is a dual high-speed data convertersuitable for connection as the HF or IF input of a communications system. It features two 400 MHz 14-bit

A/Ds, a DUC with two 800 MHz 16-bit D/As, andtwo Virtex-5 FPGAs. Model 7156 uses the popularPMC format and supports the VITA 42 XMC standardfor switched fabric interfaces.

The Model 7156 architecture includes two Virtex-5FPGAs. The first FPGA is used primarily for signalprocessing while the second one is dedicated to boardinterfaces. All of the board’s data and control paths are

accessible by the FPGAs, enabling factory installedfunctions such as data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control.

Two independent 512 MB banks of DDR2 SDRAMare available to the signal processing FPGA. Built-inmemory functions include an A/D data transient capturemode with pre- and post-triggering. All memory bankscan be easily accessed through the PCI-X interface.

A high-performance IP core wideband DDC may befactory-installed in the processing FPGA.

A 5-channel DMA controller and 64 bit/100 MHz PCI- X interface assures efficient transfers to and from the modu

Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces, connect the FPGA to the XMC connector with two 2.5 GB/sec data links to thecarrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichanneapplications where the relative phases must be preserve

Versions of the 7156 are also available as a PCIe fulllength board (Models 7756 and 7756D dual density),PCIe half-length board (Model 7856), PCI board(Model 7656), 6U cPCI (Models 7256 and 7256D dualdensity), or 3U cPCI (Model 7356). All these productshave similar features.

Figure 42





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Model 7158 is a dual high-speed data convertersuitable for connection as the HF or IF input of a communications system. It features two 500 MHz 12-bit

A/Ds, a digital upconverter with two 800 MHz 16-bitD/As, and two Virtex-5 FPGAs. Model 7158 uses thepopular PMC format and supports the VITA 42 XMCstandard for switched fabric interfaces.

The Model 7158 architecture includes two Virtex-5FPGAs. The first FPGA is used primarily for signalprocessing while the second one is dedicated to boardinterfaces. All of the board’s data and control paths are

accessible by the FPGAs, enabling factory installedfunctions such as data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control.

Two independent 256 MB banks of DDR2 SDRAMare available to the signal processing FPGA. Built-inmemory functions include an A/D data transient capturemode with pre- and post-triggering. All memory bankscan be easily accessed through the PCI-X interface.

A 5-channel DMA controller and 64 bit / 100 MHzPCI-X interface assures efficient transfers to and from themodule.

Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces, connect the FPGA to the XMC connector with two 2.5 GB/sec data links to thecarrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichanne

applications where the relative phases must be preserveVersions of the 7158 are also available as a PCIe full

length board (Models 7758 and 7758D dual density),PCIe half-length board (Model 7858), PCI board(Model 7658), 6U cPCI (Models 7258 and 7258D dualdensity), or 3U cPCI (Model 7358). All these productshave similar features.

Dual SDR Transceivers with 500 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs




Figure 43

Products

Model 7158 PMC/XMC

RF In

14

ADS5463500 MHz12-bitA/D

RFXFORMR

RF In

14

ADS5463500 MHz

12-bitA/D

RFXFORMR

TIMING BUSGENERATOR

Clock/ Sync /Gate / PPS

Sample Clock /Reference Clock In

TTL Gate / Trig

A/D Clock Bus

TTL Sync / PPS

Sample ClkSync Clk

Gate AGate B

SyncPPS

PPS In

PROCESSING FPGA

VIRTEX –5: LX50T, LX155T, SX50T, SX95T or FX100TToAllSections

Control/Status

VCXOGTP GTP GTP

INTERFACE FPGAVIRTEX-5: LX30T, SX50T or FX70T

PCI-X BUS(64 Bits

100 MHz)

P15 XMCVITA 42.x

(PCIe, etc.)

P4 PMCFPGA

I/O

64

32

4X

4X

4X4X

GTP

PCI-X GTP

1632 32DDR 2SDRAM256 MB

DDR 2SDRAM256 MB

FLASH32 MB

32

LVDS

LVDS

Timing Bus

D/AClock Bus

32

RFXFORMR

RFXFORMR

RF Out RF Out

DIGITAL UPCONVERTER

800 MHz16-bit D/A

800 MHz16-bit D/A

64


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3-C

Software Defined Radio Hbk43

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