Software Defined Radio Handbook

PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: [email protected] • http://www.pentek.com

11111

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PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 • Fax: (201) 818-5904Email: [email protected] • http://www.pentek.com

Copyright © 1998, 2001, 2003, 2006, 2008, 2009, 2010, 2011, 2012 Pentek, Inc.Last updated: April 2012

All rights reserved.Contents of this publication may not be reproduced in any form without written permission.

Specifications are subject to change without notice.Pentek, GateFlow, ReadyFow, SystemFlow and Cobalt are registered trademarks of Pentek, Inc.

SamplingSamplingSamplingSamplingSampling

PPPPPrinciples of SDRrinciples of SDRrinciples of SDRrinciples of SDRrinciples of SDR

TTTTTechnologyechnologyechnologyechnologyechnology

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ApplicationsApplicationsApplicationsApplicationsApplications

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by

RRRRRodger Hodger Hodger Hodger Hodger H. Hosking. Hosking. Hosking. Hosking. HoskingVice-President & Cofounder of Pentek, Inc.

®


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Software Defined Radio Handbook

Preface

SDR (Software Defined Radio) has revolutionized electronic systems for avariety of applications including communications, data acquisition and signal processing.

This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),the fundamental building blocks of SDR, can replace legacy analog receiver designs while

offering significant benefits in performance, density and cost.

In order to fully appreciate the benefits of SDR, a conventional analog receiversystem will be compared to its digital receiver counterpart, highlighting similarities and differences.

The inner workings of the SDR will be explored with an in-depth description of the internalstructure and the devices used. Finally, some actual board- and system-level implementations and available

off-the-shelf SDR products and applications based on such products will be presented.

For more information on complementary subjects, the reader is referred to these Pentek Handbooks:Putting FPGAs to Work in Software Radio Systems

Critical Techniques for High-Speed A/D Converters in Real-Time SystemsHigh-Speed Switched Serial Fabrics Improve System Design

High-Speed, Real-Time Recording Systems


33333


Before we look at SDR and its various implementa-tions in embedded systems, we’ll review a theoremfundamental to sampled data systems such as thoseencountered in software defined radios.

Nyquist’s Theorem:

“Any signal can be represented by discretesamples if the sampling frequency is at least twice

the bandwidth of the signal.”

Notice that we highlighted the word bandwidthrather than frequency. In what follows, we’ll attempt toshow the implications of this theorem and the correctinterpretation of sampling frequency, also known assampling rate.


A Simple TA Simple TA Simple TA Simple TA Simple Technique to Visualize Samplingechnique to Visualize Samplingechnique to Visualize Samplingechnique to Visualize Samplingechnique to Visualize Sampling

To visualize what happens in sampling, imaginethat you are using transparent “fan-fold” computerpaper. Use the horizontal edge of the paper as thefrequency axis and scale it so that the paper folds lineup with integer multiples of one-half of the samplingfrequency ƒs. Each sheet of paper now represent what wewill call a “Nyquist Zone”, as shown in Figure 1.

Figure 1

Nyquist’s Theorem and SamplingNyquist’s Theorem and SamplingNyquist’s Theorem and SamplingNyquist’s Theorem and SamplingNyquist’s Theorem and Sampling

fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/20

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Frequency


44444



Figure 3

Baseband SamplingBaseband SamplingBaseband SamplingBaseband SamplingBaseband Sampling

Figure 4

A baseband signal has frequency components thatstart at ƒ = 0 and extend up to some maximum frequency.

To prevent data destruction when sampling a basebandsignal, make sure that all the signal energy falls ONY inthe 1st Nyquist band, as shown in Figure 4.

There are two ways to do this:1. Insert a lowpass filter to eliminate all signals

above ƒs/2, or2. Increase the sampling frequency so all signals

present fall below ƒs/2.

Note that ƒs/2 is also known as the “folding frequency”.

Sampling Bandpass SignalsSampling Bandpass SignalsSampling Bandpass SignalsSampling Bandpass SignalsSampling Bandpass Signals

Figure 2

Use the vertical axis of the fan-fold paper for signalenergy and plot the frequency spectrum of the signal tobe sampled, as shown in Figure 2. To see the effects ofsampling, collapse the transparent fan-fold paper into astack.

Sampling BasicsSampling BasicsSampling BasicsSampling BasicsSampling Basics

The resulting spectrum can be seen by holding thetransparent stack up to a light and looking through it.You can see that signals on all of the sheets or zones are“folded” or “aliased” on top of each other — and theycan no longer be separated.

Once this folding or aliasing occurs during sampling,the resulting sampled data is corrupted and can never berecovered. The term “aliasing” is appropriate becauseafter sampling, a signal from one of the higher zonesnow appears to be at a different frequency.

Let’s consider bandpass signals like the IF frequencyof a communications receiver that might have a 70 MHzcenter frequency and 10 MHz bandwidth. In this case,the IF signal contains signal energery from 65 to 75 MHz.

If we follow the baseband sampling rules above, wemust sample this signal at twice the highest signalfrequency, meaning a sample rate of at least 150 MHz.

However, by taking advantage of a technique called“undersampling”, we can use a much lower sampling rate.



En

erg

y



No Signal Energy

fs/20Folded Signals

Fall On Top of

Each Other


55555


fs/20

Folded signals

still fall on top of

each other - but

now there is

energy in

only one sheet !

UndersamplingUndersamplingUndersamplingUndersamplingUndersampling

Figure 5


Figure 6



No Signal EnergyNo Signal Energy

Undersampling allows us to use aliasing to ouradvantage, providing we follow the strict rules of theNyquist Theorem.

In our previous IF signal example, suppose we try asampling rate of 40 MHz.

Figure 5 shows a fan-fold paper plot with Fs = 40 MHz.You can see that zone 4 extends from 60 MHz to 80 MHz,nicely containing the entire IF signal band of 65 to 75 MHz.

Now when you collapse the fan fold sheets as shownin Figure 6, you can see that the IF signal is preservedafter sampling because we have no signal energy in anyother zone.

Also note that the odd zones fold with the lowerfrequency at the left (normal spectrum) and the evenzones fold with the lower frequency at the right (reversedspectrum).

In this case, the signals from zone 4 are frequencyreversed. This is usually very easy to accommodate inthe following stages of SDR systems.


Baseband sampling requires the sample frequency tobe at least twice the signal bandwidth. This is the sameas saying that all of the signals fall within the firstNyquist zone.

In real life, a good rule of thumb is to use the 80%relationship:

Bandwidth = 0.8 x ƒs/2

Undersampling allows a lower sample rate even thoughsignal frequencies are high, PROVIDED all of thesignal energy falls within one Nyquist zone.

To repeat the Nyquist theorem: The sampling frequencymust be at least twice the signal bandwidth — not thesignal frequency.

The major rule to follow for successful undersamplingis to make sure all of the energy falls entirely in oneNyquist zone.

There two ways to do this:1. Insert a bandpass filter to eliminate all signals

outside the one Nyquist zone.2. Increase the sampling frequency so all signals

fall entirely within one Nyquist zone.


66666


Figure 7

The conventional heterodyne radio receiver shownin Figure 7, has been in use for nearly a century. Let’sreview the structure of the analog receiver so comparisonto a digital receiver becomes apparent.

First the RF signal from the antenna is amplified,typically with a tuned RF stage that amplifies a regionof the frequency band of interest.

This amplified RF signal is then fed into a mixerstage. The other input to the mixer comes from the localoscillator whose frequency is determined by the tuningcontrol of the radio.

The mixer translates the desired input signal to theIF (Intermediate Frequency) as shown in Figure 8.

The IF stage is a bandpass amplifier that only letsone signal or radio station through. Common centerfrequencies for IF stages are 455 kHz and 10.7 MHzfor commercial AM and FM broadcasts.

The demodulator recovers the original modulatingsignal from the IF output using one of several differentschemes.

For example, AM uses an envelope detector and FMuses a frequency discriminator. In a typical home radio,the demodulated output is fed to an audio poweramplifier which drives a speaker.

Figure 8

Analog RAnalog RAnalog RAnalog RAnalog Radio Radio Radio Radio Radio Receiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagram Analog RAnalog RAnalog RAnalog RAnalog Radio Radio Radio Radio Radio Receiver Mixereceiver Mixereceiver Mixereceiver Mixereceiver Mixer

The mixer performs an analog multiplication of thetwo inputs and generates a difference frequency signal.

The frequency of the local oscillator is set so thatthe difference between the local oscillator frequency andthe desired input signal (the radio station you want toreceive) equals the IF.

For example, if you wanted to receive an FMstation at 100.7 MHz and the IF is 10.7 MHz, you wouldtune the local oscillator to:

100.7 - 10.7 = 90 MHz

This is called “downconversion” or “translation”because a signal at a high frequency is shifted down to alower frequency by the mixer.

The IF stage acts as a narrowband filter which onlypasses a “slice” of the translated RF input. The band-width of the IF stage is equal to the bandwidth of thesignal (or the “radio station”) that you are trying toreceive.

For commercial FM, the bandwidth is about100 kHz and for AM it is about 5 kHz. This is consis-tent with channel spacings of 200 kHz and 10 kHz,respectively.


ANALOG

LOCAL

OSCILLATOR

IF AMP

(FILTER)

SPEAKER

ANTENNA

DEMODULATOR

(Detector)

ANALOG

MIXER

AUDIO

AMP

RF

AMP

0

RF INPUT SIGNAL

FROM ANTENNA

MIXER TRANSLATES

INPUT SIGNAL BAND

to IF FREQUENCY

ANALOG LOCAL

OSCILLATOR

FRFFIF

Signal


77777


0 FSIG

MIXER TRANSLATES

INPUT SIGNAL

BAND to DC

DIGITAL LOCAL

OSCILLATOR

FLO = FSIG

CHANNEL

BANDWIDTH

IF BWSignal

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

DSP

DDC

Digital Downconverter

RF

TUNER

Analog

IF Signal

Analog

RF SignalA/D

CONV

Digital IF

Samples LOWPASS

FILTER

Digital

Baseband

Samples

SDR RSDR RSDR RSDR RSDR Receiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagrameceiver Block Diagram

Figure 9


Figure 10

SDR RSDR RSDR RSDR RSDR Receiver Mixereceiver Mixereceiver Mixereceiver Mixereceiver MixerFigure 9 shows a block diagram of a softwaredefined radio receiver. The RF tuner converts analog RFsignals to analog IF frequencies, the same as the first threestages of the analog receiver.

The A/D converter that follows digitizes the IF signalthereby converting it into digital samples. These samplesare fed to the next stage which is the digital downconverter(DDC) shown within the dotted lines.

The digital downconverter is typically a singlemonolithic chip or FPGA IP, and it is a key part of theSDR system.

A conventional DDC has three major sections:

• A digital mixer

• A digital local oscillator

• An FIR lowpass filter

The digital mixer and local oscillator translate thedigital IF samples down to baseband. The FIR lowpassfilter limits the signal bandwidth and acts as a decimat-ing lowpass filter. The digital downconverter includes alot of hardware multipliers, adders and shift registermemories to get the job done.

The digital baseband samples are then fed to a blocklabeled DSP which performs tasks such as demodulation,decoding and other processing tasks.

Traditionally, these needs have been handled withdedicated application specific ICs (ASICs), and program-mable DSPs.

At the output of the mixer, the high frequencywideband signals from the A/D input (shown in Figure10 above) have been translated down to DC as complex Iand Q components with a frequency shift equal to thelocal oscillator frequency.

This is similar to the analog receiver mixer exceptthere, the mixing was done down to an IF frequency.Here, the complex representation of the signal allows usto go right down to DC.

By tuning the local oscillator over its range, anyportion of the RF input signal can be mixed down to DC.

In effect, the wideband RF signal spectrum can be“slid” around 0 Hz, left and right, simply by tuning thelocal oscillator. Note that upper and lower sidebands arepreserved.


88888


DIGITAL

MIXER

DIGITAL

LOCAL

OSC

A/D

CONV

Digital IF

SamplesLOWPASS

FILTER

Digital

Baseband

Samples

Translation Filtering

Tuning Freq Decimation

DDC Signal PDDC Signal PDDC Signal PDDC Signal PDDC Signal Processingrocessingrocessingrocessingrocessing

Figure 12


Figure 11A Local Oscillator Frequency Switching

DDC LDDC LDDC LDDC LDDC Local Oscillator and Decimationocal Oscillator and Decimationocal Oscillator and Decimationocal Oscillator and Decimationocal Oscillator and Decimation

F1 F2 F3

90O

A/D Sample Rate(before decimation)

Sample Rate: Fs

Decimated

Filter OutputSample Rate: Fs/N

Figure 11B FIR Filter Decimation

Because the local oscillator uses a digital phaseaccumulator, it has some very nice features. It switchesbetween frequencies with phase continuity, so you cangenerate FSK signals or sweeps very precisely with notransients as shown in Figure 11A.

The frequency accuracy and stability are determinedentirely by the A/D clock so it’s inherently synchronousto the sampling frequency. There is no aging, drift orcalibration since it’s implemented entirely with digital logic.

Since the output of the FIR filter is band limited, theNyquist theorem allows us to lower the sample rate. Ifwe are keeping only one out of every N samples, as shownin Figure 11B above, we have dropped the sampling rateby a factor of N.

This process is called decimation and it means keepingone out of every N signal samples. If the decimatedoutput sample rate is kept higher than twice the outputbandwidth, no information is lost.

The clear benefit is that decimated signals can beprocessed easier, can be transmitted at a lower rate, orstored in less memory. As a result, decimation candramatically reduce system costs!

As shown in Figure 12, the DDC performs twosignal processing operations:

1. Frequency translation with the tuning controlledby the local oscillator.

2. Lowpass filtering with the bandwidth controlledby the decimation setting.

We will next turn our attention to the SoftwareDefined Radio Transmitter.


99999


DUC Signal PDUC Signal PDUC Signal PDUC Signal PDUC Signal Processingrocessingrocessingrocessingrocessing

Figure 14


SDR TSDR TSDR TSDR TSDR Transmitter Block Diagramransmitter Block Diagramransmitter Block Diagramransmitter Block Diagramransmitter Block Diagram

Figure 13

The input to the transmit side of an SDR system isa digital baseband signal, typically generated by a DSPstage as shown in Figure 13 above.

The digital hardware block in the dotted lines is aDUC (digital upconverter) that translates the basebandsignal to the IF frequency.

The D/A converter that follows converts the digitalIF samples into the analog IF signal.

Next, the RF upconverter converts the analog IFsignal to RF frequencies.

Finally, the power amplifier boosts signal energy tothe antenna.

Inside the DUC shown in Figure 14, the digitalmixer and local oscillator at the right translate basebandsamples up to the IF frequency. The IF translationfrequency is determined by the local oscillator.

The mixer generates one output sample for each ofits two input samples. And, the sample frequency atthe mixer output must be equal to the D/A samplefrequency ƒs.

Therefore, the local oscillator sample rate and thebaseband sample rate must be equal to the D/A samplefrequency ƒs.

The local oscillator already operates at a sample rateof ƒs, but the input baseband sample frequency at theleft is usually much lower. This problem is solved withthe Interpolation Filter.

Digital

Baseband

Samples

Fs/N

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

DUC

Digital Up

Converter

INTERPOLATION

FILTER

Digital IF

Samples

Fs

Digital

Baseband

Samples

Fs

DUC

Digital Up

Converter

Analog

IF

SignalD/A

CONV

Analog

RF

SignalRF

Upconverter

Power

AmplifierDSP

Digital

Baseband

Samples

Fs/N

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

INTERPOLATION

FILTER

Digital IF

Samples

Fs

Digital

Baseband

Samples

Fs


1010101010


Interpolation FInterpolation FInterpolation FInterpolation FInterpolation Filter: Time domainilter: Time domainilter: Time domainilter: Time domainilter: Time domain

Figure 15 Figure 16

Interpolation FInterpolation FInterpolation FInterpolation FInterpolation Filter: Filter: Filter: Filter: Filter: Frequency Domainrequency Domainrequency Domainrequency Domainrequency Domain


INTERPOLATING

LOW PASS

FIR FILTER

Fs/N

I

Q

INTERPOLATION

FACTOR = N

BASEBAND

INPUT

Interpolating

Filter OutputSample Rate: Fs

Baseband InputSample Rate: Fs/N

Fs

INTER-

POLATED

OUTPUT

I

Q

0 IF Freq

LOCAL

OSCILLATOR

F = IF Freq

MIXER

INTERPOLATED

BASEBAND INPUT TRANSLATED OUTPUT

Digital

Baseband

Samples

Fs/N

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

DUC

Digital Up

Converter

INTERPOLATION

FILTER

Digital IF

Samples

Fs

Digital

Baseband

Samples

Fs

The interpolation filter must boost the basebandinput sample frequency of ƒs/N up to the required mixerinput and D/A output sample frequency of ƒs.

The interpolation filter increases the sample frequencyof the baseband input signal by a factor N, known asthe interpolation factor.

At the bottom of Figure 15, the effect of theinterpolation filter is shown in the time domain.

Notice the baseband signal frequency content iscompletely preserved by filling in additional samples inthe spaces between the original input samples.

The signal processing operation performed by theinterpolation filter is the inverse of the decimation filterwe discussed previously in the DDC section.

Figure 16 is a frequency domain view of the digitalupconversion process.

This is exactly the opposite of the frequency domainview of the DDC in Figure 10.

The local oscillator setting is set equal to therequired IF signal frequency, just as with the DDC.


1111111111


DIGITAL

MIXER

DIGITAL

LOCAL

OSC

¸ N

A/D

CONVLOWPASS

FILTER

Translation Filtering

DSP

Fs Fb

Tuning

Freq uency

Bandwidth

Deci mation

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

´ N

INTERPOLATE

FILTER

TranslationFiltering

D/A

CONVDSP

Fb Fs

Tuning

Freq uencyInter polation

Bandwidth

DDC PDDC PDDC PDDC PDDC Processingrocessingrocessingrocessingrocessing DUC PDUC PDUC PDUC PDUC Processingrocessingrocessingrocessingrocessing

Figure 17 Figure 18


Figure 17 shows the two-step processing performedby the digital downconverter.

Frequency translation from IF down to baseband isperformed by the local oscillator and mixer.

The “tuning” knob represents the programmabilityof the local oscillator frequency to select the desiredsignal for downconversion to baseband.

The baseband signal bandwidth is set by settingdecimation factor N and the lowpass FIR filter:

● Baseband sample frequency ƒb = ƒs/N

● Baseband bandwidth = 0.8 x ƒb

The baseband bandwidth equation reflects a typical80% passband characteristic, and complex (I+Q) samples.

The “bandwidth” knob represents the program-mability of the decimation factor to select the desiredbaseband signal bandwidth.

Figure 18 shows the two-step processing performedby the digital upconverter:

The ratio between the required output sample rateand the sample rate input baseband sample rate deter-mines the interpolation factor N.

● Baseband bandwidth = 0.8 x ƒb

● Output sample frequency ƒs = ƒb x N

Again, the bandwidth equation assumes a complex(I+Q) baseband input and an 80% filter.

The “bandwidth” knob represents the programma-bility of the interpolation factor to select the desiredinput baseband signal bandwidth.

Frequency translation from baseband up to IF isperformed by the local oscillator and mixer.

The “tuning” knob represents the programmabilityof the local oscillator frequency to select the desired IFfrequency for translation up from baseband.


1212121212


KKKKKey DDC and DUCey DDC and DUCey DDC and DUCey DDC and DUCey DDC and DUC Benefits Benefits Benefits Benefits Benefits SDR TSDR TSDR TSDR TSDR Tasksasksasksasksasks

Figure 19

Here we’ve ranked some of the popular signalprocessing tasks associated with SDR systems on a twoaxis graph, with compute Processing Intensity on thevertical axis and Flexibility on the horizontal axis.

What we mean by process intensity is the degree ofhighly-repetitive and rather primitive operations. At theupper left, are dedicated functions like A/D convertersand DDCs that require specialized hardware structuresto complete the operations in real time. ASICs are usuallychosen for these functions.

Flexibility pertains to the uniqueness or variabilityof the processing and how likely the function may haveto be changed or customized for any specific application.At the lower right are tasks like analysis and decisionmaking which are highly variable and often subjective.

Programmable general-purpose processors or DSPsare usually chosen for these tasks since these tasks can beeasily changed by software.

Now let’s temporarily step away from the softwareradio tasks and take a deeper look at programmablelogic devices.

Figure 20

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

A/D

CONV

Digital IF

Samples

Fs

LOWPASS

FILTER

Digital

Baseband

Samples

Fs/N

DUC

Digital Up

Converter

D/A

CONV

Digital

Baseband

Samples

Fs/N

DIGITAL

MIXER

DIGITAL

LOCAL

OSC

INTERPOLATION

FILTER

Digital IF

Samples

Fs

Digital

Baseband

Samples

Fs

DUC

Digital Down

Converter

Think of the DDC as a hardware preprocessor forprogrammable DSP or GPP processor. It preselects onlythe signals you are interested in and removes all others.This provides an optimum bandwidth and minimumsampling rate into the processor.

The same applies to the DUC. The processor onlyneeds to generate and deliver the baseband signalssampled at the baseband sample rate. The DUC thenboosts the sampling rate in the interpolation filter,performs digital frequency translation, and deliverssamples to the D/A at a very high sample rate.

The number of processors required in a system isdirectly proportional to the sampling frequency ofinput and output data. As a result, by reducing thesampling frequency, you can dramatically reduce thecost and complexity of the programmable DSPs orGPPs in your system.

Not only do DDCs and DUCs reduce the processorworkload, the reduction of bandwidth and sampling ratehelps save time in data transfers to another subsystem. Thishelps minimize recording time and disk space, and reducestraffic and bandwidth across communication channels.



1313131313


Early REarly REarly REarly REarly Roles for FPGAsoles for FPGAsoles for FPGAsoles for FPGAsoles for FPGAs LLLLLegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologies

Figure 21 Figure 22


As true programmable gate functions becameavailable in the 1970’s, they were used extensively byhardware engineers to replace control logic, registers,gates, and state machines which otherwise would haverequired many discrete, dedicated ICs.

Often these programmable logic devices were one-time factory-programmed parts that were soldered downand never changed after the design went into production.

These programmable logic devices were mostly thedomain of hardware engineers and the software toolswere tailored to meet their needs. You had tools foraccepting boolean equations or even schematics to helpgenerate the interconnect pattern for the growingnumber of gates.

Then, programmable logic vendors started offeringpredefined logic blocks for flip-flops, registers andcounters that gave the engineer a leg up on popularhardware functions.

Nevertheless, the hardware engineer was stillintimately involved with testing and evaluating thedesign using the same skills he needed for testingdiscrete logic designs. He had to worry about propaga-tion delays, loading, clocking and synchronizing—alltricky problems that usually had to be solved the hardway—with oscilloscopes or logic analyzers.

� Used primarily to replace discrete digital

hardware circuitry for:

� Control logic

� Glue logic

� Registers and gates

� State machines

� Counters and dividers

� Devices were selected by hardware engineers

� Programmed functions were seldom changed

after the design went into production

� Tools were oriented to hardware engineers

� Schematic processors

� Boolean processors

� Gates, registers, counters, multipliers

� Successful designs required high-level

hardware engineering skills for:

� Critical paths and propagation delays

� Pin assignment and pin locking

� Signal loading and drive capabilities

� Clock distribution

� Input signal synchronization and skew analysis


1414141414


FPGAs: New Device TFPGAs: New Device TFPGAs: New Device TFPGAs: New Device TFPGAs: New Device Technologyechnologyechnologyechnologyechnology FPGAs: New Development TFPGAs: New Development TFPGAs: New Development TFPGAs: New Development TFPGAs: New Development Toolsoolsoolsoolsools

Figure 23 Figure 24


It’s virtually impossible to keep up to date on FPGAtechnology, since new advancements are being madeevery day.

The hottest features are processor cores inside thechip, computation clocks to 500 MHz and above, andlower core voltages to keep power and heat down.

Several years ago, dedicated hardware multipliersstarted appearing and now you’ll find literally thousandsof them on-chip as part of the DSP initiative launchedby virtually all FPGA vendors.

High memory densities coupled with very flexiblememory structures meet a wide range of data flowstrategies. Logic slices with the equivalent of over tenmillion gates result from silicon geometries shrinkingbelow 0.1 micron.

BGA and flip-chip packages provide plenty of I/Opins to support on-board gigabit serial transceivers andother user-configurable system interfaces.

New announcements seem to be coming out everyday from chip vendors like Xilinx and Altera in a never-ending game of outperforming the competition.

To support such powerful devices, new design toolsare appearing that now open up FPGAs to both hard-ware and software engineers. Instead of just acceptinglogic equations and schematics, these new tools acceptentire block diagrams as well as VHDL and Verilogdefinitions.

Choosing the best FPGA vendor often hingesheavily on the quality of the design tools available tosupport the parts.

Excellent simulation and modeling tools help toquickly analyze worst case propagation delays andsuggest alternate routing strategies to minimize themwithin the part. This minimizes some of the trickytiming work for hardware engineers and can save onehours of tedious troubleshooting during design verifica-tion and production testing.

In the last few years, a new industry of third partyIP (Intellectual Property) core vendors now offerthousands of application-specific algorithms. These areready to drop into the FPGA design process to help beatthe time-to-market crunch and to minimize risk.

� High Level Design Tools

� Block Diagram System Generators

� Schematic Processors

� High-level language compilers for

VHDL & Verilog

� Advanced simulation tools for modeling speed,

propagation delays, skew and board layout

� Faster compilers and simulators save time

� Graphically-oriented debugging tools

� IP (Intellectual Property) Cores

� FPGA vendors offer both free and licensed cores

� FPGA vendors promote third party core vendors

� Wide range of IP cores available

� 500+ MHz DSP Slices and Memory Structures

Over 3500 dedicated on-chip hardware multipliers

On-board GHz Serial Transceivers

Partial Reconfigurability Maintains

Operation During Changes

Switched Fabric Interface Engines

Over 690,000 Logic Cells

Gigabit Ethernet media access controllers

On-chip 405 PowerPC RISC micro-controller cores

Memory densities approaching 85 million bits

Reduced power with core voltages at 1 volt

Silicon geometries to 28 nanometers

High-density BGA and flip-chip packaging

Over 1200 user I/O pins

Configurable logic and I/O interface standards

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�

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�

�

�

�

�

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1515151515


FPGAs for SDRFPGAs for SDRFPGAs for SDRFPGAs for SDRFPGAs for SDR FPGAs Bridge the SDR Application SpaceFPGAs Bridge the SDR Application SpaceFPGAs Bridge the SDR Application SpaceFPGAs Bridge the SDR Application SpaceFPGAs Bridge the SDR Application Space

Figure 25 Figure 26


As a result, FPGAs have significantly invaded theapplication task space as shown by the center bubble inthe task diagram above.

They offer the advantages of parallel hardware tohandle some of the high process-intensity functions likeDDCs and the benefit of programmability to accommo-date some of the decoding and analysis functions of DSPs.

These advantages may come at the expense ofincreased power dissipation and increased product costs.However, these considerations are often secondary to theperformance and capabilities of these remarkable devices.

Like ASICs, all the logic elements in FPGAs canexecute in parallel. This includes the hardware multipli-ers, and you can now get over 1000 of them on a singleFPGA.

This is in sharp contrast to programmable DSPs,which normally have just a handful of multipliers thatmust be operated sequentially.

FPGA memory can now be configured with thedesign tool to implement just the right structure fortasks that include dual port RAM, FIFOs, shift registersand other popular memory types.

These memories can be distributed along the signalpath or interspersed with the multipliers and mathblocks, so that the whole signal processing task operatesin parallel in a systolic pipelined fashion.

Again, this is dramatically different from sequentialexecution and data fetches from external memory as in aprogrammable DSP.

As we said, FPGAs now have specialized serial andparallel interfaces to match requirements for high-speedperipherals and buses.

� Parallel Processing

� Hardware Multipliers for DSP

� FPGAs can now have over 500 hardware multipliers

� Flexible Memory Structures

� Dual port RAM, FIFOs, shift registers, look up tables, etc.

� Parallel and Pipelined Data Flow

� Systolic simultaneous data movement

� Flexible I/O

� Supports a variety of devices, buses and interface standards

� High Speed

� Available IP cores optimized for special functions


1616161616


ModelModel

FeatureFeature7141-4307141-430 7141-4207141-420 7142-4287142-428 71517151 71527152 71537153

125 MHz125 MHzMax Sample RateMax Sample Rate 125 MHz125 MHz 125 MHz125 MHz 200 MHz200 MHz 200 MHz200 MHz 200 MHz200 MHz

14-Bit14-BitInput ResolutionInput Resolution 14-Bit14-Bit 14-Bit14-Bit 16-Bit16-Bit 16-Bit16-Bit 16-Bit16-Bit

11Input ChannelsInput Channels 22 44 44 44 44

256256DDC ChannelsDDC Channels 2 or 42 or 4 44 256256 3232 2 or 42 or 4

1K-10K1K-10KDecimation RangeDecimation Range Core: 2,4,8,16,32,64

GC4016: 32to 16k

Core: 2,4,8,16,32,64

GC4016: 32to 16k2 to 64K

Steps of 1

2 to 64K

Steps of 1128 to 1024

Steps of 64

128 to 1024

Steps of 6416 to 8192

Steps of 8

16 to 8192

Steps of 82 Ch: 2 to 65536

4 Ch: 2 to 256

2 Ch: 2 to 65536

4 Ch: 2 to 256

24*DEC/51224*DEC/512No. of Filter TapsNo. of Filter Taps Core: 28*DECCore: 28*DEC 28*DEC28*DEC 24*DEC/6424*DEC/64 28*DEC/828*DEC/8 28*DEC28*DEC

Normal I/QNormal I/QOutput FormatOutput Format I/Q, Offset,

Inverse, Real

I/Q, Offset,

Inverse, RealI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, Inverse

16-Bit16-BitOutput ResolutionOutput Resolution 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit

32-bits - 0 to Fs32-bits - 0 to FsTuning FrequencyTuning Frequency 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs

--Phase OffsetPhase Offset 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg 32-bits ± 180 deg32-bits ± 180 deg

32 bits32 bitsGain ControlGain Control 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits

NoneNoneDAC InterpolationDAC Interpolation 2 - 327682 - 32768 2 - 327682 - 32768 NoneNone NoneNone NoneNone

NoneNonePower MetersPower Meters NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneThresh DetectorsThresh Detectors NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneChannel SummersChannel Summers NoneNone NoneNone NoneNone 32 channels32 channels 2 or 4 channels2 or 4 channels

The above chart shows the salient characteristics forsome of Pentek’s SDR products with IP cores installedin their FPGAs. The chart provides information regard-ing the number of input channels, maximum samplingfrequency of their A/Ds, and number of DDC channelsin each one. This information is followed by DDCcharacteristics regarding the decimation range and availablesteps along with the output format and resolution.


TTTTTypical Pypical Pypical Pypical Pypical Pentek Pentek Pentek Pentek Pentek Products with Installed SDR IP Coresroducts with Installed SDR IP Coresroducts with Installed SDR IP Coresroducts with Installed SDR IP Coresroducts with Installed SDR IP Cores

Other information that’s specific to each core isincluded as well as an indication of the models thatinclude an interpolation filter and output D/A. As shownin the chart, some of these models include power meters,threshold detectors, and gain along with phase offsetcontrol for optimizing results in applications such asdirection-finding and beamforming.

All the models shown here are PMC or PMC/XMCmodules. These products are also available in PCI, cPCI,PCIe and VPX formats as well.

Figure 27


1717171717



FPGA RFPGA RFPGA RFPGA RFPGA Resource Comparisonesource Comparisonesource Comparisonesource Comparisonesource Comparison

Figure 28

The above chart compares the available resources inthe five Xilinx FPGA families that are used in most ofthe Pentek products.

● Virtex-II Pro: VP● Virtex-4: FX, LX and SX● Virtex-5: LX and SX● Virtex-6: LX and SX● Virtex-7: VX

The Virtex-II family includes hardware multipliersthat support digital filters, averagers, demodulatorsand FFTs—a major benefit for software radio signalprocessing. The Virtex-II Pro family dramaticallyincreased the number of hardware multipliers and alsoadded embedded PowerPC microcontrollers.

The Virtex-4 family is offered as three subfamiliesthat dramatically boost clock speeds and reduce powerdissipation over previous generations.

The Virtex-4 LX family delivers maximum logic andI/O pins while the SX family boasts of 512 DSP slicesfor maximum DSP performance. The FX family is agenerous mix of all resources and is the only family tooffer RocketIO, PowerPC cores, and the newly addedgigabit Ethenet ports.

*Virtex-II Pro and Virtex-4 Slices actually require 2.25 Logic Cells;*Virtex-5, Virtex-6 and Virtex-7 Slices actually require 6.4 Logic Cells

VirVirVirVirVirtex-II Ptex-II Ptex-II Ptex-II Ptex-II Prororororo VirVirVirVirVirtex-4tex-4tex-4tex-4tex-4 VirVirVirVirVirtex-5tex-5tex-5tex-5tex-5 VirVirVirVirVirtex-6tex-6tex-6tex-6tex-6 VirVirVirVirVirtex-7tex-7tex-7tex-7tex-7VPVPVPVPVP FX, LX, SXFX, LX, SXFX, LX, SXFX, LX, SXFX, LX, SX LX, SXLX, SXLX, SXLX, SXLX, SX LX, SXLX, SXLX, SXLX, SXLX, SX VXVXVXVXVX

Logic Cells 53K–74K 41K–152K 46K–156K 128K–476K 326K–693KSlices* 24K–33K 18K–68K 7K–24K 20K–74K 51K–108KCLB Flip-Flops 47K–66K 51K–98K 33K–97K 160K–595K 408K–866KBlock RAM (kb) 4,176–5,904 4,176–6,768 4,752–8,784 9,504–36,304 27,000–52,920DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48E DSP48EDSP Slices 232–328 96–512 128–640 480–2,016 1,120–3,600Serial Gbit Transceivers – 0–20 12–16 20–48 20–48PCI Express Support – – – Gen2x8 Gen2x8, Gen3x8SelectIO – 448–768 480–640 320–600 300–600

The Virtex-5 family LX devices offer maximumlogic resources, gigabit serial transceivers, and Ethernetmedia access controllers. The SX devices push DSPcapabilities with all of the same extras as the LX.

The Virtex-5 devices offer lower power dissipation,faster clock speeds and enhanced logic slices. They alsoimprove the clocking features to handle faster memoryand gigabit interfaces. They support faster single-endedand differential parallel I/O buses to handle fasterperipheral devices.

The Virtex-6 and Virtex-7 devices offer still higherdensity, more processing power, lower power consump-tion, and updated interface features to match the latesttechnology I/O requirements including PCI Express.Virtex-6 supports PCIe 2.0 and Virtex-7 supports PCIe 3.0

The ample DSP slices are responsible for themajority of the processing power of the Virtex-6 andVirtex-7 families. Increases in operating speed from 500 MHzin V-4, to 550 MHz in V-5, to 600 MHz in V-6, to900 MHz in V-7 and continuously increasing densityallow more DSP slices to be included in the same-sizepackage. As shown in the chart, Virtex-6 tops out at animpressive 2,016 DSP slices, while Virtex-7 tops out atan even more impressive 3,600 DSP slices.


1818181818


The Pentek family of board-level software radioproducts is the most comprehensive in the industry.Most of these products are available in several formatsto satisfy a wide range of requirements.

In addition to their commercial versions, manysoftware radio products are available in ruggedized andconduction-cooled versions.

All of the software radio products include input A/Dconverters. Some of these products are software radioreceivers in that they include only DDCs. Others aresoftware radio transceivers and they include DDCs aswell as DUCs with output D/A converters. These comewith independent input and output clocks.

All Pentek software radio products include multiboardsynchronization that facilitates the design of multichannelsystems with synchronous clocking, gating and triggering.

Pentek’s comprehensive software support includesthe ReadyFlow® Board Support Package, the GateFlow®

FPGA Design Kit and high-performance factory-installed IP cores that expand the features and rangeof many Pentek software radio products. In addition,Pentek software radio recording systems are supportedwith SystemFlow® recording software that features agraphical user interface.

A complete listing of these products with activelinks to their datasheets on Pentek’s website is includedat the end of this handbook.


Figure 29

PMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, and VMEbus SofPMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, and VMEbus SofPMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, and VMEbus SofPMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, and VMEbus SofPMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, and VMEbus Software Rtware Rtware Rtware Rtware Radioadioadioadioadio

PMC/XMC Module

6U CompactPCI BoardPCI Board Full-length

PCI Express Board

Half-lengthPCI Express Board

VMEbus Board

3U OpenVPX BoardsCOTS and Rugged


1919191919


Multiband RMultiband RMultiband RMultiband RMultiband Receiverseceiverseceiverseceiverseceivers

The unit supports the channel combining mode ofthe 4016s such that two or four individual 2.5 MHzchannels can be combined for output bandwidths of5 MHz or 10 MHz, respectively.

The sampling clock can be sourced from an internal100 MHz crystal oscillator or from an external clock suppliedthrough an SMA connector or the LVDS clock/sync bus onthe front panel. The LVDS bus allows multiple modules to besynchronized with the same sample clock, gating, triggeringand frequency switching signals. Up to 80 modules can besynchronized with the Model 9190 Clock and Sync Genera-tor. Custom interfaces can be implemented by using the 64user-defined FPGA I/O pins on the P4 connector.

Versions of the 7131 are also available as a PCIboard (Model 7631A), 6U cPCI (Models 7231 and7231D dual density), 3U cPCI (Model 7331) and 3UVPX (Model 5331). All these products have similarfeatures.


The Model 7131, a 16-Channel Multiband Receiver,is a PMC module. The 7131 PMC may be attached to awide range of industry processor platforms equippedwith PMC sites.

Two 14-bit 105 MHz A/D Converters accepttransformer-coupled RF inputs through two front panelSMA connectors. Both inputs are connected to fourTI/GC4016 quad DDC chips, so that all 16 DDCchannels can independently select either A/D.

Four parallel outputs from the four DDCs deliverdata into the Virtex-II FPGA which can be either theXC2V1000 or XC2V3000. The outputs of the two A/Dconverters are also connected directly to the FPGA tosupport the DDC bypass path to the PCI bus and for directprocessing of the wideband A/D signals by the FPGA.

Figure 30

Model 53313U VPX

Model 7231D6U cPCI

Model 73313U cPCI

Model 7631APCI

Model 7131PMC

Model 7131 PMC Model 7131 PMC Model 7131 PMC Model 7131 PMC Model 7131 PMC ●●●●● Model 7231 6U cPCI Model 7231 6U cPCI Model 7231 6U cPCI Model 7231 6U cPCI Model 7231 6U cPCI ●●●●● Model 7331 3U cPCI Model 7331 3U cPCI Model 7331 3U cPCI Model 7331 3U cPCI Model 7331 3U cPCI●●●●● Model 7631A PCI Model 7631A PCI Model 7631A PCI Model 7631A PCI Model 7631A PCI ●●●●● Model 5331 3U VPX Model 5331 3U VPX Model 5331 3U VPX Model 5331 3U VPX Model 5331 3U VPX


2020202020


Multiband TMultiband TMultiband TMultiband TMultiband Transceivers with Virransceivers with Virransceivers with Virransceivers with Virransceivers with Virtex-II Ptex-II Ptex-II Ptex-II Ptex-II Pro FPGAro FPGAro FPGAro FPGAro FPGA


Figure 31

Model 7141PMC/XMC

The Model 7141 PMC/XMC module combinesboth receive and transmit capabilities with a high-performance Virtex II-Pro FPGA and supports theVITA 42 XMC standard with optional switched fabricinterfaces for high-speed I/O.

The front end of the module accepts two RF inputsand transformer-couples them into two 14-bit A/Dconverters running at 125 MHz. The digitized outputsignals pass to a Virtex-II Pro FPGA for signal process-ing or routing to other module resources.

These resources include a quad digital down-converter, a digital upconverter with dual D/A converters,512 MB DDR SDRAM delay memory and the PCIbus. The FPGA also serves as a control and statusengine with data and programming interfaces to each ofthe on-board resources. Factory-installed FPGA functionsinclude data multiplexing, channel selection, data packing,gating, triggering, and SDRAM memory control.

In addition to acting as a simple transceiver, themodule can perform user-defined DSP functions on the

baseband signals, developed using Pentek’s GateFlowand ReadyFlow development tools.

The module includes a TI/GC4016 quad digitaldownconverter along with a TI DAC5686 digitalupconverter with dual D/A converters.

Each channel in the downconverter can be set withan independent tuning frequency and bandwidth. Theupconverter translates a real or complex baseband signal toany IF center frequency from DC to 160 MHz and candeliver real or complex (I + Q) analog outputs throughits two 16-bit D/A converters. The digital upconvertercan be bypassed for two interpolated D/A outputs withsampling rates to 500 MHz.

Versions of the 7141 are also available as a PCIefull-length board (Models 7741 and 7741D dual density),PCIe half-length board (Model 7841), 3U VPX board(Model 5341), PCI board (Model 7641), 6U cPCI(Models 7241 and 7241D dual density), and 3U cPCI(Model 7341). Model 7141-703 is a conduction-cooledversion.

Model 7141 PMC/XMC Model 7141 PMC/XMC Model 7141 PMC/XMC Model 7141 PMC/XMC Model 7141 PMC/XMC ●●●●● Model 7241 6U cPCI Model 7241 6U cPCI Model 7241 6U cPCI Model 7241 6U cPCI Model 7241 6U cPCI ●●●●● Model 7341 3U cPCI Model 7341 3U cPCI Model 7341 3U cPCI Model 7341 3U cPCI Model 7341 3U cPCI ● ● ● ● ● Model 7641 PCIModel 7641 PCIModel 7641 PCIModel 7641 PCIModel 7641 PCI●●●●● Model 7741 F Model 7741 F Model 7741 F Model 7741 F Model 7741 Full-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ●●●●● Model 7841 Half-length PCIe Model 7841 Half-length PCIe Model 7841 Half-length PCIe Model 7841 Half-length PCIe Model 7841 Half-length PCIe ●●●●● Model 5341 3U VPX Model 5341 3U VPX Model 5341 3U VPX Model 5341 3U VPX Model 5341 3U VPX

AD6645

105 MHz

14-BIT A/D

AD6645

105 MHz

14-BIT A/D

TIMING BUS

GENERATOR A

XTL

OSC A

SYNC

INTERRUPTS

& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

RF

XFORMR

RF

XFORMR

VIRTEX-II Pro FPGA

XC2VP50

DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.

FLASH

16 MB

DDR

SDRAM

256 MB

DDR

SDRAM

128 MB

DDR

SDRAM

128 MBPCI 2.2 INTERFACE

(64 Bits / 66 MHz)

Sample

Clock B In

Sample

Clock A In

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/

Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

RF In RF In

Clock/Sync/Gate

Bus A

Clock/Sync/Gate

Bus B

To All

Sections Control/

Status

PCI BUS

(64 Bits / 66 MHz)

P15 XMC

VITA 42.0

(Serial RapidIO,

PCI-Express, etc.)

P4 PMC

FPGA I/O

(Option –104)

14 14

16

16

16

14

24

32

16

32 32 3264 64

RF XFORMR RF XFORMR

RF Out RF Out

DAC5686

DIGITAL UPCONVERTER

16-bit D/A 16-bit D/A

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

FRONT

PANEL

CONNECTOR

GC4016

4-CHANNEL

DDC


2121212121



TTTTTransceivers with Dual Wransceivers with Dual Wransceivers with Dual Wransceivers with Dual Wransceivers with Dual Wideband DDC and Interpolation Fideband DDC and Interpolation Fideband DDC and Interpolation Fideband DDC and Interpolation Fideband DDC and Interpolation Filter Installed Coresilter Installed Coresilter Installed Coresilter Installed Coresilter Installed Cores

Figure 32

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE

MEMORY

CONTROL

&

DATA ROUTING

MEM W

FIFO

MEM W

FIFO

A/D A

FIFO

A/D B

FIFO

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

D/A A

FIFO

D/A B

FIFO

MUX

MUX

CFIR

FILTER

CIC

FILTER

MUX

WIDEBAND

DIGITAL

DOWNCONVERTR A

DECIMATION: 2 – 64

WIDEBAND

DIGITAL

DOWNCONVERTR A


M

U

X

M

U

X

MUX

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

MEMORY

MEMORY

DDC C

DDC D

D/A A

D/A B

A/D A

A/D B

A/D A

A/D B

DDC A

DDC B

A/D A

A/D B

DDC A

DDC BWB DDC A

DDC A

WB DDC B

DDC B

MEMORY

D/A A FIFO

MEMORY

D/A B FIFO

PCI BUS

64 bit /

66 MHz

WIDEBAND DDC CORE

INTERPOLATION CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE

Model 7141-420 PMC/XMC Model 7141-420 PMC/XMC Model 7141-420 PMC/XMC Model 7141-420 PMC/XMC Model 7141-420 PMC/XMC ●●●●● Model 7241-420 6U cPCI Model 7241-420 6U cPCI Model 7241-420 6U cPCI Model 7241-420 6U cPCI Model 7241-420 6U cPCI ●●●●● Model 7341-420 3U cPCI Model 7341-420 3U cPCI Model 7341-420 3U cPCI Model 7341-420 3U cPCI Model 7341-420 3U cPCIModel 7641-420 PCI Model 7641-420 PCI Model 7641-420 PCI Model 7641-420 PCI Model 7641-420 PCI ●●●●● Model 7741-420 F Model 7741-420 F Model 7741-420 F Model 7741-420 F Model 7741-420 Full-length PCIeull-length PCIeull-length PCIeull-length PCIeull-length PCIe

Model 7841-420 Half-length PCIeModel 7841-420 Half-length PCIeModel 7841-420 Half-length PCIeModel 7841-420 Half-length PCIeModel 7841-420 Half-length PCIe ●●●●● Model 5341-420 3U VPX Model 5341-420 3U VPX Model 5341-420 3U VPX Model 5341-420 3U VPX Model 5341-420 3U VPX

The Pentek IP Core 420 includes a dual high-performance wideband DDC and an interpolation filter.Factory-installed in the Model 7141 FPGA, they extendthe range of both the GC4016 ASIC DDC and theDAC5686 DUC.

Each of the core 420 DDCs translates any frequencyband within the input bandwidth range down to zerofrequency. A complex FIR low pass filter removes any out-of-band frequency components. An output decimator andformatter deliver either complex or real data. An input gainblock scales both I and Q data streams by a 16-bit gainterm.

The mixer utilizes four 18x18-bit multipliers tohandle the complex inputs from the NCO and thecomplex data input samples. The FIR filter is capable ofstoring and utilizing up to four independent sets of18-bit coefficients for each decimation value. Thesecoefficients are user-programmable by using RAMstructures within the FPGA.

The decimation settings of 2, 4, 8, 16, 32, and 64provide output bandwidths from 40 MHz down to 1.25MHz for an A/D sampling of 100 MHz. A multiplexer allowsdata to be sourced from either the A/Ds or the GC4016,extending the cascaded decimation range to 1,048,576.

The interpolation filter included in the 420 Core,expands the interpolation factor from 2 to 32,768programmable in steps of 2, and relieves the hostprocessor from performing upsampling tasks. Includingthe DUC, the maximum interpolation factor is 32,768which is comparable to the maximum decimation of theGC4016 narrowband DDC.

Versions of the 7141-420 are also available as a 3UVPX board (Model 5341-420), PCIe full-length board(Models 7741-420 and 7741D-420 dual density), PCIehalf-length board (Model 7841-420), PCI board (Model7641-420), 6U cPCI (Models 7241-420 and 7241D-420dual density), or 3U cPCI (Model 7341-420).Model 7141-703-420 is a conduction-cooled version.


2222222222


TTTTTransceivers with 256-ransceivers with 256-ransceivers with 256-ransceivers with 256-ransceivers with 256-Channel Narrowband DDC Installed CoreChannel Narrowband DDC Installed CoreChannel Narrowband DDC Installed CoreChannel Narrowband DDC Installed CoreChannel Narrowband DDC Installed Core


Figure 33

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INT

MEM W

FIFO

MEM W

FIFO

D/A A

FIFO

D/A B

FIFO

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

DDC 1

Local Oscillator, Mixer, Filter

M

U

X

1

2

255

256

MUX

M

U

X

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

OUT A

DDC A

OUT B

DDC B

OUT C

DDC C

OUT D

DDC D

PCI BUS

64 bit /

66 MHz

256 CHANNEL DIGITAL DOWNCONVERTER BANK

CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

DDC 1


DDC 255


DDC 256


For applications that require many channels ofnarrowband downconverters, Pentek offers the GateFlowIP Core 430 256-channel digital downconverter bank.Factory installed in the Model 7141 FPGA, Core 430creates a flexible, very high-channel count receiversystem in a small footprint.

Unlike classic channelizer methods, the Pentek 430core allows for completely independent programmabletuning of each individual channel with 32-bit resolutionas well as filter characteristics comparable to manyconventional ASIC DDCs.

Added flexibility comes from programmable globaldecimation settings ranging from 1024 to 8192 in stepsof 256, and 18-bit user programmable FIR decimatingfilter coefficients for the DDCs. Default DDC filtercoefficient sets are included with the core for all possibledecimation settings.

Core 430 utilizes a unique method of channelization.It differs from others in that the channel center frequen-

Model 7141-430 PMC/XMC Model 7141-430 PMC/XMC Model 7141-430 PMC/XMC Model 7141-430 PMC/XMC Model 7141-430 PMC/XMC ●●●●● Model 7241-430 6U cPCI Model 7241-430 6U cPCI Model 7241-430 6U cPCI Model 7241-430 6U cPCI Model 7241-430 6U cPCI ●●●●● Model 7341-430 3U cPCI Model 7341-430 3U cPCI Model 7341-430 3U cPCI Model 7341-430 3U cPCI Model 7341-430 3U cPCIModel 7641-4Model 7641-4Model 7641-4Model 7641-4Model 7641-4333330 PCI 0 PCI 0 PCI 0 PCI 0 PCI ●●●●● Model 7741-4 Model 7741-4 Model 7741-4 Model 7741-4 Model 7741-4333330 F0 F0 F0 F0 Full-length PCIeull-length PCIeull-length PCIeull-length PCIeull-length PCIe

Model 7841-4Model 7841-4Model 7841-4Model 7841-4Model 7841-4333330 Half-length PCIe0 Half-length PCIe0 Half-length PCIe0 Half-length PCIe0 Half-length PCIe ●●●●● Model 5341-430 3U VPX Model 5341-430 3U VPX Model 5341-430 3U VPX Model 5341-430 3U VPX Model 5341-430 3U VPX

cies need not be at fixed intervals, and are independentlyprogrammable to any value.

Core 430 DDC comes factory installed in the Model7141-430. A multiplexer allows data to be sourced from eitherA/D. At the output, a multiplexer allows for routing eitherthe output of the GC4016 or the 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from bothA/D channels are presented to the PCI Bus at a rate equalto the A/D clock rate divided by any integer value between1 and 4096. A TI DAC5686 digital upconverter and dualD/A accepts baseband real or complex data streams fromthe PCI Bus with signal bandwidths up to 50 MHz.

Versions of the 7141-430 are also available as a PCIefull-length board (Models 7741-430 and 7741D-430 dualdensity), PCIe half-length board (Model 7841-430), 3UVPX board (Model 5341-430), PCI board (Model 7641-430), 6U cPCI (Models 7241-430 and 7241D-430 dualdensity), or 3U cPCI (Model 7341-430).Model 7141-703-430 is a conduction-cooled version.


2323232323


DDR 2

SDRAM

256 MB

DDR 2

SDRAM

256 MB

DDR 2

SDRAM

256 MB

32 32 32

32

RF

XFORMR

RF Out

DAC5686

DIGITAL

UPCONVERTER

16-bit D/A

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

P15 XMC

VITA 42.0

P4 PMC

FPGA I/O

(Option –104)

64

64LOCAL

BUS

VIRTEX-4 FPGA

XC4VFX60 or XC4VFX100

PCI BUS

(64 Bits / 66 MHz)

PCI 2.2

INTERFACE

SERIAL

INTERFACE

32 32 32HI-SPEED

BUSES

VIRTEX-4 FPGA

XC4VSX55

DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.

Control/

Status

TIMING BUS

GENERATOR A

XTL

OSC A

SYNC

INTERRUPTS

& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/

Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

Clock/Sync/Gate

Bus A

Clock/Sync/Gate

Bus B

To All

Sections

Sample

Clock In

Multichannel TMultichannel TMultichannel TMultichannel TMultichannel Transceivers with Virransceivers with Virransceivers with Virransceivers with Virransceivers with Virtex-4 FPGAstex-4 FPGAstex-4 FPGAstex-4 FPGAstex-4 FPGAs


Model 7142PMC/XMC

Figure 34

The Model 7142 is a Multichannel PMC/XMCmodule. It includes four 125 MHz 14-bit A/D convert-ers and one upconverter with a 500 MHz 16-bit D/Aconverter to support wideband receive and transmitcommunication channels.

Two Xilinx Virtex-4 FPGAs are included: anXC4VSX55 or LX100 and an XC4VFX60 or FX100.The first FPGA is used for control and signal processingfunctions, while the second one is used for implement-ing board interface functions including the XMC interface.

It also features 768 MB of SDRAM for implementingup to 2.0 sec of transient capture or digital delay memoryfor signal intelligence tracking applications at 125 MHz.

A 16 MB flash memory supports the boot code forthe two on-board IBM 405 PowerPC microcontrollercores within the FPGA.

A 9-channel DMA controller and 64 bit / 66 MHz PCIinterface assures efficient transfers to and from the module.

A high-performance 160 MHz IP core wideband digitaldownconverter may be factory-installed in the first FPGA.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the second FPGAto the XMC connector with two 2.5 GB/sec data linksto the carrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichannelapplications where the relative phases must be preserved.

Versions of the 7142 are also available as a PCIe full-length board (Models 7742 and 7742D dual density),PCIe half-length board (Model 7842), 3U VPX (Model5342), PCI board (Model 7642), 6U cPCI (Models 7242and 7242D dual density), and 3U cPCI (Model 7342).

Model 714Model 714Model 714Model 714Model 71422222 PMC/XMC PMC/XMC PMC/XMC PMC/XMC PMC/XMC ●●●●● Model 724 Model 724 Model 724 Model 724 Model 72422222 6U cPCI 6U cPCI 6U cPCI 6U cPCI 6U cPCI ●●●●● Model 734 Model 734 Model 734 Model 734 Model 73422222 3U cPCI 3U cPCI 3U cPCI 3U cPCI 3U cPCI ●●●●● Model 764Model 764Model 764Model 764Model 76422222 PCI PCI PCI PCI PCIModel 7Model 7Model 7Model 7Model 777777444442 F2 F2 F2 F2 Full-lengthull-lengthull-lengthull-lengthull-length PCIe PCIe PCIe PCIe PCIe ●●●●● Model 7 Model 7 Model 7 Model 7 Model 788888444442 Half-length2 Half-length2 Half-length2 Half-length2 Half-length PCIe PCIe PCIe PCIe PCIe ●●●●● Model Model Model Model Model 55555343434343422222 3U 3U 3U 3U 3U VPXVPXVPXVPXVPX


2424242424


TTTTTransceivers with Fransceivers with Fransceivers with Fransceivers with Fransceivers with Four Multiband DDCs and Interpolation Four Multiband DDCs and Interpolation Four Multiband DDCs and Interpolation Four Multiband DDCs and Interpolation Four Multiband DDCs and Interpolation Filter Installed Coresilter Installed Coresilter Installed Coresilter Installed Coresilter Installed Cores


Figure 35

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

MEMORY

CONTROL &

DATA ROUTING

D/A

FIFO

MUXCFIR

FILTER

CIC

FILTER

MUX

DIGITAL

DOWNCONVERTR A

STAGE 1


CH A

RF In

CH B

RF In

RF Out

Sample

Clock In

Clock/Sync

Bus

A/D A

A/D A

A/D B

A/D A

MEMORY

D/A FIFO

PCI BUS

64 bit /

66 MHz

DIGITAL DOWNCONVERTER CORE

INTERPOLATION CORE XC4VSX55

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

LTC2255

125 MHz

14-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

A/D B

A/D C

A/D D

A/D C

A/D D

DIGITAL

DOWNCONVERTR A

STAGE 2


DIGITAL

DOWNCONVERTR B

STAGE 1


A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR B

STAGE 2


DIGITAL

DOWNCONVERTR C

STAGE 1


A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR C

STAGE 2


DIGITAL

DOWNCONVERTR D

STAGE 1


A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR D

STAGE 2


DDC A

MUX

A/D B

DDC B

MUX

A/D C

DDC C

MUX

A/D D

DDC D

D/A

M

U

X

M

U

X

M

U

X

M

U

X

MEM W

FIFO

MEM W

FIFO

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

256 MB DDR

SDRAM

256 MB DDR

SDRAM

256 MB DDR

SDRAM

The Pentek IP Core 428 includes four high-performance multiband DDCs and an interpolationfilter. Factory-installed in the Model 7142 FPGA,they add DDCs to the Model 7142 and extend therange of its DAC5686 DUC.

The Core 428 downconverter translates any frequencyband within the input bandwidth range down to zerofrequency. The DDCs consist of two cascaded decimat-ing FIR filters. The decimation of each DDC can be setindependently. After each filter stage is a post filter gainstage. This gain may be used to amplify small signalsafter out-of-band signals have been filtered out.

The NCO provides over 108 dB spurious-freedynamic range (SFDR). The FIR filter is capable ofstoring and utilizing two independent sets of 18-bitcoefficients. These coefficients are user-programmable byusing RAM structures within the FPGA. NCO tuningfrequency, decimation and filter coefficients can bechanged dynamically.

Four identical Core 428 DDCs are factory installedin the 7142-428 FPGA. An input multiplexer allowsany DDC to independently select any of the four A/Dsources. The overal decimation range from 2 to 65,536,programmable in steps of 1, provides output bandwidthsfrom 50 MHz down to 1.52 kHz for an A/D samplingrate of 125 MHz and assuming an 80% filter.

The Core 428 interpolation filter increases the samplingrate of real or complex baseband signals by a factor of 16 to2048, programmable in steps of 4, and relieves the hostprocessor from performing upsampling tasks. The interpola-tion filter can be used in series with the DUC’s built-ininterpolation, for a maximum interpolation of 32,768.

Versions of the 7142-428 are also available as a PCIefull-length board (Models 7742-428 and 7742D-428 dualdensity), PCIe half-length board (Model 7842-428), PCIboard (Model 7642-428), 6U cPCI (Models 7242-428 and7242D-428 dual density), 3U cPCI (Model 7342-428),and 3U VPX (Model 5342-428).

Model 714Model 714Model 714Model 714Model 7142-4282-4282-4282-4282-428 PMC/XMC PMC/XMC PMC/XMC PMC/XMC PMC/XMC ●●●●● Model 724 Model 724 Model 724 Model 724 Model 7242-4282-4282-4282-4282-428 6U cPCI 6U cPCI 6U cPCI 6U cPCI 6U cPCI ●●●●● Model 734 Model 734 Model 734 Model 734 Model 7342-4282-4282-4282-4282-428 3U cPCI 3U cPCI 3U cPCI 3U cPCI 3U cPCIModel 7642-428 PCI Model 7642-428 PCI Model 7642-428 PCI Model 7642-428 PCI Model 7642-428 PCI ●●●●● Model 7742-428 F Model 7742-428 F Model 7742-428 F Model 7742-428 F Model 7742-428 Full-length PCIeull-length PCIeull-length PCIeull-length PCIeull-length PCIe

Model 7742-428 Model 7742-428 Model 7742-428 Model 7742-428 Model 7742-428 HalfHalfHalfHalfHalf-length PCIe-length PCIe-length PCIe-length PCIe-length PCIe ●●●●● Model Model Model Model Model 5555534343434342-4282-4282-4282-4282-428 3U 3U 3U 3U 3U VPXVPXVPXVPXVPX


2525252525


256- 256- 256- 256- 256-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/D


Figure 36

.

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

PCI 2.2

INTERFACE

MUXDIGITAL

DOWNCONVERTR

BANK 1: CH 1 - 64

DECIMATION: 128 - 1024

CH A

RF In

CH B

RF In

Sample

Clock In

Sync Bus

A/D A

A/D BI & Q

PCI BUS

64 bit /

66 MHz


XC5VSX95T

RF

XFORMR

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

TIMING BUS

GENERATOR

Clock / Gate /

Sync / PPS

XTAL

OSC

PCI 2.2

INTERFACE

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

A/D C

A/D D

DDC BANK 1

MUX

MUX

MUX

M

U

X

M

U

X

M

U

X

M

U

X

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

PPS In

TTL In

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR

BANK 2: CH 65 - 128


DIGITAL

DOWNCONVERTR

BANK 3: CH 129 - 192


DIGITAL

DOWNCONVERTR

BANK 4: CH 193 - 256


A/D B

DDC BANK 2

A/D C

DDC BANK 3

A/D D

DDC BANK 4

I & Q

I & Q

I & Q

The Model 7151 PMC module is a 4-channel high-speed digitizer with a factory-installed 256-channelDDC core. The front end of the module accepts fourRF inputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7151 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical64-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as theinput source for each DDC bank. Each of the 256 DDCshas an independent 32-bit tuning frequency setting.

All of the 64 channels within a bank share a commondecimation setting that can range from 128 to 1024,programmable in steps of 64. For example, with a samplingrate of 200 MHz, the available output bandwidthsrange from 156.25 kHz to 1.25 MHz. Each 64-channelbank can have its own unique decimation setting

supporting as many as four different output bandwidthsfor the board.

The decimating filter for each DDC bank accepts aunique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% output band-width is better than 100 dB.

Each DDC delivers a complex output streamconsisting of 24-bit I + 24-bit Q samples. Any numberof channels can be enabled within each bank, selectablefrom 0 to 64. Each bank includes an output sampleinterleaver that delivers a channel-multiplexed stream forall enabled channels within the bank.

Versions of the 7151 are also available as a PCIefull-length board (Models 7751 and 7751D dual density),PCIe half-length board (Model 7851), PCI board (Model7651), 6U cPCI (Models 7251 and 7251D dual density),3U cPCI (Model 7351), and 3U VPX (Model 5351).

Model 7151 PMC Model 7151 PMC Model 7151 PMC Model 7151 PMC Model 7151 PMC ●●●●● Model 7251 6U cPCI Model 7251 6U cPCI Model 7251 6U cPCI Model 7251 6U cPCI Model 7251 6U cPCI ●●●●● Model 7351 3U cPCI Model 7351 3U cPCI Model 7351 3U cPCI Model 7351 3U cPCI Model 7351 3U cPCI ●●●●● Model 7651 PCI Model 7651 PCI Model 7651 PCI Model 7651 PCI Model 7651 PCIModel 7751 FModel 7751 FModel 7751 FModel 7751 FModel 7751 Full-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ●●●●● Model 7851 Half-length PCIe Model 7851 Half-length PCIe Model 7851 Half-length PCIe Model 7851 Half-length PCIe Model 7851 Half-length PCIe ●●●●● Model 5351 3U VPX Model 5351 3U VPX Model 5351 3U VPX Model 5351 3U VPX Model 5351 3U VPX


2626262626


32-32-32-32-32-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/DChannel DDC Installed Core with Quad 200 MHz, 16-bit A/D


Figure 37

.

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

PCI 2.2

INTERFACE

MUXDIGITAL

DOWNCONVERTR

BANK 1: CH 1 - 8

DEC: 16 - 8192

CH A

RF In

CH B

RF In

Sample

Clock In

Sync Bus

A/D A

A/D BI & Q

PCI BUS

64 bit /

66 MHz


XC5VSX95T

RF

XFORMR

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

TIMING BUS

GENERATOR

Clock / Gate /

Sync / PPS

XTAL

OSC

PCI 2.2

INTERFACE

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

A/D C

A/D D

BANK 1

MUX

MUX

MUX

M

U

X

M

U

X

M

U

X

M

U

X

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

PPS In

TTL In

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR

BANK 2: CH 9 - 16

DEC: 16 - 8192

DIGITAL

DOWNCONVERTR

BANK 3: CH 17 - 24

DEC: 16 - 8192

DIGITAL

DOWNCONVERTR

BANK 4: CH 25 - 32

DEC: 16 - 8192

A/D B

BANK 2

A/D C

BANK 3

A/D D

BANK 4

8 x 4

CHANNEL

SUMMATION

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

A/D B

I & Q

I & Q

I & Q

SUM

The Model 7152 PMC module is a 4-channel high-speed digitizer with a factory-installed 32-channel DDCcore. The front end of the module accepts four RFinputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7152 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical8-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as theinput source for each DDC bank. Each of the 32 DDCshas an independent 32-bit tuning frequency setting.

All of the 8 channels within a bank share a commondecimation setting that can range from 16 to 8192,programmable in steps of 8. For example, with a samplingrate of 200 MHz, the available output bandwidths rangefrom 19.53 kHz to 10.0 MHz. Each 8-channel bank can

have its own unique decimation setting supporting asmany as four different output bandwidths for the board.

The decimating filter for each DDC bank accepts a uniqueset of user-supplied 18-bit coefficients. The 80% default filtersdeliver an output bandwidth of 0.8*ƒs/N, where N is thedecimation setting. The rejection of adjacent-band componentswithin the 80% output band-width is better than 100 dB.

Each DDC delivers a complex output stream consist-ing of 24-bit I + 24-bit Q samples. Any number of channelscan be enabled within each bank, selectable from 0 to 8.Each bank includes an output sample interleaver thatdelivers a channel-multiplexed stream for all enabledchannels within the bank. Gain and phase control, powermeters and threshold detectors are included.

Versions of the 7152 are also available as a PCIe full-length board (Models 7752 and 7752D dual density), PCIehalf-length board (Model 7852), PCI board (Model 7652),6U cPCI (Models 7252 and 7252D dual density), 3U cPCI(Model 7352), and 3U VPX (Model 5352).



2727272727



Figure 38

Model 7153 is a 4-channel, high-speed software radiomodule designed for processing baseband RF or IF signals.It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter)installed core and a complete set of beamforming functions.With built-in multiboard synchronization and an Auroragigabit serial interface, it provides everything needed forimplementing multichannel beamforming systems.

The Model 7153 employs an advanced FPGA-basedDDC engine consisting of four identical multiband banks.Four independently controllable input multiplexers selectone of the four A/Ds as the input source for each DDCbank. Each of the 4 DDCs has an independent 32-bittuning frequency setting.

All four DDCs have a decimation setting that canrange from 2 to 256, programmable independenly insteps of 1. The decimating filter for each DDC bankaccepts a unique set of user-supplied 18-bit coefficients.The 80% default filters deliver an output bandwidth of

0.8*ƒs/N, where N is the decimation setting. Therejection of adjacent-band components within the 80%output band-width is better than 100 dB.

In addition to the DDCs, the 7153 features a com-plete beamforming subsystem. Each channel containsprogramable I & Q phase and gain adjustments followedby a power meter that continuously measures the individualaverage power output. The time constant of the averaginginterval for each meter is programmable up to 8 ksamples.The power meters present average power measurements foreach channel in easy-to-read registers. Each channel alsoincludes a threshold detector that sends an interrupt tothe processor if the average power level of any DDCfalls below or exceeds a programmable threshold.

Versions of the 7153 are also available as a PCIe full-length board (Models 7753 and 7753D dual density),PCIe half-length board (Model 7853), PCI board (Model7653), 6U cPCI (Models 7253 and 7253D dual density),3U cPCI (Model 7353), and 3U VPX (Model 5353).

.

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

PCI 2.2

INTERFACE

MUXDIGITAL

DOWNCONVERTR

CH 1

DEC: 2 - 256

CH A

RF In

CH B

RF In

Sample

Clock In

Sync Bus

A/D A

A/D BI & Q

PCI BUS

64 bit /

66 MHz


XC5VSX50T

RF

XFORMR

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

TIMING BUS

GENERATOR

Clock / Gate /

Sync / PPS

XTAL

OSC

PCI 2.2

INTERFACE

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

A/D C

A/D D

DDC 1

MUX

MUX

MUX

M

U

X

M

U

X

M

U

X

M

U

X

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

PPS In

TTL In

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR

CH 2

DEC: 2 - 256

DIGITAL

DOWNCONVERTR

CH 3

DEC: 2 - 256

DIGITAL

DOWNCONVERTR

CH 4

DEC: 2 - 256

A/D B

DDC 2

A/D C

DDC 3

A/D D

DDC 4

4

CHANNEL

SUMMATION

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

A/D B

I & Q

I & Q

I & Q

SUM

4-4-4-4-4-Channel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/DsChannel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/DsChannel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/DsChannel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/DsChannel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/Ds

Model 7153 PMC/XMC Model 7153 PMC/XMC Model 7153 PMC/XMC Model 7153 PMC/XMC Model 7153 PMC/XMC ●●●●● Model 7253 6U cPCI Model 7253 6U cPCI Model 7253 6U cPCI Model 7253 6U cPCI Model 7253 6U cPCI ●●●●● Model 7353 3U cPCI Model 7353 3U cPCI Model 7353 3U cPCI Model 7353 3U cPCI Model 7353 3U cPCI ●●●●● Model 7653 PCI Model 7653 PCI Model 7653 PCI Model 7653 PCI Model 7653 PCIModel 7753 FModel 7753 FModel 7753 FModel 7753 FModel 7753 Full-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ●●●●● Model 7853 Half-length PCIe Model 7853 Half-length PCIe Model 7853 Half-length PCIe Model 7853 Half-length PCIe Model 7853 Half-length PCIe ●●●●● Model 5353 3U VPX Model 5353 3U VPX Model 5353 3U VPX Model 5353 3U VPX Model 5353 3U VPX


2828282828



Dual SDR TDual SDR TDual SDR TDual SDR TDual SDR Transceivers with 400 MHz A/D, 800 MHz D/A, and Virransceivers with 400 MHz A/D, 800 MHz D/A, and Virransceivers with 400 MHz A/D, 800 MHz D/A, and Virransceivers with 400 MHz A/D, 800 MHz D/A, and Virransceivers with 400 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAstex-5 FPGAstex-5 FPGAstex-5 FPGAstex-5 FPGAs

Model 7156PMC/XMC

Model 7156 is a dual high-speed data convertersuitable for connection as the HF or IF input of acommunications system. It features two 400 MHz 14-bitA/Ds, a DUC with two 800 MHz 16-bit D/As, andtwo Virtex-5 FPGAs. Model 7156 uses the popularPMC format and supports the VITA 42 XMC standardfor switched fabric interfaces.

The Model 7156 architecture includes two Virtex-5FPGAs. The first FPGA is used primarily for signalprocessing while the second one is dedicated to boardinterfaces. All of the board’s data and control paths areaccessible by the FPGAs, enabling factory installedfunctions such as data multiplexing, channel selection, datapacking, gating, triggering and SDRAM memory control.

Two independent 512 MB banks of DDR2 SDRAMare available to the signal processing FPGA. Built-inmemory functions include an A/D data transient capturemode with pre- and post-triggering. All memory bankscan be easily accessed through the PCI-X interface.

A high-performance IP core wideband DDC may befactory-installed in the processing FPGA.

A 5-channel DMA controller and 64 bit/100 MHz PCI-X interface assures efficient transfers to and from the module.

Two 4X switched serial ports implemented with theXilinx Rocket I/O interfaces, connect the FPGA to theXMC connector with two 2.5 GB/sec data links to thecarrier board.

A dual bus system timing generator allows forsample clock synchronization to an external systemreference. It also supports large, multichannel appli-cations where the relative phases must be preserved.

Versions of the 7156 are also available as a PCIe full-length board (Models 7756 and 7756D dual density),PCIe half-length board (Model 7856), PCI board(Model 7656), 6U cPCI (Models 7256 and 7256D dualdensity), 3U cPCI (Model 7356), and 3U VPX (Model5356). All these products have similar features.

Figure 39

Model 7156 PMC/XMC Model 7156 PMC/XMC Model 7156 PMC/XMC Model 7156 PMC/XMC Model 7156 PMC/XMC ●●●●● Model 7256 6U cPCI Model 7256 6U cPCI Model 7256 6U cPCI Model 7256 6U cPCI Model 7256 6U cPCI ●●●●● Model 7356 3U cPCI Model 7356 3U cPCI Model 7356 3U cPCI Model 7356 3U cPCI Model 7356 3U cPCI ●●●●● Model 7656 PCI Model 7656 PCI Model 7656 PCI Model 7656 PCI Model 7656 PCIModel 7756 FModel 7756 FModel 7756 FModel 7756 FModel 7756 Full-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ●●●●● Model 7856 Half-length PCIe Model 7856 Half-length PCIe Model 7856 Half-length PCIe Model 7856 Half-length PCIe Model 7856 Half-length PCIe ●●●●● Model 5356 3U VPX Model 5356 3U VPX Model 5356 3U VPX Model 5356 3U VPX Model 5356 3U VPX

RF In

14

ADS5474

400 MHz

14-bit A/D

RF

XFORMR

RF In

14

ADS5474

400 MHz

14-bit A/D

RF

XFORMR

TIMING BUS

GENERATOR

Clock/ Sync /

Gate / PPS

Sample Clock In

TTL Gate / Trig

A/D Clock Bus

TTL Sync / PPS

Sample Clk

Sync Clk

Gate A

Gate B

Sync

PPS

PPS In

PROCESSING FPGA

VIRTEX –5: LX50T, SX50T, SX95T or FX100TTo All

Sections

Control/

Status

VCXO

GTP GTP GTP

INTERFACE FPGA

VIRTEX-5: LX30T, SX50T or FX70T

PCI-X BUS

(64 Bits

133 MHz)

P15 XMC

VITA 42.x

(PCIe, etc.)

P4 PMC

FPGA

I/O

64

32

4X

4X

4X4X

GTP

PCI-X GTP

1632 32

DDR 2

SDRAM

512 MB

DDR 2

SDRAM

512 MB

FLASH

32 MB

32

LVDS

LVDS

Timing Bus

D/A Clock Bus

32

RF

XFORMR

RF

XFORMR

RF Out RF Out

DIGITAL UPCONVERTER

800 MHz

16-bit D/A

800 MHz

16-bit D/A

64


2929292929


Model 7158 is a dual high-speed data convertersuitable for connection as the HF or IF input of acommunications system. It features two 500 MHz 12-bitA/Ds, a digital upconverter with two 800 MHz 16-bitD/As, and two Virtex-5 FPGAs. Model 7158 uses thepopular PMC format and supports the VITA 42 XMCstandard for switched fabric interfaces.

The Model 7158 architecture includes two Virtex-5FPGAs. The first FPGA is used primarily for signalprocessing while the second one is dedicated to boardinterfaces. All of the board’s data and control paths areaccessible by the FPGAs, enabling factory installedfunctions such as data multiplexing, channel selection, datapacking, gating, triggering and SDRAM memory control.

Two independent 256 MB banks of DDR2 SDRAMare available to the signal processing FPGA. Built-inmemory functions include an A/D data transient capturemode with pre- and post-triggering. All memory bankscan be easily accessed through the PCI-X interface.

A 5-channel DMA controller and 64 bit / 100 MHzPCI-X interface assures efficient transfers to and from themodule.

Two 4X switched serial ports implemented with theXilinx Rocket I/O interfaces, connect the FPGA to theXMC connector with two 2.5 GB/sec data links to thecarrier board.

A dual bus system timing generator allows forsample clock synchronization to an external systemreference. It also supports large, multichannel appli-cations where the relative phases must be preserved.

Versions of the 7158 are also available as a PCIe full-length board (Models 7758 and 7758D dual density),PCIe half-length board (Model 7858), PCI board(Model 7658), 6U cPCI (Models 7258 and 7258D dualdensity), 3U cPCI (Model 7358), and 3U VPX (Model5358). All these products have similar features.

Dual SDR TDual SDR TDual SDR TDual SDR TDual SDR Transceivers with 500 MHz A/D, 800 MHz D/A, and Virransceivers with 500 MHz A/D, 800 MHz D/A, and Virransceivers with 500 MHz A/D, 800 MHz D/A, and Virransceivers with 500 MHz A/D, 800 MHz D/A, and Virransceivers with 500 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAstex-5 FPGAstex-5 FPGAstex-5 FPGAstex-5 FPGAs

Figure 40


Model 7158PMC/XMC

RF In

14

ADS5463

500 MHz

12-bit A/D

RF

XFORMR

RF In

14

ADS5463

500 MHz

12-bit A/D

RF

XFORMR

TIMING BUS

GENERATOR

Clock/ Sync /

Gate / PPS

Sample Clock /

Reference Clock In

TTL Gate / Trig

A/D Clock Bus

TTL Sync / PPS

Sample Clk

Sync Clk

Gate A

Gate B

Sync

PPS

PPS In

PROCESSING FPGA

VIRTEX –5: LX50T, LX155T, SX50T, SX95T or FX100TTo All

Sections

Control/

Status

VCXO

GTP GTP GTP

INTERFACE FPGA

VIRTEX-5: LX30T, SX50T or FX70T

PCI-X BUS

(64 Bits

100 MHz)

P15 XMC

VITA 42.x

(PCIe, etc.)

P4 PMC

FPGA

I/O

64

32

4X

4X

4X4X

GTP

PCI-X GTP

1632 32

DDR 2

SDRAM

256 MB

DDR 2

SDRAM

256 MB

FLASH

32 MB

32

LVDS

LVDS

Timing Bus

D/A Clock Bus

32

RF

XFORMR

RF

XFORMR

RF Out RF Out

DIGITAL UPCONVERTER

800 MHz

16-bit D/A

800 MHz

16-bit D/A

64

Model 7158 PMC/XMC Model 7158 PMC/XMC Model 7158 PMC/XMC Model 7158 PMC/XMC Model 7158 PMC/XMC ●●●●● Model 7258 6U cPCI Model 7258 6U cPCI Model 7258 6U cPCI Model 7258 6U cPCI Model 7258 6U cPCI ●●●●● Model 7358 3U cPCI Model 7358 3U cPCI Model 7358 3U cPCI Model 7358 3U cPCI Model 7358 3U cPCI ● ● ● ● ● Model 7658 PCIModel 7658 PCIModel 7658 PCIModel 7658 PCIModel 7658 PCIModel 7758 FModel 7758 FModel 7758 FModel 7758 FModel 7758 Full-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ull-length PCIe ●●●●● Model 7858 Half-length PCIe Model 7858 Half-length PCIe Model 7858 Half-length PCIe Model 7858 Half-length PCIe Model 7858 Half-length PCIe ●●●●● Model 5358 3U VPX Model 5358 3U VPX Model 5358 3U VPX Model 5358 3U VPX Model 5358 3U VPX


3030303030


3-3-3-3-3-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 71620 XMC Model 71620 XMC Model 71620 XMC Model 71620 XMC Model 71620 XMC ●●●●● Model 78620 Half-length PCIe Model 78620 Half-length PCIe Model 78620 Half-length PCIe Model 78620 Half-length PCIe Model 78620 Half-length PCIe ●●●●● Model 53620 3U VPX Model 53620 3U VPX Model 53620 3U VPX Model 53620 3U VPX Model 53620 3U VPXModel 72620 6U cPCI Model 72620 6U cPCI Model 72620 6U cPCI Model 72620 6U cPCI Model 72620 6U cPCI ● ● ● ● ● Model 73620 3U cPCI Model 73620 3U cPCI Model 73620 3U cPCI Model 73620 3U cPCI Model 73620 3U cPCI ● ● ● ● ● Model 74620 6U cPCIModel 74620 6U cPCIModel 74620 6U cPCIModel 74620 6U cPCIModel 74620 6U cPCI

Figure 41


Model 71620XMC

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS

VCXO

200 MHz16-BIT A/D

RFXFORMR

RFXFORMR

VIRTEX-6 FPGA

LX130T, LX240T, LX365T, SX315T or SX475T

16

QDRII+SRAM8 MB

TTL Gate / TrigTTL Sync / PPS

Sample ClkReset

Gate A/DGate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

200 MHz16-BIT A/D

Sample Clk /Reference Clk In

800 MHz16-BIT D/A

RFXFORMR

321616

RFXFORMR

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RFXFORMR

200 MHz16-BIT A/D

16

Memory Banks 1 & 2 Memory Banks 3 & 4

DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In RF In RF In RF OutRF Out

D/AClock/Sync

Bus

A/DClock/Sync

Bus

RFXFORMR

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

Model 71620 is a member of the Cobalt® family ofhigh performance XMC modules based on the XilinxVirtex-6 FPGA. A multichannel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkey solution.It includes three 200 MHz, 16-bit A/Ds, a DUC withtwo 800 MHz, 16-bit D/As and four banks of memory.In addition to supporting PCI Express Gen. 2 as anative interface, the Model 71620 includes generalpurpose and gigabit serial connectors for application-specific I/O .

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architec-ture organizes the FPGA as a container for data processingapplications where each function exists as an intellec-tual property (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 71620 factory-installedfunctions include an A/D acquisition and a D/A waveformplayback IP module. In addition, IP modules for eitherDDR3 or QDRII+ memories, a controller for all dataclocking and synchronization functions, a test signalgenerator and a PCIe interface complete the factory-installed functions.

Multiple 71620’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected modules. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or as combina-tion of two banks of each type of memory.

Versions of the 71620 are also available as a PCIe half-length board (Model 78620), 3U VPX (Model 53620), 6UcPCI (Models 72620 and 74620 dual density), and 3UcPCI (Model 73620).


3131313131


PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

PCIe

8Xfrom previousboard

to nextboard

sum out

sum in

VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

A/DACQUISITIONIP MODULE 1



LINKED-LISTDMA ENGINE



METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

MUX MUX MUX

DATA PACKING &FLOW CONTROL



AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�

SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

BEAMFORMER CORE

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE

D/AWAVEFORMPLAYBACKIP MODULE

toD/A

D/A loopbackTEST

SIGNALGENERATOR

MUX


toMem

Bank 4

MEMORYCONTROL


DATA UNPACKING& FLOW CONTROL

INTERPOLATOR2 TO 65536

IP CORE

8X4X 4X

3-3-3-3-3-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP CoresChannel 800 MHz D/A, Installed IP CoresChannel 800 MHz D/A, Installed IP CoresChannel 800 MHz D/A, Installed IP CoresChannel 800 MHz D/A, Installed IP Cores


Figure 42

Model 71621XMC


Model 71621 is a member of the Cobalt family of highperformance XMC modules based on the Xilinx Virtex-6FPGA. A multichannel, high-speed data converter based onthe Model 71620 described in the previous page, it includesfactory-installed IP cores to enhance the performance of the71620 and address the requirements of many applications.

The 71621 factory-installed functions include three A/Dacquisition and one D/A waveform playback IP modules.Each of the three acquisition IP modules contains apowerful, programmable DDC IP core. The waveformplayback IP module contains an interpolation IP core, idealfor matching playback rates to the data and decimationrates of the acquisition modules. IP modules for eitherDDR3 or QDRII+ memories, a controller for all dataclocking and synchronization functions, a test signalgenerator, an Aurora gigabit serial interface, and a PCIeinterface complete the factory-installed functions.

Each DDC has an independent 32-bit tuningfrequency setting that ranges from DC to ƒs, where ƒs is

the A/D sampling frequency. Each DDC can have itsown unique decimation setting, supporting as many asthree different output bandwidths for the board. Decima-tions can be programmed from 2 to 65,536 providing awide range to satisfy most applications.

The 71621 also features a complete beamformingsubsystem. Each DDC core contains programable I & Qphase and gain adjustments followed by a power meterthat continuously measures the individual average poweroutput. The power meters present average power measure-ments for each DDC core output in easy-to-read registers. Athreshold detector automatically sends an interrupt tothe processor if the average power level of any DDCcore falls below or exceeds a programmable threshold.



3232323232


1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 78630 Half-length PCIe Model 78630 Half-length PCIe Model 78630 Half-length PCIe Model 78630 Half-length PCIe Model 78630 Half-length PCIe ● ● ● ● ● Model 71630 XMC Model 71630 XMC Model 71630 XMC Model 71630 XMC Model 71630 XMC ●●●●● Model 53630 3U VPX Model 53630 3U VPX Model 53630 3U VPX Model 53630 3U VPX Model 53630 3U VPXModel 72630 6U cPCI Model 72630 6U cPCI Model 72630 6U cPCI Model 72630 6U cPCI Model 72630 6U cPCI ● ● ● ● ● Model 73630 3U cPCI Model 73630 3U cPCI Model 73630 3U cPCI Model 73630 3U cPCI Model 73630 3U cPCI ● ● ● ● ● Model 74630 6U cPCIModel 74630 6U cPCIModel 74630 6U cPCIModel 74630 6U cPCIModel 74630 6U cPCI

Figure 43


Model 78630half-length PCIe

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS D/A Clock/Sync Bus

VCXO

VIRTEX-6 FPGA


16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

x8 PCIe

8X

GTX

x8 PCI Express

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDS

FPGAGPIO

(option 104)

P14PMC

P16XMC

Model 78630 is a member of the Cobalt family of highperformance PCIe boards based on the Xilinx Virtex-6FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communications or radarsystem. Its built-in data capture and playback features offeran ideal turnkey solution as well as a platform for develop-ing and deploying custom FPGA processing IP. It includes1 GHz, 12-bit A/D, 1 GHz, 16-bit D/A converters andfour banks of memory. In addition to supporting PCIExpress Gen. 2 as a native interface, the Model 78630includes optional general purpose and gigabit serial cardconnectors for application- specific I/O protocols.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architec-ture organizes the FPGA as a container for data process-ing applications where each function exists as an intellec-tual property (IP) module.


Multiple 78630’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected boards. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or as combina-tion of two banks of each type of memory.

Versions of the 78630 are also available as an XMCmodule (Model 71630), 3U VPX (Model 53630), 6U cPCI(Models 72630 and 74630 dual density), and 3U cPCI(Model 73630).


3333333333


Figure 44


TIMING BUSGENERATOR


VIRTEX-6 FPGA


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

3.6 GHz (1 Channel)or

1.8 GHz (2 Channel)12-bit A/D

12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

Block Diagram, Model 72640

Model 74640 doubles all resources

except the PCI-to-PCI Bridge

VIRTEX-6 FPGA

MODEL 73640

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX

OptionalFPGA I/O(option 104)

PCI/PCI-X BUS32-bit, 33/66 MHz

J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40

OptionalSerial I/O(option 105)

OptionalSerial I/O(option 105)

From/To OtherXMC Module ofMODEL 74640

4X

GTX

4X

GTXLVDS GTX

OptionalFPGA I/O

(option 104)

OptionalFPGA I/O

(option 104)

One Other

x4 PCIe

PCI/PCI-X BUS32/64-bit, 33/66 MHz

4X

J3or the

Model 74640Dual Density

Model 73640Single Density

Model 72640 6U cPCI Model 72640 6U cPCI Model 72640 6U cPCI Model 72640 6U cPCI Model 72640 6U cPCI ● ● ● ● ● Model 73640 3U cPCI Model 73640 3U cPCI Model 73640 3U cPCI Model 73640 3U cPCI Model 73640 3U cPCI ● ● ● ● ● Model 74640 6U cPCIModel 74640 6U cPCIModel 74640 6U cPCIModel 74640 6U cPCIModel 74640 6U cPCIModel 71640 XMC Model 71640 XMC Model 71640 XMC Model 71640 XMC Model 71640 XMC ●●●●● Model 78640 Half-length PCIe Model 78640 Half-length PCIe Model 78640 Half-length PCIe Model 78640 Half-length PCIe Model 78640 Half-length PCIe ●●●●● Model 53640 3U VPX Model 53640 3U VPX Model 53640 3U VPX Model 53640 3U VPX Model 53640 3U VPX

1- or 2-1- or 2-1- or 2-1- or 2-1- or 2-Channel 3.6 GHz and 2- or 4-Channel 3.6 GHz and 2- or 4-Channel 3.6 GHz and 2- or 4-Channel 3.6 GHz and 2- or 4-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 72640, 73640 and 74640 are membersof the Cobalt family of high performance CompactPCIboards based on the Xilinx Virtex-6 FPGA. Theyconsist of one or two Model 71640 XMC modulesmounted on a cPCI carrier board. These models include oneor two 3.6 GHz, 12-bit A/D converters and four or eightbanks of memory.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installedfunctions including data multiplexing, channel selec-tion, data packing, gating, triggering and memory control.The Cobalt architecture organizes the FPGA as a containerfor data processing applications where each function existsas an intellectual property (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The factory-installed functions ofthese models include one or two A/D acquisition IP

modules. In addition, IP modules for DDR3 memories,controllers for all data clocking and synchronizationfunctions, a test signal generator and a PCIe interfacecomplete the factory-installed functions.

The front end accepts analog HF or IF inputs ona pair of front panel SSMC connectors with transformercoupling into a National Semiconductor ADC12D180012-bit A/D. The converter operates in single-channelinterleaved mode with a sampling rate of 3.6 GHz andan input bandwidth of 1.75 GHz; or, in dual-channelmode with a sampling rate of 1.8 GHz and input band-width of 2.8 GHz. The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing these models to havea full scale input range of +2 dBm to +4 dBm.

Model 72640 is a 6U cPCI board, while Model73640 is a 3U cPCI board; Model 74640 is a dualdensity 6U cPCI board. Also available is an XMC module(Model 71640), PCIe half-length board (Model 78640),and 3U VPX (Model 53640).


3434343434


2-2-2-2-2-Channel 500 MHz A/D, DUC, 2-Channel 500 MHz A/D, DUC, 2-Channel 500 MHz A/D, DUC, 2-Channel 500 MHz A/D, DUC, 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 53650 3U VPX Model 53650 3U VPX Model 53650 3U VPX Model 53650 3U VPX Model 53650 3U VPX ●●●●● Model 71650 XMC Model 71650 XMC Model 71650 XMC Model 71650 XMC Model 71650 XMC ● ● ● ● ● Model 78650 Half-length PCIeModel 78650 Half-length PCIeModel 78650 Half-length PCIeModel 78650 Half-length PCIeModel 78650 Half-length PCIeModel 72650 6U cPCI Model 72650 6U cPCI Model 72650 6U cPCI Model 72650 6U cPCI Model 72650 6U cPCI ● ● ● ● ● Model 73650 3U cPCI Model 73650 3U cPCI Model 73650 3U cPCI Model 73650 3U cPCI Model 73650 3U cPCI ●●●●● Model 74650 6U cPCI Model 74650 6U cPCI Model 74650 6U cPCI Model 74650 6U cPCI Model 74650 6U cPCI

Figure 45

Model 53650 3U VPXCOTS and rugged


D/AClock/Sync

Bus

VCXO

500 MHz12-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-6 FPGA


16

QDRII+SRAM8 MB

TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

500 MHz12-BIT A/D

Sample Clk /Reference Clk In A/D

Clock/SyncBus 800 MHz

16-BIT D/A

RFXFORMR

321616

RF Out

RFXFORMR

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

TTLPPS/Gate/Sync

TIMING BUSGENERATOR


LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

Model 53650 is a member of the Cobalt family ofhigh performance 3U VPX boards based on the XilinxVirtex-6 FPGA. A two-channel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkeysolution as well as a platform for developing and deployingcustom FPGA processing IP. The 53650 includes two500 MHz 12-bit A/Ds, one DUC, two 800 MHz 16-bitD/As and four banks of memory. It features built-insupport for PCI Express over the 3U VPX backplane.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architec-ture organizes the FPGA as a container for data process-ing applications where each function exists as an intellec-tual property (IP) module.


Multiple 53650’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected boards. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or as combina-tion of two banks of each type of memory.

Versions of the 53650 are also available as an XMCmodule (Model 71650), as a PCIe half-length board (Model78650), 6U cPCI (Models 72650 and 74650 dual density),and 3U cPCI (Model 73650).

This Model is alsoavailable with 400 MHz,

14-bit A/Ds


3535353535


Model 72651 6U cPCI Model 72651 6U cPCI Model 72651 6U cPCI Model 72651 6U cPCI Model 72651 6U cPCI ● ● ● ● ● Model 73651 3U cPCI Model 73651 3U cPCI Model 73651 3U cPCI Model 73651 3U cPCI Model 73651 3U cPCI ● ● ● ● ● Model 74651 6U cPCIModel 74651 6U cPCIModel 74651 6U cPCIModel 74651 6U cPCIModel 74651 6U cPCIModel 53651 3U VPX Model 53651 3U VPX Model 53651 3U VPX Model 53651 3U VPX Model 53651 3U VPX ● ● ● ● ● Model 71651 XMC Model 71651 XMC Model 71651 XMC Model 71651 XMC Model 71651 XMC ●●●●● Model 78651 Half-length PCIe Model 78651 Half-length PCIe Model 78651 Half-length PCIe Model 78651 Half-length PCIe Model 78651 Half-length PCIe


2- or 4-2- or 4-2- or 4-2- or 4-2- or 4-Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-Channel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Figure 46

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

PCIe


to nextboard

sum out

sum in






METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

MUX MUX



AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�SUMMER

DDCDEC: 2 TO 131027

DDCDEC: 2 TO 131027

BEAMFORMER CORE

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE

D/AWAVEFORMPLAYBACKIP MODULE

toD/A

D/A loopbackTEST

SIGNALGENERATOR

MUX


toMem

Bank 4

MEMORYCONTROL

DATA UNPACKING& FLOW CONTROL

INTERPOLATOR2 TO 65536

IP CORE

4X 4X

Model 74651Dual Density

Model 73651Single Density

Models 72651, 73651 and 74651 are members ofthe Cobalt family of high performance CompactPCI boardsbased on the Xilinx Virtex-6 FPGA. They consist ofone or two Model 71651 XMC modules mounted on acPCI carrier board. These models include two or four A/Ds,two or four multiband DDCs, one ot two DUCs, twoor four D/As and three or six banks of memory.

These models feature two or four A/D Acquisition IPmodules for easily capturing and moving data. Eachmodule can receive data from either of the two A/Ds, atest signal generator or from the D/A Waveform PlaybackIP module in loopback mode.

Within each A/D Acquisition IP Module is apowerful DDC IP core. Because of the flexible inputrouting of the A/D Acquisition IP Modules, many differentconfigurations can be achieved including one A/D drivingboth DDCs or each of the two A/Ds driving its own DDC.

Each DDC has an independent 32-bit tuningfrequency setting that ranges from DC to ƒs, where ƒs is

the A/D sampling frequency. Each DDC can have itsown unique decimation setting, supporting as many astwo or four different output bandwidths for the board.Decimations can be programmed from 2 to 131,072providing a wide range to satisfy most applications.

In addition to the DDCs, these models feature oneor two complete beamforming subsystems. Each DDCcore contains programable I & Q phase and gain adjust-ments followed by a power meter that continuouslymeasures the individual average power output. The timeconstant of the averaging interval for each meter is program-mable up to 8K samples. The power meters present averagepower measurements for each DDC core output in easy-to-read registers.

Model 72651 is a 6U cPCI board, while Model73651 is a 3U cPCI board; Model 74651 is a dualdensity 6U cPCI board. Also available is an XMC module(Model 71651), PCIe half-length board (Model 78651),and 3U VPX (Model 53651).


3636363636



Figure 47

4-4-4-4-4-Channel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA


Model 71660XMC

TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-6 FPGA


16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16

Gate / Trigger /Sync / PPS

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

Model 71660 is a member of the Cobalt family ofhigh performance XMC modules based on the XilinxVirtex-6 FPGA. A multichannel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkey solutionas well as a platform for developing and deploying customFPGA processing IP. It includes four 200 MHz, 16-bit A/Dsand four banks of memory. In addition to supportingPCI Express Gen. 2 as a native interface, the Model71660 includes general purpose and gigabit serial connec-tors for application-specific I/O .


Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 71660 factory-installedfunctions include four A/D acquisition IP modules. Inaddition, IP modules for either DDR3 or QDRII+memories, a controller for all data clocking and syn-chronization functions, a test signal generator and aPCIe interface complete the factory-installed functions.

Multiple 71660’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected modules. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or as combina-tion of two banks of each type of memory.



3737373737



Figure 48

4-4-4-4-4-Channel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP Cores


Model 71661XMC

BEAMFORMER CORE

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe


to nextboard

sum out

sum in










METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX





AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�

SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR



8X4X 4X

Model 71661 is a member of the Cobalt family of highperformance XMC modules based on the Xilinx Virtex-6FPGA. A multichannel, high-speed data converter based onthe Model 71660 described in the previous page, it includesfactory-installed IP cores to enhance the performance of the71620 and address the requirements of many applications.

The 71661 factory-installed functions include four A/Dacquisition IP modules. Each of the four acquisition IPmodules contains a powerful, programmable DDC IPcore. IP modules for either DDR3 or QDRII+ memo-ries, a controller for all data clocking and synchronizationfunctions, a test signal generator, an Aurora gigabitserial interface, and a PCIe interface complete thefactory-installed functions.

Each DDC has an independent 32-bit tuningfrequency setting that ranges from DC to ƒs, where ƒs isthe A/D sampling frequency. Each DDC can have itsown unique decimation setting, supporting as many asfour different output bandwidths for the board. Decima-

tions can be programmed from 2 to 65,536 providing awide range to satisfy most applications.

The 71661 also features a complete beamformingsubsystem. Each DDC core contains programable I & Qphase and gain adjustments followed by a power meterthat continuously measures the individual average poweroutput. The power meters present average power measure-ments for each DDC core output in easy-to-read registers. Athreshold detector automatically sends an interrupt tothe processor if the average power level of any DDCcore falls below or exceeds a programmable threshold.

For larger systems, multiple 71661’s can be chainedtogether via the built-in Xilinx Aurora gigabit serialinterface through the P16 XMC connector.



3838383838


Figure 49


4-4-4-4-4-Channel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP CoresChannel 200 MHz 16-bit A/D with Installed IP Cores

Model 78662 Half-length PCIe Model 78662 Half-length PCIe Model 78662 Half-length PCIe Model 78662 Half-length PCIe Model 78662 Half-length PCIe ●●●●● Model 71662 XMC Model 71662 XMC Model 71662 XMC Model 71662 XMC Model 71662 XMC ●●●●● Model 53662 3U VPX Model 53662 3U VPX Model 53662 3U VPX Model 53662 3U VPX Model 53662 3U VPXModel 72662 6U cPCI Model 72662 6U cPCI Model 72662 6U cPCI Model 72662 6U cPCI Model 72662 6U cPCI ● ● ● ● ● Model 73662 3U cPCI Model 73662 3U cPCI Model 73662 3U cPCI Model 73662 3U cPCI Model 73662 3U cPCI ● ● ● ● ● Model 74662 6U cPCIModel 74662 6U cPCIModel 74662 6U cPCIModel 74662 6U cPCIModel 74662 6U cPCI

Model 78662 is a member of the Cobalt family ofhigh performance PCIe boards based on the Xilinx Virtex-6FPGA. Based on the Model 71660 presented previously,this four-channel, high-speed data converter withprogrammable DDCs is suitable for connection to HF orIF ports of a communications or radar system.

The 78662 factory-installed functions include four A/Dacquisition IP modules. Each of the four acquisition IPmodules contains a powerful, programmable 8-channelDDC IP core. IP modules for either DDR3 or QDRII+memories, a controller for all data clocking and synchroni-zation functions, a test signal generator, voltage andtemperature monitoring, and a PCIe interface complete thefactory-installed functions.

Each of the 32 DDC channels has an independent32-bit tuning frequency setting that ranges from DC toƒs, where ƒs is the A/D sampling frequency. All of the8 channels within a bank share a common decimationsetting ranging from 16 to 8192 programmable in steps

of eight. Each 8-channel bank can have its own uniquedecimation setting supporting a different bandwidthassociated with each of the four acquisition modules.

The decimating filter for each DDC bank acceptsa unique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% outputbandwidth is better than 100 dB.

Each DDC delivers a complex output stream consistingof 24-bit I + 24-bit Q samples at a rate of ƒs/N. Anynumber of channels can be enabled within each bank,selectable from 0 to 8. Multiple 78662’s can be drivenfrom the LVPECL bus master, supporting synchronoussampling and sync functions across all connected boards.

Versions of the 78662 are also available as an XMCmodule (Model 71662), 3U VPX (Model 53662), 6UcPCI (Models 72662 and 74662 dual density), and 3UcPCI (Model 73662).

Model 78662half-length PCIe

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4








METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX





INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR



DDCCORE

DIGITALDOWN-

CONVERTER

BANK 1: CH 1-8DEC: 16 TO 8192

.

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 2: CH 9-16DEC: 16 TO 8192

.

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 3: CH 17-24DEC: 16 TO 8192

.

DDCCORE

DIGITALDOWN-

CONVERTER

BANK 4: CH 18-32DEC: 16 TO 8192

.

MemoryBank 4

PCIe INTERFACE

PCIe8X



GigabitSerial I/O

FPGAGPIO

(supports user installed IP)

4X 4X 4032MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32


3939393939


Figure 50

4-4-4-4-4-Channel 1.25 GHz D/A with DUC, VirChannel 1.25 GHz D/A with DUC, VirChannel 1.25 GHz D/A with DUC, VirChannel 1.25 GHz D/A with DUC, VirChannel 1.25 GHz D/A with DUC, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA


TIMING BUSGENERATOR


VCXOVIRTEX-6 FPGA


16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

Model 71670XMC

Model 71670 is a member of the Cobalt family ofhigh performance XMC modules based on the XilinxVirtex-6 FPGA. This 4-channel, high-speed dataconverter is suitable for connection to transmit HF or IFports of a communications or radar system. Its built-indata playback features offer an ideal turnkey solutionfor demanding transmit applications. It includes fourD/As, four digital upconverters and four banks ofmemory. In addition to supporting PCI Express Gen. 2 asa native interface, the Model 71670 includes generalpurpose and gigabit serial connectors for application-specific I/O .

The Pentek Cobalt Architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installedfunctions including data multiplexing, channel selection,data packing, gating, triggering and memory control.The Cobalt Architecture organizes the FPGA as acontainer for data processing applications where eachfunction exists as an intellectual property (IP) module.

Each member of the Cobalt family is delivered withfactory-installed applications ideally matched to the board’sanalog interfaces. The 71670 factory-installed functionsinclude four D/A waveform playback IP modules, to supportwaveform generation through the D/A converters. IP modulesfor DDR3 SDRAM memories, a controller for all dataclocking and synchronization functions, a test signal generator,and a PCIe interface complete the factory-installed functionsand enable the 71670 to operate as a complete turnkeysolution, without the need to develop any FPGA IP.

The Model 71670 factory-installed functionsinclude a sophisticated D/A Waveform Playback IPmodule. Four linked list controllers support waveformgeneration to the four D/As from tables stored in eitheron-board memory or off-board host memory.




4040404040


LLLLL-Band RF T-Band RF T-Band RF T-Band RF T-Band RF Tuner with 2-uner with 2-uner with 2-uner with 2-uner with 2-Channel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 53690 3U VPX Model 53690 3U VPX Model 53690 3U VPX Model 53690 3U VPX Model 53690 3U VPX ●●●●● Model 71690 XMC Model 71690 XMC Model 71690 XMC Model 71690 XMC Model 71690 XMC ●●●●● Model 78690 Half-length PCIe Model 78690 Half-length PCIe Model 78690 Half-length PCIe Model 78690 Half-length PCIe Model 78690 Half-length PCIeModel 72690 6U cPCI Model 72690 6U cPCI Model 72690 6U cPCI Model 72690 6U cPCI Model 72690 6U cPCI ● ● ● ● ● Model 73690 3U cPCI Model 73690 3U cPCI Model 73690 3U cPCI Model 73690 3U cPCI Model 73690 3U cPCI ● ● ● ● ● Model 74690 6U cPCIModel 74690 6U cPCIModel 74690 6U cPCIModel 74690 6U cPCIModel 74690 6U cPCI

Figure 51


Model 53690 3U VPXCOTS and rugged

VCXOVIRTEX-6 FPGA


16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

XTALOSC

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


RefOption 100

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTXLVDS

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

4X8X 4X

x8PCIe

Model 53690 is a member of the Cobalt family ofhigh performance 3U VPX boards based on the XilinxVirtex-6 FPGA. A 2-Channel high-speed data converter,it is suitable for connection directly to the RF port of acommunications or radar system. Its built-in data capturefeatures offer an ideal turnkey solution. The Model 53690includes an L-Band RF tuner, two 200 MHz, 16-bitA/Ds and four banks of memory. It features built-insupport for PCI Express over the 3U VPX backplane.


Each member of the Cobalt family is delivered withfactory-installed applications ideally matched to the

board’s analog interfaces. The 53690 factory-installedfunctions include two A/D acquisition IP modules. IPmodules for either DDR3 or QDRII+ memories, acontroller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interfacecomplete the factory-installed functions.

A front panel connector accepts L-Band signalsbetween 925 MHz and 2175 MHz from an antennaLNB. A Maxim MAX2112 tuner directly convertsthese signals to baseband using a broadband I/Qdownconverter. The device includes an RF variable-gain LNA (low-noise amplifier), a PLL synthesizedlocal oscillator, quadrature (I + Q) downconvertingmixers, baseband lowpass filters and variable-gainbaseband amplifiers.

Versions of the 53690 are also available as an XMCmodule (Model 71690), as a PCIe half-length board (Model78690), 6U cPCI (Models 72690 and 74690 dual density),and 3U cPCI (Model 73690).


4141414141


4-4-4-4-4-Channel 200 MHz, 16-bit A/D with VirChannel 200 MHz, 16-bit A/D with VirChannel 200 MHz, 16-bit A/D with VirChannel 200 MHz, 16-bit A/D with VirChannel 200 MHz, 16-bit A/D with Virtex-7 FPGAtex-7 FPGAtex-7 FPGAtex-7 FPGAtex-7 FPGA


Figure 52


Model 71760XMC

TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T, VX485T or VX690T

32


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16

ConfigFLASH128 MB

32

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

3232

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16

Gate / Trigger /Sync / PPS

48

GigabitSerial I/O

(option 105)

4X

GTX

4X8X

GTX LVDSGTX

FPGAGPIO

(option 104)

P14PMC

P16XMC

P15XMC

PCIeGen3 x8

Model 71760 is a member of the OnyxTM family ofhigh performance XMC modules based on the XilinxVirtex-7 FPGA. A multichannel, high-speed data converter,it is suitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capturefeatures offer an ideal turnkey solution as well as aplatform for developing and deploying custom FPGAprocessing IP. It includes four A/Ds and four banks ofmemory. In addition to supporting PCI Express Gen. 3 as anative interface, the Model 71760 includes general purposeand gigabit serial connectors for application-specific I/O.

Based on the proven design of the Pentek Cobalt family,Onyx raises the processing performance with the new flagshipfamily of Virtex-7 FPGAs from Xilinx. As the central feature ofthe board architecture, the FPGA has access to all data andcontrol paths, enabling factory-installed functions including datamultiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes theFPGA as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.

Each member of the Onyx family is delivered with factory-installed applications ideally matched to the board’s analoginterfaces. The 71760 factory-installed functions include fourA/D acquisition IP modules for simplifying data capture anddata tranfer. IP modules for DDR3 SDRAM memories, acontroller for all data clocking and synchronization functions, atest signal generator, and a PCIe interface complete the factory-installed functions and enable the 71760 to operate as a completeturnkey solution without the need to develop any FPGA IP.

The 71760 architecture supports four independentDDR3 SDRAM memory banks. Each bank is 1 GB deepand is an integral part of the module’s DMA capabili-ties, providing FIFO memory space for creating DMApackets. Built-in memory functions include multichannelA/D data capture, tagging and streaming.



4242424242


215 MHz, 12-bit A/D with W215 MHz, 12-bit A/D with W215 MHz, 12-bit A/D with W215 MHz, 12-bit A/D with W215 MHz, 12-bit A/D with Wideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXS

The Model 6821 is a 6U single slot board with theAD9430 12-bit, 215 MHz A/D converter.

Capable of digitizing input signal bandwidths up to100 MHz, it is ideal for wideband applications includ-ing radar and spread spectrum communication systems.

The sampling clock can be supplied either from afront panel input or from an internal crystal oscillator.Data from the A/D converter flows into two XilinxVirtex-II Pro FPGAs where optional signal processingfunctions can be performed. The size of the FPGAs canrange from the XC2VP20 to the XC2VP50.

Because the sampling rate is well beyond conven-tional ASIC digital downconverters, none are includedon the board.

Instead, the Pentek GateFlow IP Core 422 UltraWideband Digital Downconverter can be factory-

installed in one or both of the FPGAs to perform thisfunction.

Two 128 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking receivers.

Either two or four FPDP-II ports connect the FPGAsto external digital destinations such as processor boards,memory boards or storage devices.

A VMEbus interface supports configuration of theFPGAs over the backplane and also provides data andcontrol paths for runtime applications. A VXS interfaceis optionally available.

This Model is available in commercial as well asconduction-cooled versions.

Figure 53

Model 6821-422Model 6821-422Model 6821-422Model 6821-422Model 6821-422


128kFIFO

FPDP-IIOut CSlot 2

FPDP-IIOut BSlot 1

32 32

128kFIFO

FPDP-IIOut DSlot 2

32 32

128kFIFO

FPDP-IIOut ASlot 1

32 32

32 32

128kFIFO

16 MB

FLASH

16

128 MB

SDRAM

32

16 MB

FLASH

16

128 MB

SDRAM

32

XILINX

VIRTEX-II

PRO FPGA

XC2VP50

64

XILINX

VIRTEX-II

PRO FPGA

XC2VP50

215 MHz

12-Bit A/D

AD9430

RF Input50 ohms

VMEbus

VME Slave Interface

XTAL

OSC

Ext Clock In50 ohms

CLOCK, SYNC

& TRIGGER

GENERATOR

Fs/2

FrontPanelLVDS

TimingBus

Control and StatusTo All Sections

Fs

Model 6821

4x SwitchedSerial Fabric1.25 GB/sec

VXS Switched Backplane


LVDSI/O

LVDSI/O


4343434343


Dual 215 MHz, 12-bit A/D with WDual 215 MHz, 12-bit A/D with WDual 215 MHz, 12-bit A/D with WDual 215 MHz, 12-bit A/D with WDual 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXSideband DDCs - VME/VXS

The Model 6822 is a 6U single slot VME boardwith two AD9430 12-bit 215 MHz A/D converters.

Capable of digitizing input signal bandwidths up to100 MHz, it is ideal for wideband applications includ-ing radar and spread spectrum communication systems.

The sampling clock can be supplied either from afront panel input or from an internal crystal oscillator.Data from each A/D converter flows into a XilinxVirtex-II Pro FPGA where optional signal processingfunctions can be performed. The size of the FPGAs canrange from the XC2VP20 to the XC2VP50.

Because the sampling rate is well beyond conven-tional ASIC digital downconverters, none are includedon the board.

Instead, the Pentek GateFlow IP Core 422 UltraWideband Digital Downconverter can be factory-

installed in one or both of the FPGAs to perform thisfunction.

Two 128 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking receivers.

Either two or four FPDP-II ports connect the FPGAsto external digital destinations such as processor boards,memory boards or storage devices.

A VMEbus interface supports configuration of theFPGAs over the backplane and also provides data andcontrol paths for runtime applications. A VXS interfaceis optionally available.

This Model is available in commercial as well asconduction-cooled versions.

Model 6822-422Model 6822-422Model 6822-422Model 6822-422Model 6822-422

Figure 54


FPDP-IIOut ASlot 1

32 32

32 32

128kFIFO

XILINX

VIRTEX-II

PRO FPGA

XC2VP50

FPDP-IIOut BSlot 1

32XILINX

VIRTEX-II

PRO FPGA

XC2VP50

32

128kFIFO

FPDP-IIOut DSlot 2

32 32



VXS Switched Backplane

215 MHz

12-Bit A/D

AD9430

RF Input50 ohms

XTAL

OSC

Ext Clock In50 ohms

CLOCK

GEN

LVDS Clock& Sync Bus

Fs

215 MHz

12-Bit A/D

AD9430

RF Input50 ohms

VMEbus

VME Slave InterfaceControl and StatusTo All Sections

Fs/2

16 MB

FLASH

16

64

128 MB

SDRAM

32

16 MB

FLASH

16

128 MB

SDRAM

32

Model 6822

128kFIFO

LVDSI/O

128kFIFO

FPDP-IIOut CSlot 2

LVDSI/O


4444444444


Dual 2 GHz, 10-bit A/D with VDual 2 GHz, 10-bit A/D with VDual 2 GHz, 10-bit A/D with VDual 2 GHz, 10-bit A/D with VDual 2 GHz, 10-bit A/D with Vererererery High-Speed DDCs - VME/VXSy High-Speed DDCs - VME/VXSy High-Speed DDCs - VME/VXSy High-Speed DDCs - VME/VXSy High-Speed DDCs - VME/VXS

The Model 6826 is a 6U single slot VME boardwith two Atmel AT84AS008 10-bit 2 GHz A/Dconverters.

Capable of digitizing input signals at sampling ratesup to 2 GHz, it is ideal for extremely widebandapplications including radar and spread spectrumcommunication systems. The sampling clock is anexternally supplied sinusoidal clock at a frequency from200 MHz to 2 GHz.

Data from each of the two A/D converters flowsinto an innovative dual-stage demultiplexer that packsgroups of eight data samples into 80-bit words fordelivery to the Xilinx Virtex-II Pro XC2VP70 FPGAat one eighth the sampling frequency. This advancedcircuit features the Atmel AT84CS001 demultiplexerwhich represents a significant improvement over previoustechnology.

Because the sampling rate is well beyond conven-tional digital downconverters, none are included on theboard. A very high-speed digital downconverter IP core

Model 6826Model 6826Model 6826Model 6826Model 6826


Figure 55

for the Model 6826 can be developed for a customer whois interested in one.

The customer will be able to incorporate this coreinto the Model 6826 by ordering it as a factory-installedoption.

Two 512 MB or 1 GB SDRAMs, support largememory applications such as swinging buffers, digitalfilters, DSP algorithms, and digital delay lines fortracking receivers.

Either two or four FPDP-II ports connect the FPGAto external digital destinations such as processor boards,memory boards or storage devices.

A VMEbus interface supports configuration of theFPGA over the backplane and also provides data andcontrol paths for runtime applications. A VXS interfaceis optionally available.

This Model is also available in a single-channelversion and in commercial as well as conduction-cooledversions.

4:1

DEMUX

AT84CS001

40 2:1

DEMUX

V4 FPGA

10

40 2:1

DEMUX

V4 FPGA

10 4:1

DEMUX

AT84CS001

16 MB

FLASH

16

VMEbus

VME SLAVE

INTERFACE

Model 6826

128k

FIFO

FPDP-II

400 MB/sec

32 32

128k

FIFO

32 FPDP-II

400 MB/sec

32

128k

FIFO

FPDP-II

400 MB/sec

32 32

128k

FIFO

32 FPDP-II

400 MB/sec

32

VXS SWITCHED BACKPLANE

4x SWITCHED

SERIAL FABRIC

1.25 GB/SEC

4x SWITCHED

SERIAL FABRIC

1.25 GB/SEC

512 MB

DDR RAM

64

512 MB

DDR RAM

64

XILINX

VIRTEX-II

PRO FPGA

XC2VP70

80

80

4:1

DEMUX

AT84CS001

40 2:1

DEMUX

V4 FPGA

10

40 2:1

DEMUX

V4 FPGA

10 4:1

DEMUX

AT84CS001

2 GHz

10-Bit A/D

AT84AS008

RF INPUT50 OHMS

XTAL

OSC

Fs

2 GHz

10-Bit A/D

AT84AS008

RF INPUT50 OHMS

Fs

EXTCLOCKINPUT

GATE

TRIGGER

& SYNC

Fs/4

Fs/4 Fs/8

Fs/8

Fs/8 IN

Fs/8 OUT

FPGA SYNC IN

GATE A IN

GATE B IN


4545454545



Figure 56

Model 6890 - VMEModel 6890 - VMEModel 6890 - VMEModel 6890 - VMEModel 6890 - VME

2.2 GHz Clock, Sync and Gate Distribution Board2.2 GHz Clock, Sync and Gate Distribution Board2.2 GHz Clock, Sync and Gate Distribution Board2.2 GHz Clock, Sync and Gate Distribution Board2.2 GHz Clock, Sync and Gate Distribution Board

BUFFER1:2

BUFFER1:2

BUFFER1:2

PROGDELAY

PROGDELAY

MUX2:1

MUX2:1

FrontPanelSync

Output

FrontPanelClock

Output

FrontPanelGate

Output

Ch 1

Ch 1

Ch 1

Ch 2

Ch 2

Ch 2

Ch 3

Ch 3

Ch 3

Ch 4

Ch 4

Ch 4

Ch 5

Ch 5

Ch 5

Ch 6

Ch 6

Ch 6

Ch 7

Ch 7

Ch 7

Ch 8

Ch 8

Ch 8

LVPECLBUFFER

1:8

LVPECLBUFFER

1:8

POWERSPLITTER

1:8

POWERSPLITTER

1:2

TTL / PECLSELECTOR

TTL / PECLSELECTOR

TTL / PECLSELECTOR

TTL / PECLSELECTOR

GATECONTROL

SYNCCONTROL

FrontPanelClockInput

FrontPanelGateInput

FrontPanelSyncInput

FrontPanelGate

Enable

FrontPanelSync

Enable REG

REG

Model 6890VME

Model 6890 Clock, Sync and Gate DistributionBoard synchronizes multiple Pentek I/O boards within asystem. It enables synchronous sampling and timingfor a wide range of multichannel high-speed dataacquisition, DSP and software radio applications. Upto eight boards can be synchronized using the 6890,each receiving a common clock of up to 2.2 GHz alongwith timing signals that can be used for synchronizing,triggering and gating functions.

Clock signals are applied from an external sourcesuch as a high performance sine wave generator. Gateand sync signals can come from an external source, orfrom one supported board set to act as the master.

The 6890 accepts clock input at +10 dBm to +14 dBmwith a frequency range from 800 MHz to 2.2 GHz anduses a 1:2 power splitter to distribute the clock. The firstoutput of this power splitter sends the clock signal to a1:8 splitter for distribution to up to eight boards usingSMA connectors. The second output of the 1:2 power

splitter feeds a 1:2 buffer which distributes the clocksignal to both the gate and synchronization circuits.

The 6890 features separate inputs for gate/triggerand sync signals with user-selectable polarity. Each ofthese inputs can be TTL or LVPECL. Separate GateEnable and Sync Enable inputs allow the user to enableor disable these circuits using an external signal.

A programmable delay allows the user to maketiming adjustments on the gate and sync signals beforethey are sent to an LVPECL buffer. A bank of eightMMCX connectors at the output of each buffer deliverssignals to up to eight boards.

A 2:1 multiplexer in each circuit allows the gate/trigger and sync signals to be registered with the inputclock signal before output, if desired.

Sets of input and output cables for two to eightboards are available from Pentek.


4646464646



Figure 57

System Synchronizer and Distribution BoardSystem Synchronizer and Distribution BoardSystem Synchronizer and Distribution BoardSystem Synchronizer and Distribution BoardSystem Synchronizer and Distribution Board

Model 6891 - VMEModel 6891 - VMEModel 6891 - VMEModel 6891 - VMEModel 6891 - VME

BUFFER1:2

BUFFER1:2

PROGDELAY

PROGDELAY

MUX2:1

MUX2:1

Ch 1

Ch 1

Ch 1

Ch 2

Ch 2

Ch 2

Ch 3

Ch 3

Ch 3

Ch 4

Ch 4

Ch 4

Ch 5

Ch 5

Ch 5

Ch 6

Ch 6

Ch 6

Ch 7

Ch 7

Ch 7

Ch 8

Ch 8

Ch 8

SYNCLVPECLBUFFER

1:8

GATELVPECLBUFFER

1:8

CLOCKLVPECLBUFFER

1:10

GATECONTROL

Front PanelClock Input

Front PanelGateInput

Front PanelSync Input

Front PanelGate Enable

Front PanelSync Enable REG

REG

Gate

SyncClockSync Bus

Input

MUX2:1

MUX2:1

MUX2:1

SYNCCONTROL

Gate

SyncClock Sync Bus

Output 8

Gate

SyncClock Sync Bus

Output 7

Gate

SyncClock Sync Bus

Output 6

Gate

SyncClock Sync Bus

Output 5

Gate

SyncClock Sync Bus

Output 4

Gate

SyncClock Sync Bus

Output 3

Gate

SyncClock Sync Bus

Output 2

Gate

SyncClock Sync Bus

Output 1

to Sync BusOutputs 2-8



Model 6891VME

Model 6891 System Synchronizer and DistributionBoard synchronizes multiple Pentek I/O modules within asystem. It enables synchronous sampling and timing for awide range of multichannel high-speed data acquisition,DSP and software radio applications.

Up to eight modules can be synchronized using the6891, each receiving a common clock up to 500 MHzalong with timing signals that can be used for synchroniz-ing, triggering and gating functions. For larger systems,up to eight 6891’s can be linked together to providesynchronization for up to 64 I/O modules producingsystems with up to 256 channels.

Model 6891 accepts three TTL input signals fromexternal sources: one for clock, one for gate or triggerand one for a synchronization signal. Two additionalinputs are provided for separate gate and sync enable signals.

Clock signals can be applied from an external sourcesuch as a high performance sine-wave generator. Gate/triggerand sync signals can come from an external system source.Alternately, a Sync Bus connector accepts LVPECL inputsfrom any compatible Pentek products to drive the clock,sync and gate/trigger signals.

The 6891 provides eight front panel Sync Bus outputconnectors, compatible with a wide range of Pentek I/Omodules. The Sync Bus is distributed through ribboncables, simplifying system design. The 6891 accepts clockinput at +10 dBm to +14 dBm with a frequency rangefrom 1 kHz to 800 MHz. This clock is used to registerall sync and gate/trigger signals as well as providing asample clock to all connected I/O modules.

A programmable delay allows the user to maketiming adjustments on the gate and sync signals beforethey are sent to an LVPECL buffer for output throughthe Sync Bus connectors.


4747474747


ReferenceIn

Control

PCI INTERFACE

PCI BUS(32 Bits / 66 MHz)32

Clock Out1

Clock Out2

Clock Out3

Clock Out4

Clock Out5

Clock Out6

Clock Out7

Clock Out8

CLOCKSYNTHESIZER

AND JITTERCLEANER

A

1÷÷ 2÷ 4÷ 8÷16

QUADVCXO

A

CLOCKSYNTHESIZER

AND JITTERCLEANER

B

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

C

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

D

1÷÷ 2÷ 4÷ 8÷16

Supports:any In to any Out,any In to multiple

Outs

CROSSBAR

SWITCH

In

In

In

In

Out

Out

Out

Out

Out

QUADVCXO

B

QUADVCXO

C

QUADVCXO

D


Figure 58

Multifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock Synthesizer

Model 7190PMC

Model 7190 generates up to eight synthesized clocksignals suitable for driving A/D and D/A converters inhigh-performance real-time data acquisition and softwareradio systems. The clocks offer exceptionally low phase noiseand jitter to preserve the signal quality of the data converters.These clocks are synthesized from on-board quad VCXOsand can be phase-locked to an external reference signal.

The 7190 uses four Texas Instruments CDC7005 clocksynthesizer and jitter cleaner devices. Each CDC7005 is pairedwith a dedicated VCXO to provide the base frequency forthe clock synthesizer. Each of the four VCXOs can beindependently programmed to generate one of four frequen-cies between 50 MHz and 700 MHz.

The CDC7005 can output the selected frequencyof its associated VCXO, or generate submultiples usingdivisors of 2, 4, 8 or 16. The four CDC7005’s can outputup to five frequencies each. The 7190 can be programmed toroute any of these 20 frequencies to the module’s fiveoutput drivers.

The CDC7005 includes phase-locking circuitrythat locks the frequency of its associated VCXO to aninput reference of 5 MHz to 100 MHz.

Eight front panel SMC connectors supply synthesizedclock outputs driven from the five clock output drivers.This supports a single identical clock to all eight outputsor up to five different clocks to various outputs. Withfour independent quad VCXOs and each CDC7005capable of providing up to five different submultipleclocks, a wide range of clock configurations is possible. Insystems where more than five different clock outputs arerequired simultaneously, multiple 7190’s can be used andphase-locked with the 5 MHz to 100 MHz system reference.

Versions of the 7190 are also available as a PCIe full-length board (Models 7790 and 7790D dual density),PCIe half-length board (Model 7890), 3U VPX board(Model 5390), PCI board (Model 7690), 6U cPCI(Models 7290 and 7290D dual density), or 3U cPCI(Model 7390).



4848484848


ReferenceIn

Control

PCI INTERFACE

PCI BUS(32 Bits / 66 MHz)32

Clock Out1

Clock Out2

Clock Out3

Clock Out4

Clock Out5

Clock Out6

Clock Out7

Clock Out8

CLOCKSYNTHESIZER

AND JITTERCLEANER

A

1÷÷ 2÷ 4÷ 8÷16

PROGRAMVCXO

A

CLOCKSYNTHESIZER

AND JITTERCLEANER

B

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

C

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

D

1÷÷ 2÷ 4÷ 8÷16

Supports:any In to any Out,any In to multiple

Outs

CROSSBAR

SWITCH

In

In

In

In

Out

Out

Out

Out

Out

PROGRAMVCXO

B

PROGRAMVCXO

C

PROGRAMVCXO

D


Figure 59


Model 7191 generates up to eight synthesized clocksignals suitable for driving A/D and D/A converters inhigh-performance real-time data acquisition and softwareradio systems. The clocks offer exceptionally low phase noiseand jitter to preserve the signal quality of the data converters.These clocks are synthesized from programmable VCXOsand can be phase-locked to an external reference signal.

The 7191 uses four Texas Instruments CDC7005 clocksynthesizer and jitter cleaner devices. Each CDC7005 is pairedwith a dedicated VCXO to provide the base frequency forthe clock synthesizer. Each of the four VCXOs can beindependently programmed to a desired frequency between50 MHz and 700 MHz with 32-bit tuning resolution.

The CDC7005 can output the programmed frequencyof its associated VCXO, or generate submultiples usingdivisors of 2, 4, 8 or 16. The four CDC7005’s can outputup to five frequencies each. The 7191 can be programmed toroute any of these 20 frequencies to the module’s fiveoutput drivers.

The CDC7005 includes phase-locking circuitrythat locks the frequency of its associated VCXO to aninput reference of 5 MHz to 100 MHz.

Eight front panel SMC connectors supply synthesizedclock outputs driven from the five clock output drivers.This supports a single identical clock to all eight outputsor up to five different clocks to various outputs. Withfour programmable VCXOs and each CDC7005capable of providing up to five different submultipleclocks, a wide range of clock configurations is possible. Insystems where more than five different clock outputs arerequired simultaneously, multiple 7191’s can be used andphase-locked with the 5 MHz to 100 MHz system reference.

Versions of the 7191 are also available as a PCIe full-length board (Models 7791 and 7791D dual density),PCIe half-length board (Model 7891), 3U VPX board(Model 5391), PCI board (Model 7691), 6U cPCI(Models 7291 and 7291D dual density), or 3U cPCI(Model 7391).

Model 7191PMC

PPPPProgrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizer


4949494949


Figure 60

Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC ●●●●● Model 7892 Half-length PCIe Model 7892 Half-length PCIe Model 7892 Half-length PCIe Model 7892 Half-length PCIe Model 7892 Half-length PCIe ●●●●● Model 5393 3U VPX Model 5393 3U VPX Model 5393 3U VPX Model 5393 3U VPX Model 5393 3U VPXModel 7292 6U cPCI Model 7292 6U cPCI Model 7292 6U cPCI Model 7292 6U cPCI Model 7292 6U cPCI ●●●●● Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI ● ● ● ● ● Model 7492 6U cPCIModel 7492 6U cPCIModel 7492 6U cPCIModel 7492 6U cPCIModel 7492 6U cPCI

High-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution Board

Model 7192PMC/XMC

PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

:N

PROGRAMMABLEVCXO

Clock /Calibration Out

:N

BUFFER&

PROGRAMDELAYS

Clk/RefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *

Gate / Trigger OutSync OutReference Clk Out

MUX

Trig/GateIn

SyncIn

TWSICONTROL



Gate / Trigger In

Sync In

�Sync 3

�Sync 2

�Sync 1

�Sync 4

* For 71640 A/D calibration

The Model 7192 High-Speed Synchronizer andDistribution Board synchronizes multiple Pentek Cobaltor Onyx modules within a system. It enables synchronoussampling and timing for a wide range of multichannelhigh-speed data acquisition, DSP, and software radioapplications. Up to four modules can be synchronizedusing the 7192, with each receiving a common clockalong with timing signals that can be used for synchro-nizing, triggering and gating functions.

Model 7192 provides three front panel MMCXconnectors to accept input signals from external sources:one for clock, one for gate or trigger and one for a synchro-nization signal. Clock signals can be applied from anexternal source such as a high performance sine-wavegenerator. Gate/trigger and sync signals can come froman external system source. In addition to the MMCXconnector, a reference clock can be accepted through thefirst front panel µSync output connector, allowing asingle Cobalt or Onyx board to generate the clock forall subsequent boards in the system.

The 7192 provides four front panel µSync outputconnectors, compatible with a range of high-speedPentek Cobalt and Onyx modules. The µSync signalsinclude a reference clock, gate/trigger and sync signals and aredistributed through matched cables, simplifying systemdesign. The 7192 features a calibration output specifi-cally designed to work with the 71640 or 717403.6 GHz A/D module and provide a signal reference forphase adjustment across multiple D/As.

The 7192 supports all high-speed models in the Cobaltfamily including the 71630 1 GHz A/D and D/A XMC,the 71640 3.6 GHz A/D XMC and the 71670 Four-channel 1.25 GHz, 16-bit D/A XMC. The 7192 will alsosupport high-speed models in the Onyx family as theybecome available.




5050505050



Figure 61

Clock and Sync Generator for I/O ModulesClock and Sync Generator for I/O ModulesClock and Sync Generator for I/O ModulesClock and Sync Generator for I/O ModulesClock and Sync Generator for I/O Modules

ToModuleNo. 80

FromModuleMasterSource

ToModuleNo. 2

ToModuleNo. 1

OPTIONALINTERNAL

OSCILLATOR

LVDSDIFF.

RECEIVER

LVDSDIFF.

DRIVERS

LVDSDIFF.

DRIVERS

LVDSDIFF.

DRIVERS

FrontPanel

OutputSMA

Connectors

LINEDRIVERS

FrontPanelInputSMA

Connectors

TimingSignals

MultiplexerSwitches

TimingSignals

TimingSignals

Ext. Clock

ClockLINERCVRS

Model 9190

Model 9190 - RModel 9190 - RModel 9190 - RModel 9190 - RModel 9190 - Rack-mountack-mountack-mountack-mountack-mount

Model 9190 Clock and Sync Generator synchronizesmultiple Pentek I/O modules within a system to providesynchronous sampling and timing for a wide range ofhigh-speed, multichannel data acquisition, DSP andsoftware radio applications. Up to 80 I/O modules canbe driven from the Model 9190, each receiving acommon clock and up to five different timing signalswhich can be used for synchronizing, triggering andgating functions.

Clock and timing signals can come from six frontpanel SMA user inputs or from one I/O module set to actas the timing signal master. (In this case, the master I/Omodule will not be synchronous with the slave modulesdue to delays through the 9190.) Alternately, the masterclock can come from a socketed, user-replaceable crystaloscillator within the Model 9190.

Buffered versions of the clock and five timingsignals are available as outputs on the 9190’s front panelSMA connectors.

Model 9190 is housed in a line-powered, 1.75 in.high metal chassis suitable for mounting in a standard19 in. equipment rack, either above or below the cageholding the I/O modules.

Separate cable assemblies extend from openings inthe front panel of the 9190 to the front panel clock andsync connectors of each I/O module. Mounted betweentwo standard rack-mount card cages, Model 9190 candrive a maximum of 80 clock and sync cables, 40 to thecard cage above and 40 to the card cage below. Fewercables may be installed for smaller systems.


5151515151



High-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer Unit

Model 9192 - RModel 9192 - RModel 9192 - RModel 9192 - RModel 9192 - Rack-mountack-mountack-mountack-mountack-mount

PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

:N

PROGRAMMABLEVCXO

Clock Out 1

:N

BUFFER&

PROGRAMDELAYS

ClkRefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *


MUX

Trig/GateIn

SyncIn

TWSICONTROL


Gate / Trigger In

Sync In

�Sync 2

�Sync 1

�Sync 12

* For 71640 A/D calibration

�Sync 3through

�Sync 11

Clock Out 2

Clock Out 12

CLOCKSPLITTER

Clock Out 3throughClock Out 11

External Clk In

MUX

USB-TO-TWSIINTERFACE

USB

Model 9192

Model 9192 Rack-mount High-Speed SystemSynchronizer Unit synchronizes multiple Pentek Cobalt orOnyx modules within a system. It enables synchronoussampling and timing for a wide range of multichannelhigh-speed data acquisition, DSP, and software radioapplications. Up to twelve boards can be synchronizedusing the 9192, each receiving a common clock alongwith timing signals that can be used for synchronizing,triggering and gating functions.

Model 9192 provides four rear panel SMA connec-tors to accept input signals from external sources: twofor clock, one for gate or trigger and one for a synchro-nization signal. Clock signals can be applied from anexternal source such as a high performance sine-wavegenerator. Gate/trigger and sync signals can come from anexternal system source. In addition to the SMA connector,a reference clock can be accepted through the first rearpanel µSync output connector, allowing a single Cobaltor Onyx board to generate the clock for all subsequentboards in the system.

Figure 62

The 9192 provides four rear panel µSync outputconnectors, compatible with a range of high-speed PentekCobalt and Onyx boards. The µSync signals include areference clock, gate/trigger and sync signals and are distrib-uted through matched cables, simplifying system design.

The 9192 features twelve calibration outputsspecifically designed to work with the 71640 or 717403.6 GHz A/D module and provide a signal reference forphase adjustment across multiple D/As.

The 9192 allows programming of operation parametersincluding: VCXO frequency, clock dividers, and delays thatallow the user to make timing adjustments on the gate andsync signals. These adjustments are made before they are sentto buffers for output through the µSync connectors.

The 9192 supports all high-speed models in the Cobaltfamily including the 71630 1 GHz A/D and D/A XMC, the71640 3.6 GHz A/D XMC and the 71670 Four-channel1.25 GHz, 16-bit D/A XMC. The 9192 will also support high-speed models in the Onyx family as they become available.


5252525252



2-2-2-2-2-Channel RF/IF 125 MS/sec RChannel RF/IF 125 MS/sec RChannel RF/IF 125 MS/sec RChannel RF/IF 125 MS/sec RChannel RF/IF 125 MS/sec Rack-mount Rack-mount Rack-mount Rack-mount Rack-mount Recorderecorderecorderecorderecorder

Model RTS 2701 Model RTS 2701 Model RTS 2701 Model RTS 2701 Model RTS 2701

Figure 63

CH 1In

125 MHz14-bit A/D

MODEL

7641-420

CH 2In

Out

125 MHz14-bit A/D

SampleClock A In

CLOCK &SYNC

GENERATOR

Clock/SyncBus

XTALOSC B

XTALOSC B

SampleClock B In

TTL Gate/TriggerIn

TTL SyncIn

DIGITALDOWN-

CONVERTER

DIGITALDOWN-

CONVERTER

DIGITALUPCONVERTER

INTELPROCESSOR

SYSTEM DRIVE

A

500 MHz16-bit D/A

DDRSDRAM

HOST PROCESSOR

RAID

DATA DRIVES DATA DRIVES


MODEL RTS 2701

USB

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

The TalonTM RTS 2701 is a highly scalable recordingand playback system in an industrial rack-mount PC serverchassis. Built on the Windows® XP professional workstation,it utilizes the Model 7641-420 multiband transceiverPCI module with two 14-bit 125 MHz A/Ds, ASICDDC, and DUC with two 16-bit 500 MHz D/As.

The factory-installed IP core 420 provides a dualwideband DDC and expands the decimation range ofthe ASIC DDC. The core also includes an interpolationfilter that expands the interpolation factor of the ASICDUC. The Model 7641-420 combines downconverter andupconverter functions in one PCI module and offersrecording and playback capabilities.

Included with this instrument is Pentek’s SystemFlow®

recording software.The RTS 2701 uses a native NTFSrecord/playback file format for easy access by user

applications for analysis, signal processing, and waveformgeneration. File headers include recording parametersettings and time stamping so that the signal viewercorrectly formats and annotates the displayed signals.

A high-performance PCI Express SATA RAIDcontroller connects to multiple SATA hard drives tosupport storage to 4 terabytes and real-time sustainedrecording rates to 480 MB/sec.

Multiple RAID levels, including 0, 1, 5, 6, 10 and50, provide a choice for the required level of redundancy.The Pentek RTS 2701 serves equally well as a develop-ment platform for advanced research projects and proof-of-concept prototypes, or as a cost-effective strategy fordeploying high-performance, multichannel embeddedsystems.


5353535353


ChannelsIn

ChannelsOut

200 MHz16-bit A/D

0 to 8Channels

DIGITALDOWN-

CONVERTERDecimation:2 to 65,536

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

UP TO 20 TB RAID



MODEL RTS 2706

USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2

GPSAntenna(Optional)

800 MHzor 1.25 GHz16-bit D/A

0 to 8Channels

DIGITALUP-




Figure 64

8-8-8-8-8-Channel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec Rack-mount Rack-mount Rack-mount Rack-mount Rack-mount Recorderecorderecorderecorderecorder

The Talon RTS 2706 is a turnkey, multibandrecording and playback instrument for recording andreproducing high-bandwidth signals. The RTS 2706uses 16-bit, 200 MHz A/D converters and providessustained recording rates up to 1600 MB/sec in four-channelconfiguration.

The RTS 2706 uses Pentek’s high-powered Virtex-6-basedCobalt modules, that provide flexibility in channel count,with optional digital downconversion capabilities. Optional16-bit, 800 MHz D/A converters with digital upconversionallow real-time reproduction of recorded signals.

A/D sampling rates, DDC decimations and band-widths, D/A sampling rates and DUC interpolations areamong the GUI-selectable system parameters, providinga fully-programmable instrument capable of recordingand reproducing a wide range of signals.

Included with this instrument is Pentek’s SystemFlowrecording software. Optional GPS time and positionstamping allows the user to record this critical signalinformation.

Built on a Windows 7 Professional workstation withhigh performance Intel® CoreTM i7 processor the RTS 2706allows the user to install post processing and analysistools to operate on the recorded data. The instrumentrecords data to the native NTFS file system, providingimmediate access to the recorded data.

The RTS 2706 is configured in a 4U 19" rack-mount-able chassis, with hot-swap data drives, front panel USBports and I/O connectors on the rear panel. Systems arescalable to accommodate multiple chassis to increasechannel counts and aggregate data rates. All recorderchassis are connected via Ethernet and can be controlledfrom a single GUI either locally or from a remote PC.

Model RTS 2706COTS

Model RTS 2706Rugged


5454545454




Figure 65

2-2-2-2-2-Channel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet Rack-mount Rack-mount Rack-mount Rack-mount Rack-mount Recorderecorderecorderecorderecorder

Ch 1In / Out 10G

Ethernet INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

UP TO 20 TB RAID



MODEL RTS 2715

USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2


Ch 2In / Out 10G

Ethernet

The Talon RTS 2715 is a complete turnkey recordingsystem for storing one or two 10 gigabit Ethernet (10 GbE)streams. It is ideal for capturing any type of streaming sourcesincluding live transfers from sensors or data from other computersand supports both TCP and UDP protocols. Using highly-optimized disk storage technology, the system achievesaggregate recording rates up to 2 GB/sec.

Two rear panel SFP+LC connectors for 850 nm multi-mode or single-mode fibre cables, or CX4 connectors for coppertwinax cables accommodate all popular 10 GbE interfaces.Optional GPS time and position stamping accuratelyidentifies each record in the file header.

The RTS 2715 includes the SystemFlow RecordingSoftware. SystemFlow features a Windows-based GUI(Graphical User Interface) that provides a simple andintuitive means to configure and control the system.Custom configurations can be stored as profiles and later

loaded as needed, allowing the user to select preconfiguredsettings with a single click.

Built on a server-class Windows 7 Professionalworkstation, the RTS 2715 allows the user to installpost-processing and analysis tools to operate on therecorded data. The RTS 2715 records data to the nativeNTFS file system, providing immediate access to therecorded data.

The RTS 2715 is configured in a 4U or 5U 19" rack-mountable chassis, with hot-swap data drives, front panelUSB ports and I/O connectors on the rear panel. Systemsare scalable to accommodate multiple chassis to increasechannel counts and aggregate data rates.

All recorder chassis are connected via Ethernet andcan be controlled from a single GUI either locally orfrom a remote PC.


5555555555



2-2-2-2-2-Channel RF/IF 125 MS/sec PChannel RF/IF 125 MS/sec PChannel RF/IF 125 MS/sec PChannel RF/IF 125 MS/sec PChannel RF/IF 125 MS/sec Pororororortable Rtable Rtable Rtable Rtable Recorderecorderecorderecorderecorder


Figure 66

CH 1In

125 MHz14-bit A/D

MODEL

7641-420

CH 2In

Out

125 MHz14-bit A/D

SampleClock A In

CLOCK &SYNC

GENERATOR

Clock/SyncBus

XTALOSC B

XTALOSC B

SampleClock B In

TTL Gate/TriggerIn

TTL SyncIn

DIGITALDOWN-

CONVERTER

DIGITALDOWN-

CONVERTER

DIGITALUPCONVERTER

INTELPROCESSOR

SYSTEM DRIVE

A

500 MHz16-bit D/A

DDRSDRAM

HOST PROCESSOR

RAID



HIGH RESOLUTIONVIDEO DISPLAY

MODEL RTS 2721

USB

GigabitEthernet

PS/2Keyboard

PS/2Mouse

Aux VideoOutput

The Talon RTS 2721 is a turnkey real-time record-ing and playback instrument supplied in a convenientbriefcase-size package that weighs just 30 pounds. Builton the Windows XP professional workstation, it includesa dual-core Xeon processor, a high-resolution 17-inchLCD monitor and a high-performance SATA RAIDcontroller.

The RTS 2721 utilizes the Model 7641 multibandtransceiver PCI module with two 14-bit 125 MHzA/Ds, ASIC DDC, and DUC with two 16-bit 500 MHzD/As. The factory-installed IP core 420 provides adual wideband DDC and expands the decimation rangeof the ASIC DDC. The core also includes an interpola-tion filter that expands the interpolation factor of theASIC DUC.

The Model 7641-420 combines downconverter andupconverter functions in one PCI module and offersreal-time recording capabilities.

Fully supported by Pentek’s SystemFlow recordingsoftware, the RTS 2721 uses a native NTFS record/play-back file format for easy access by user applications foranalysis, signal processing, and waveform generation.File headers include recording parameter settings andtime stamping so that the signal viewer correctly formatsand annotates the displayed signals.

A high-performance PCI Express SATA RAIDcontroller connects to multiple SATA hard drives tosupport storage to 3 terabytes and real-time sustainedrecording rates up to 480 MB/sec.

Pentek’s portable recorder instrument provides aflexible architecture that is easily customized to meetspecial needs. Multiple RAID levels, including 0, 1, 5,6, 10 and 50, provide a choice for the required level ofredundancy. With its wide range of programmabledecimation and interpolation, the system supports signalbandwidths from 8 kHz to 60MHz.


5656565656


INTEL CORE i7PROCESSOR

SSDSYSTEM DRIVE

DDRSDRAM

WINDOWS HOST PROCESSOR

RAID DATA STORE

SSD DRIVES SSD DRIVES


HIGH RESOLUTIONVIDEO DISPLAY

8x USB 2.0

1x GigabitEthernet

Aux VideoVGA Output

MODEL RTR 2726

ChannelsIn

ChannelsOut

2x eSATA 3

200 MHz16-bit A/D

Up to 4Channels

DIGITAL DOWNCONVERTERDEC: 2 to 64K

800 MHz16-bit D/A

Up to 2Channels

DIGITAL UPCONVERTER

INT: 2 to 512K

2x USB 3.0


4-4-4-4-4-Channel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec Rugged Pugged Pugged Pugged Pugged Pororororortable Rtable Rtable Rtable Rtable Recorderecorderecorderecorderecorder

Model RTR 2726 Model RTR 2726 Model RTR 2726 Model RTR 2726 Model RTR 2726

Figure 67

The Talon RTR 2726 is a turnkey, multiband recordingand playback system that allows the user to record andreproduce high-bandwidth signals with a lightweight,portable and rugged package. The RTR 2726 providessustained recording rates of up to 1600 MB/sec in a four-channel system and is ideal for the user who requiresboth portability and solid performance in a compactrecording system.

The RTR 2726 is supplied in a small footprintportable package measuring only 16.9" W x 9.5" D x13.4" H and weighing just 30 pounds. With measurementssimilar to a small briefcase, this portable workstationincludes an Intel® CoreTM i7 processor a high-resolu-tion 17" LCD monitor, and a high-performance SATARAID controller.

At the heart of the RTR 2726 are Pentek CobaltSeries Virtex-6 software radio boards featuring A/D andD/A converters, DDCs, DUCs, and complementary

FPGA IP cores. This architecture allows the systemengineer to take full advantage of the latest technologyin a turnkey system.

Because SSDs operate reliably under conditions ofvibration and shock, the RTR 2726 performs well inground, shipborne and airborne environments. Theeight hot-swappable SSD’s provide a storage capacity of upto 4 TB. The drives can be easily removed or exchangedduring or after a mission to retrieve recorded data. Thesystem supports simultaneous recording up to fourwideband A/D or multiband DDC channels withbandwidths from 2.5 kHz to 80 MHz. Recorded signalscan be reproduced via playback as either baseband orupconverted IF signals.

Included in this system is the Pentek SystemFlowrecording software. SystemFlow features a Windows-basedGUI that provides a simple means to configure and controlthe system.


5757575757



8-8-8-8-8-Channel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec RChannel RF/IF 200 MS/sec Rugged Rugged Rugged Rugged Rugged Rack-mount Rack-mount Rack-mount Rack-mount Rack-mount Recorderecorderecorderecorderecorder


Figure 68

ChannelsIn

ChannelsOut

200 MHz16-bit A/D

0 to 8Channels

DIGITALDOWN-


INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

UP TO 24 TB RAID



MODEL RTR 2746

USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2


800 MHzor 1.25 GHz16-bit D/A

0 to 8Channels

DIGITALUP-


The Talon RTR 2746 is a turnkey, multiband recordand playback system that is built to operate under harshconditions. Designed to withstand high vibration andoperating temperatures, the RTR 2746 is intended formilitary, airborne and UAV applications requiring a ruggedsystem. With scalable A/Ds, D/As and SSD (solid-statedrive) storage, the RTR 2746 can be configured to streamdata to and from disk at rates as high as 1600 MB/sec.

The RTR 2746 uses Pentek’s high-powered Virtex-6-based Cobalt boards, that provide flexibility in channel countwith optional digital downconversion capabilities. Optional16-bit, 800 MHz D/A converters with digital upconversionallow real-time reproduction of recorded signals.

Built on a Windows 7 Professional workstation, theRTR 2746 allows the user to install post processing andanalysis tools to operate on the recorded data. The RTR2746 records data to the native NTFS file system, providingimmediate access to the recorded data.

The recorder can be configured with up to six datadrive packs, each containing up to eight SSDs. Thisfeature allows instant removal of acquired data by simplyremoving the drive packs for remote copying and analysis.For installations that demand a minimum of down-time, new drive packs can be immediately swapped for theremoved ones.

The RTR 2746 is delivered in a 4U 19" rugged rack-mount-able chassis. Designed to MIL-STD-810F, it is built tosurvive shock and vibration. Stress to the motherboardand CPU heatsink is mitigated by multiple attachmentpoints to stabilize the PCB. All fasteners and connectors areretained with locking mechanisms and shock-isolateddrive bays.

High-speed, high-volume, thermally-controlled fansoffer maximum airflow and are designed for long life.Additionally, extended temperature operation is possiblewith an optional high-temperature CPU.


5858585858



2-2-2-2-2-Channel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet RChannel 10 Gigabit Ethernet Rugged Rugged Rugged Rugged Rugged Rack-mount Rack-mount Rack-mount Rack-mount Rack-mount Recorderecorderecorderecorderecorder


Figure 69

Ch 1In / Out 10G

Ethernet INTELPROCESSOR

SSDSYSTEM DRIVE

DDRSDRAM

WINDOWS HOST PROCESSOR

RAID DATA STORE



MODEL RTR 2755

USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2


Ch 2In / Out 10G

Ethernet

The Talon RTR 2755 is a complete turnkey recordingsystem for storing one or two 10 gigabit Ethernet (10 GbE)streams. It is ideal for capturing any type of streamingsources including live transfers from sensors or data from othercomputers and supports both TCP and UDP protocols.Using highly-optimized disk storage technology, thesystem guarantees loss-free performance at aggregaterecording rates up to 2 GB/sec.

Two rear panel SFP+ LC connectors for 850 nmmulti-mode or single-mode fibre cables, or CX4 connec-tors for copper twinax cables accommodate all popular10 GbE interfaces. Optional GPS time and positionstamping accurately identifies each record in the fileheader.

Built on a server-class Windows 7 Professionalworkstation, the RTR 2755 allows the user to installpost-processing and analysis tools to operate on therecorded data.

The RTR 2755 records data to the native NTFS filesystem, providing immediate access to the recorded data.The system is configured in a 4U 19" rack-mountablechassis, with hot-swap SSD storage, front panel USB portsand I/O connectors on the rear panel.

Because SSDs operate reliably under conditions ofvibration and shock, the RTR 2755 performs well inground, shipborne and airborne environments. The 24hot-swappable SSD’s provide storage capacity of up to12 TB. The drives can be easily removed or exchangedduring or after a mission to retrieve recorded data.

Systems are scalable to accommodate multiplechassis to increase channel counts and aggregate datarates. All recorder chassis are connected via Ethernet andcan be controlled from a single GUI either locally orfrom a remote PC. Multiple RAID levels, including 0, 1,5, 6, 10 and 50, provide a choice for the required level ofredundancy.


5959595959


PPPPPentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Recording Sofecording Sofecording Sofecording Sofecording Softwaretwaretwaretwaretware

Figure 70

Signal Viewer

Recorder Interface Hardware ConfigurationInterface

The Pentek SystemFlow® Recording Software providesa rich set of function libraries and tools for controlling allPentek RTS real-time data acquisition and recordinginstruments. SystemFlow software allows developers toconfigure and customize system interfaces and behavior.

The Recorder Interface includes configuration, record,playback and status screens, each with intuitive controlsand indicators. The user can easily move between screensto set configuration parameters, control and monitor arecording, play back a recorded signal and monitorboard temperatures and voltage levels.

The Hardware Configuration Interface providesentries for input source, center frequency, decimation, aswell as gate and trigger information. All parameterscontain limit-checking and integrated help to provide aneasier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtualoscilloscope and spectrum analyzer for signal monitoringin both the time and frequency domains. It is extremelyuseful for previewing live inputs prior to recording, andfor monitoring signals as they are being recorded to helpensure successful recording sessions. The viewer can alsobe used to inspect and analyze the recorded files afterthe recording is complete.

Advanced signal analysis capabilities include automaticcalculators for signal amplitude and frequency, secondand third harmonic components, THD (total harmonicdistortion) and SINAD (signal to noise and distortion).With time and frequency zoom, panning modes and dualannotated cursors to mark and measure points of interest,the SystemFlow Signal Viewer can often eliminate theneed for a separate oscilloscope or spectrum analyzer inthe field.



6060606060



Figure 71

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

UP TO 20 TB RAID



USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2

GPSAntenna

x8 PCIe

Input A

Input B

Output A

Output B

500 MHzA/D

500 MHzA/D

800 MHzD/A

800 MHzD/A

Pentek Cobalt 78651 PCIe Board

DUC

FPGAwith

2 Channelsof DDC

2-2-2-2-2-Channel SofChannel SofChannel SofChannel SofChannel Software Rtware Rtware Rtware Rtware Radio Radio Radio Radio Radio Recording and Playback Systemecording and Playback Systemecording and Playback Systemecording and Playback Systemecording and Playback System

Shown above is a 2-channel recording and playbacksystem utilizing the Pentek Cobalt 78651 PCIe board.The 78651 samples two input channels at up to 500 mega-samples per second, thereby accommodating inputsignals with up to 200 MHz bandwidth.

Factory-installed in the FPGA is a powerful 2-channelDDC (Digital Downconverter) IP core. Each DDC hasan independent 32-bit tuning frequency setting thatranges from DC to ƒs, where ƒs is the A/D samplingfrequency. Each DDC can have its own uniquedecimation setting, supporting as many as two differentoutput bandwidths for the board. Decimations can beprogrammed from 2 to 131,072 providing a wide range tosatisfy most applications.

The decimating filter for each DDC accepts aunique set of user-supplied 16-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% outputbandwidth is better than 100 dB. Each DDC delivers acomplex output stream consisting of 24-bit I + 24-bit Qor 16-bit I + 16-bit Q samples at a rate of ƒs/N.

A TI DAC5688 DUC (Digital Upconverter) and D/Aaccepts a baseband real or complex data stream from theFPGA and provides that input to the upconvert, inter-polate and dual D/A stages.

When operating as a DUC, it interpolates and trans-lates real or complex baseband input signals to any IFcenter frequency up to 360 MHz. It delivers real orquadrature (I+Q) analog outputs to the dual 16-bit D/Aconverter. Analog output is through a pair of front panelSSMC connectors. If translation is disabled, theDAC5688 acts as a dual interpolating 16-bit D/A withoutput sampling rates up to 800 MHz.

Built on a Windows 7 Professional workstation withhigh performance Intel® CoreTM i7 processor this systemallows the user to install post processing and analysistools to operate on the recorded data. The system recordsdata to the native NTFS file system, providing immediateaccess to the recorded data.

Included with this system is Pentek’s SystemFlowrecording software. Optional GPS time and positionstamping allows the user to record this critical signalinformation.


6161616161



Figure 72

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

UP TO 20 TB RAID



USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

2

6

eSATA2

GPSAntenna

x8 PCIe

x8 PCIe

Input A

Input B

Input C

Input D

200 MHzA/D

200 MHzA/D

200 MHzA/D

200 MHzA/D

FPGAwith

4 banks of8-Channel

DDC


Input A

Input B

Input C

Input D

200 MHzA/D

200 MHzA/D

200 MHzA/D

200 MHzA/D

FPGAwith

4 banks of8-Channel

DDC


64-64-64-64-64-Channel SofChannel SofChannel SofChannel SofChannel Software Rtware Rtware Rtware Rtware Radio Radio Radio Radio Radio Recording Systemecording Systemecording Systemecording Systemecording System

Each DDC delivers a complex output stream consist-ing of 24-bit I + 24-bit Q samples at a rate of ƒs/N. Anynumber of channels can be enabled within each bank,selectable from 0 to 8. Each bank includes an outputsample interleaver that delivers a channel-multiplexedstream for all enabled channels within a bank.

An internal timing bus provides all timing and synchro-nization required by the eight A/D converters. It includesa clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock.This clock can be used directly by the A/D or divided bya built-in clock synthesizer circuit.

Built on a Windows 7 Professional workstation withhigh performance Intel® CoreTM i7 processor this systemallows the user to install post processing and analysistools to operate on the recorded data. The system recordsdata to the native NTFS file system, providing immediateaccess to the recorded data.

Included with this system is Pentek’s SystemFlowrecording software. Optional GPS time and positionstamping allows the user to record this critical signalinformation.

Shown above is a 64-channel recording system utilizingtwo Pentek Cobalt 78662 PCIe boards. The 78662samples four input channels at up to 200 megasamplesper second, thereby accommodating input signals withup to 80 MHz bandwidth.

Factory-installed in the FPGA of each 78662 is apowerful DDC IP core containing 32 channels. Each ofthe 32 channels has an independent 32-bit tuningfrequency setting that ranges from DC to ƒs, where ƒs isthe A/D sampling frequency. All of the 8 channelswithin each bank share a common decimation settingthat can range from 16 to 8192, programmable in stepsof 8. For example, with a sampling rate of 200 MHz, theavailable output bandwidths range from 19.53 kHz to10.0 MHz. Each 8-channel bank can have its ownunique decimation setting supporting a different band-width associated with each of the four acquisition modules.

The decimating filter for each DDC bank acceptsa unique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% outputbandwidth is better than 100 dB.


6262626262


LLLLL-Band Signal P-Band Signal P-Band Signal P-Band Signal P-Band Signal Processing Systemrocessing Systemrocessing Systemrocessing Systemrocessing System


The Cobalt Model 78690 L-Band RF Tuner targetsreception and processing of digitally-modulated RFsignals such as satellite television and terrestrial wirelesscommunications. The 78690 requires only an antennaand a host computer to form a complete L-band SDRdevelopment platform.

This system receives L-Band signals between 925 MHzand 2175 MHz directly from an antenna. Signals abovethis range such as C Band, Ku Band and K band can bedownconverted to L-Band through an LNB (Low NoiseBlock) downconverter installed in the receiving antenna.

The Maxim Max2112 L-Band Tuner IC features alow-noise amplifier with programmable gain from 0 to65 dB and a synthesized local oscillator programmablefrom 925 to 2175 MHz. The complex analog mixertranslates the input signals down to DC. Basebandamplifiers provide programmable gain from 0 to 15 dBin steps of 1 dB. The bandwidth of the baseband lowpassfilters can be programmed from 4 to 40 MHz . TheMaxim IC accommodates full-scale input levels of -50 dBmto +10 dbm and delivers I and Q complex baseband outputs.

Figure 73

Analog Digital

Baseband IL-Band

x8 PCIe

LNA

Analog Local

Oscillator

Synthesizer

Q

Baseband AmpsAnalog Mixer

Analog Mixer

I

AnalogLowpass

FilterA/D

A/D

FPGA

VIRTEX-6

PC

WINDOWS

RF Input Baseband Q

MaximMAX2112

Pentek 78690 PCIe Board

LowpassFilter

Analog

The complex I and Q outputs are digitized by two200 MHz 16-bit A/D converters operating synchronously.

The Virtex-6 FPGA is a powerful resource forrecovering and processing a wide range of signalswhile supporting decryption, decoding, demodula-tion, detection, and analysis. It is ideal for interceptingor monitoring traffic in SIGINT and COMINTapplications. Other applications that benefit includemobile phones, GPS, satellite terminals, military telem-etry, digital video and audio in TV broadcasting satellites,and voice, video and data communications.

This L-Band signal processing system is ideal as afront end for government and military systems. Its smallsize adderesses space-limited applications. Ruggedizedoptions are also available from Pentek with the Models71690 XMC module and the 53690 OpenVPX board toaddress UAV applications and other severe environments.

Development support for this system is provided bythe Pentek ReadyFlow board support package for Windows,Linux and VxWorks. Also available is the Pentek GateFlowFPGA Design Kit to support custom algorithm development.


6363636363



Figure 74

8-8-8-8-8-Channel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming System

Two Model 53661 boards are installed in slots 1 and2 of an OpenVPX backplane, along with a CPU boardin slot 3. Eight dipole antennas designed for receiving2.5 GHz signals feed RF Tuners containing low noiseamplifiers, local oscillators and mixers. The RF Tunerstranslate the 2.5 GHz antenna frequency signal downto an IF frequency of 50 MHz.

The 200 MHz 16-bit A/Ds digitize the IF signalsand perform further frequency downconversion to baseband,with a DDC decimation of 128. This provides I+Q complexoutput samples with a bandwidth of about 1.25 MHz. Phaseand gain coefficients for each channel are applied tosteer the array for directionality.

The CPU board in VPX slot 3 sends commandsand coefficients across the backplane over two x4 PCIelinks, or OpenVPX “fat pipes”.

The first four signal channels are processed in theupper left 53661 board in VPX slot 1, where the 4-channelbeamformed sum is propagated through the 4X AuroraSum Out link across the backplane to the 4X Aurora SumIn port on the second 53661 in slot 2. The 4-channel localsummation from the second 53661 is added to the propa-gated sum from the first board to form the complete 8-channelsum. This final sum is sent across the x4 PCIe link to theCPU card in slot 3.

Assignment of the three OpenVPX 4X links on theModel 53661 boards is simplified through the use of acrossbar switch which allows the 53661 to operate witha wide variety of different backplanes.

Because OpenVPX does not restrict the use of serialprotocols across the backplane links, mixed protocolarchitectures like the one shown are fully supported. ➤

VPX P1

Slot 1

EP02

EP01

DP01

FP C

VPX P1

Slot 2

VPX P1

Slot 3 CPU

EP02

EP01

DP01

FPC

x4 PCIe

x4 PCIe

200 MHz

16-bit A/D

DDC 4G + Phase

PCIe

x4

I/F

200 MHz16-bit A/D

200 MHz

16-bit A/D

200 MHz

16-bit A/D

AURORA

BEAMFORMSUMMATION

DDC 3

G + Phase

DDC 2G + Phase

DDC 1

G + Phase

4X Sum In

4X Sum Out

Model 53661

x4 PCIe

200 MHz

16-bit A/D

DDC 4

G + Phase

PCIe

x4

I/F

200 MHz16-bit A/D

200 MHz

16-bit A/D

200 MHz

16-bit A/D

AURORA

BEAMFORMSUMMATION

DDC 3

G + Phase

DDC 2

G + Phase

DDC 1

G + Phase

4X Sum In

4X Sum Out

x4 PCIe

Model 53661

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

FP B

FP A

DP01

DP02

OpenVPX

CPUBoard

VPXBACKPLANE

4X Aurora


6464646464



Figure 75

8-8-8-8-8-Channel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo system

➤➤➤➤➤ Beamforming Demo System

The beamforming demo system is equipped with aControl Panel that runs under Windows on the CPUboard. It includes an automatic signal scanner to detectthe strongest signal frequency arriving from a testtransmitter. This frequency is centered around the50 MHz IF frequency of the RF downconverter. Oncethe frequency is identified, the eight DDCs are setaccordingly to bring that signal down to 0 Hz forsummation.

The control panel software also allows specifichardware settings for all of the parameters for the eightchannels including gain, phase, and sync delay.

An additional display shows the beam-formed pattern ofthe array. This display is formed by adjusting the phaseshift of each of the eight channels to provide maximum

sensitivity across arrival angles from -90O to +90O

perpendicular to the plane of the array.

The classic 7-lobe pattern for an ideal 8-elementarray for a signal arriving at 0O angle (directly in front ofthe array) is shown above. Below the lobe pattern is apolar plot showing a single vector pointing to thecomputed angle of arrival. This is derived from identify-ing the lobe with the maximum response.

An actual plot of a real-life transmitter is also shownfor a source directly in front of the display. In this casethe perfect lobe pattern is affected by physical objects,reflections, cable length variations and minor differencesin the antennas. Nevertheless, the directional informationis computed quite well. As the signal source is moved leftand right in front of the array, the peak lobe moves withit, changing the computed angle of arrival.

This demo system is available online at Pentek. Ifyou are interested in viewing a live demonstration, pleaselet us know of your interest by clicking on this link:

Beamforming Demo.

Beamforming Demo Control Panel Theoretical 7-lobe Beamforming Patern Real-Life Beamforming Patern

http://www.pentek.com/go/bfdemo


6565656565


• Reduction of DSP processing demands

• Very fast tuning

• Fast bandwidth selection

• Zero frequency drift and error

• Precise, stable filter characteristics

• Excellent dynamic range

SDR BenefitsSDR BenefitsSDR BenefitsSDR BenefitsSDR Benefits

Benefits of Software Defined Radio:

To summarize, we restate the major benefits:

SDRs can dramatically reduce the DSP requirements forsystems which need to process signals contained within a certainfrequency band of a wideband signal.

The fast tuning of the digital local oscillator and theeasy bandwidth selection in the decimating digital filterand interpolation filter make the SDR easy to control.

Since the entire circuitry uses digital signal process-ing, the characteristics are precise, predictable, and willnot drift with time, temperature or aging. This alsomeans excellent channel-to-channel matching and no needfor calibration, alignment or maintenance.

With the addition of FPGA technology, dramaticincreases in system density have been coupled with asignificantly lower cost per channel. Furthermore,FPGA technology allows one to incorporate customalgorithms right at the front end of these systems.

As we have seen, there are inherently many benefitsand advantages to when using SDR. We hope that thisintroduction has been informative. We stand ready todiscuss your requirements and help you configure acomplete SDR system.

For all the latest information about Pentek SDRs,DSP boards and data acquisition products, be sure tovisit Pentek’s comprehensive website regularly.

Pentek offers a comprehensive array of VMEbusDSP boards featuring the AltiVec G4 PowerPC fromFreescale and the TMS320C6000 family of processorproducts from Texas Instruments.

On-board processor densities range from one toeight DSPs with many different memory and interfaceoptions available.

The Models 4205 and 4207 I/O processor boardsfeature the latest G4 PowerPCs, accept PMC mezzaninesand include built-in Fibre Channel interfaces.

The Models 4294 and 4295 processor boards featurefour MPC74xx G4 PowerPC processors utilizing theAltiVec vector processor capable of delivering severalGFLOPS of processing power.

The Models 4292 and 4293 processor boards featurethe Texas Instruments latest TMS320C6000 family offixed-point DSPs that represent a 10-fold increase inprocessing power over previous designs.

Once again, the ability of the system designer tofreely choose the most appropriate DSP processor foreach software radio application, facilitates systemrequirement changes and performance upgrades.

Full software development tools are available for work-stations running Windows and Linux with many differentdevelopment system configurations available.

DSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbusDSP Boards for VMEbus


Figure 76

• Freescale Altivec G4PowerPC

• Texas InstrumentsC6000 DSPs

• Single, Dual, Quad andOctal Processor versions

• PMC, PMC/XMC, PCIand cPCI I/O peripherals

• VME/VXS platforms

Figure 77


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More links on the next page ➤

The following links provide you with additional information about the Pentek productspresented in this handbook: just click on the model number. Links are also provided to otherhandbooks or catalogs that may be of interest in your software radio development projects.

ModelModelModelModelModel DescriptionDescriptionDescriptionDescriptionDescription PPPPPageageageageage

7131 Multiband Receiver - PMC 197231 Multiband Receiver - 6U cPCI 197331 Multiband Receiver - 3U cPCI 197631A Multiband Receiver - PCI 195331 Multiband Receiver - 3U VPX 197141 Multiband Transceiver with Virtex-II Pro FPGA - PMC/XMC 207141-703 Conduction-cooled Multiband Transceiver with Virtex-II FPGA - PMC/XMC 207241 Multiband Transceiver with Virtex-II Pro FPGA - 6U cPCI 207341 Multiband Transceiver with Virtex-II Pro FPGA - 3U cPCI 207641 Multiband Transceiver with Virtex-II Pro FPGA - PCI 207741 Multiband Transceiver with Virtex-II Pro FPGA - Full-length PCIe 207841 Multiband Transceiver with Virtex-II Pro FPGA - Half-length PCIe 205341 Multiband Transceiver with Virtex-II Pro FPGA - 3U VPX 207141-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - PMC/XMC 217241-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - 6U cPCI 217341-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - 3U cPCI 217641-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - PCI 217741-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - Full-length PCIe 217841-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - Half-length PCIe 215341-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - 3U VPX 217141-430 Transceiver w. 256-Channel Narrowband DDC - PMC/XMC 227241-430 Transceiver w. 256-Channel Narrowband DDC - 6U cPCI 227341-430 Transceiver w. 256-Channel Narrowband DDC - 3U cPCI 227641-430 Transceiver w. 256-Channel Narrowband DDC - PCI 227741-430 Transceiver w. 256-Channel Narrowband DDC - Full-length PCIe 227841-430 Transceiver w. 256-Channel Narrowband DDC - Half-length PCIe 225341-430 Transceiver w. 256-Channel Narrowband DDC - 3U VPX 227142 Multichannel Transceiver with Virtex-4 FPGAs - PMC/XMC 237242 Multichannel Transceiver with Virtex-4 FPGAs - 6U cPCI 237342 Multichannel Transceiver with Virtex-4 FPGAs - 3U cPCI 237642 Multichannel Transceiver with Virtex-4 FPGAs - PCI 237742 Multichannel Transceiver with Virtex-4 FPGAs - Full-length PCIe 237842 Multichannel Transceiver with Virtex-4 FPGAs - Half-length PCIe 235342 Multichannel Transceiver with Virtex-4 FPGAs - 3U VPX 237142-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter - PMC/XMC 247242-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 6U cPCI 247342-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 3U cPCI 247642-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- PCI 247742-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Full-length PCIe 247842-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Half-length PCIe 245342-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 3U VPX 24


http://pentek.com/products/Detail.cfm?Model=7131

http://pentek.com/products/Detail.cfm?Model=5342-428



http://pentek.com/products/Detail.cfm?Model=7631A






































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7151 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 257251 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 6U cPCI 257351 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U cPCI 257651 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PCI 257751 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Full-length PCIe 257851 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Half-length PCIe 255351 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U VPX 257152 32-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 267252 32-Channel DDC with Quad 200 MHz, 16-bit A/D - 6U cPCI 267352 32-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U cPCI 267652 32-Channel DDC with Quad 200 MHz, 16-bit A/D - PCI 267752 32-Channel DDC with Quad 200 MHz, 16-bit A/D - Full-length PCIe 267852 32-Channel DDC with Quad 200 MHz, 16-bit A/D - Half-length PCIe 265352 32-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U VPX 267153 4-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC/XMC 277253 4-Channel DDC with Quad 200 MHz, 16-bit A/D - 6U cPCI 277353 4-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U cPCI 277653 4-Channel DDC with Quad 200 MHz, 16-bit A/D - PCI 277753 4-Channel DDC with Quad 200 MHz, 16-bit A/D - Full-length PCIe 277853 4-Channel DDC with Quad 200 MHz, 16-bit A/D - Half-length PCIe 275353 4-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U VPX 277156 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 287256 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI 287356 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI 287656 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 287756 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 287856 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 285356 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX 287158 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 297258 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI 297358 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI 297658 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 297758 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 297858 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 295358 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX 2971620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3078620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - PCIe 3053620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3072620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 6U cPCI 3073620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U cPCI 3074620 6-Channel 200 MHz A/D, DUC, 4-Channel 800 MHz D/A, Two Virtex-6 FPGAs - 6U cPCI 30













































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ModelModelModelModelModel DescriptionDescriptionDescriptionDescriptionDescription PPPPPageageageageage71621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - XMC 3178621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - PCIe 3153621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - 3U VPX 3172621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - 6U cPCI 3173621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - 3U cPCI 3174621 4-Channel 200 MHz A/D, DUC, 4-Channel 800 MHz D/A, Installed IP Cores - 6U cPCI 3178630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - PCIe 3271630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - XMC 3253630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 3U VPX 3272630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 6U cPCI 3273630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 3U cPCI 3274630 Two 1 GHz A/Ds, Two 1 GHz D/As, Two Virtex-6 FPGAs - 6U cPCI 3272640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 3373640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 3374640 2-Channel 3.6 GHz and 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGAs - 6U cPCI 3371640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC 3378640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - PCIe 3353640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U VPX 3353650 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3471650 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3478650 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - PCIe 3472650 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 6U cPCI 3473650 2-Channel 500 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U cPCI 3474650 4-Channel 500 MHz A/D, DUC, 4-Channel 800 MHz D/A, Two Virtex-6 FPGAs - 6U cPCI 3472651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 6U cPCI 3573651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U cPCI 3574651 2-Channel 500 MHz A/D, with DDCs, DUCs, 2-Channel 800 MHz D/A, Virtex-6 FPGA- 6U cPCI 3571651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3578651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - PCIe 3553651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3571660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - XMC 3678660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - PCIe 3653660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - 3U VPX 3672660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - 6U cPCI 3673660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGAs - 3U cPCI 3674660 8-Channel 200 MHz 16-bit A/D with Two Virtex-6 FPGAs - 6U cPCI 3671661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - XMC 3778661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - PCIe 3753661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U VPX 3772661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 6U cPCI 3773661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U cPCI 3774661 8-Channel 200 MHz 16-bit A/D with Installed IP Cores - 6U cPCI 37

















































6969696969




78662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - PCIe 3871662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - XMC 3853662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U VPX 3872662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 6U cPCI 3873662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U cPCI 3874662 8-Channel 200 MHz 16-bit A/D with Installed IP Cores - 6U cPCI 3871670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 3978670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - PCIe 3953670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX 3972670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U cPCI 3973670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U cPCI 3974670 8-Channel 1.25 GHz D/A with DUCs, and Two Virtex-6 FPGAs - 6U cPCI 3953690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U VPX 4071690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC 4078690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - PCIe 4072690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 6U cPCI 4073690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U cPCI 4074690 Dual L-Band RF Tuner with 4-Channel 200 MHz A/D and Two Virtex-6 FPGAs - 6U cPCI 4071760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - XMC 4178760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - PCIe 4153760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - 3U VPX 4172760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - 6U cPCI 4173760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - 3U cPCI 4174760 8-Channel 200 MHz 16-bit A/D with Two Virtex-7 FPGAs - 6U cPCI 416821-422 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS 426822-422 Dual 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS 436826 Dual 2 GHz 10-bit A/D - VME/VXS 446890 2.2 GHz Clock, Sync and Gate Distribution Board - VME 456891 System Synchronizer and Distribution Board - VME 467190 Multifrequency Clock Synthesizer - PMC 477290 Multifrequency Clock Synthesizer - 6U cPCI 477390 Multifrequency Clock Synthesizer - 3U cPCI 477690 Multifrequency Clock Synthesizer - PCI 477790 Multifrequency Clock Synthesizer - Full-length PCIe 477890 Multifrequency Clock Synthesizer - Half-length PCIe 475390 Multifrequency Clock Synthesizer - 3U VPX 477191 Programmable Multifrequency Clock Synthesizer - PMC 487291 Programmable Multifrequency Clock Synthesizer - 6U cPCI 487391 Programmable Multifrequency Clock Synthesizer - 3U cPCI 487691 Programmable Multifrequency Clock Synthesizer - PCI 487791 Programmable Multifrequency Clock Synthesizer - Full-length PCIe 487891 Programmable Multifrequency Clock Synthesizer - Half-length PCIe 485391 Programmable Multifrequency Clock Synthesizer - 3U VPX 48















































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7192 High-Speed Synchronizer and Distribution Board - PMC/XMC 497892 High-Speed Synchronizer and Distribution Board - PCIe 495392 High-Speed Synchronizer and Distribution Board - 3U VPX 497292 High-Speed Synchronizer and Distribution Board - 6U cPCI 497392 High-Speed Synchronizer and Distribution Board - 3U cPCI 497492 High-Speed Synchronizer and Distribution Board - 6U cPCI 499190 Clock and Sync Generator for I/O Modules - Rack mount 509192 High-Speed System Synchronizer Unit - Rack mount 51RTS 2701 2-Channel RF/IF 125 MS/sec Rack-mount Recorder 52RTS 2706 8-Channel RF/IF 200 MS/sec Rack-mount Recorder 53RTS 2715 2-Channel 10 Gigabit Ethernet Rack-mount Recorder 54RTS 2721 2-Channel RF/IF 125 MS/sec Portable Recorder 55RTR 2726 4-Channel RF/IF 200 MS/sec Rugged Portable Recorder 56RTR 2746 8-Channel RF/IF 200 MS/sec Rugged Rack-mount Recorder 57RTR 2755 2-Channel 10 Gigabit Ethernet Rugged Rack-mount Recorder 58 — Pentek SystemFlow Recording Software 594207 PowerPC and FPGA I/O Processor - VME/VXS 62

Click here Putting FPGAs to Work in Software Radio Systems HandbookClick here Critical Techniques for High-Speed A/D Converters in Real-Time Systems HandbookClick here High-Speed Switched Serial Fabrics Improve System Design HandbookClick here High-Speed, Real-Time Recording SystemsClick here Cobalt Virtex-6 Product CatalogClick here Pentek Product CatalogClick here Model 4207 PowerPC and FPGA I/O Processor Board Brochure

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Software Defined Radio Handbook

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