Sige Seg Growth
1
1.0E-12 1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 0 200 400 600 800 1000 Ion [uA/um] Ioffs [A/um] Si SiGe 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.0 1.1 1.2 1.3 1.4 1. EOT (nm) Vtlin_L10W1 (V) Si SiGe -210mV b) SiGe SEG growth for buried channels p-MOS devices A.Hikavyy, R.Loo, L.Witters S. Takeoka * , J. Geypen, B.Brijs, C. Merckling, M.Caymax and J. Dekoster IMEC, Kapeldreef 75, B-3001 Leuven, Belgium * Panasonic, Kapeldreef 75, B-3001 Leuven, Belgium SiGe buried channel p-MOS devices are being intensively investigated for future low-power high – performance applications beyond the 22-nm technology generation [1-5]. It has been shown that an improvement of the p-MOS device is two-fold: a favorable V t shift which depends on Ge content can be achieved; while the device gets an additional boost due to enhanced mobility in the SiGe channel. The first IMEC’s attempt to incorporate a SiGe buried channel with Ge concentrations within 20-30% and NO oxide gate dielectric/poly-gate was made in 2002 [1, 2]. This work was initiated by the growing interest in the high mobility channels as an alternative to Si. Later work in which the SiGe buried channel was used together with a poly or FUSI gate and a high-k dielectric was mostly focused on Vt adjustment, though devices improvement due to increased mobility was noticed as well [6]. In both cases devices were made in the IMEC’s 200 mm pilot line. Due to increased interest in the device community, SiGe process has been recently combined with poly/metal gate/high-k in the state-of-the-art 300 mm IMEC’s pilot line and further extended to higher Ge concentrations (45 and 60%). It must be mentioned that in our integration scheme deposition of SiGe channel is followed by Si capping layer deposition. The purpose of this Si layer is to suppress the scatter of holes in the SiGe channel on the Si/SiO 2 interface [1,2] and enable use of a conventional high-k gate dielectric process. Selective deposition of Si capping layer is not straightforward especially on SiGe with high Ge deposition which requires relatively low temperatures in order to avoid the SiGe layer relaxation. In this contribution, we will firstly discuss different metrology techniques used during the development of epi processes. It will be shown that in order to assure a high layers quality in-line monitoring a combination of different techniques is indispensable. Secondly we will shortly review the deposition process of Si 0.75 Ge 0.25 buried channel and present results obtained on the devices manufactured in the 300 mm pilot line (Fig. 1). Fig.1 Electrical results obtained on the devices with Si 0.75 Ge 0.25 buried channel. a) I on /I off comparison with a Si reference; b) measured V t shift for devices with Si 0.75 Ge 0.25 buried channel. Thirdly, we will discuss in depth the development of Si 0.55 Ge 0.45 and Si 0.40 Ge 0.60 selective epitaxial growth (SEG) together with Si capping layer processes. It will be shown that in order to deposit high quality SiGe layers with high Ge concentration (Fig. 2) the process temperature has to be relatively low in order to avoid layer relaxation due to Stranski-Krastanov growth mode. Fig.2 TEM picture showing a high quality of Si 0.55 Ge 0.45 /SiCap buried channel layers. We will also elaborate the relation between critical thickness and Ge content. Despite the existing reports [3, 5] stating that SiGe with high Ge content can be grown thicker than the theoretical critical thickness we show that this point should be addressed more carefully (Fig. 3). Fig.3 SEM pictures of two Si 0.60 Ge 0.40 layers deposited at 650 0 C. a) 25 nm, b) 15 nm. Acknowledgement All epi experiments mentioned in this contribution were performed either on blanket or patterned Si wafers in a single-wafer ASM Epsilon® 3200 reactor. This work has been done in the frame of IMEC’s IIAP Planar-Emerald program. References [1] N.Collaert, P. Verheyen, K.De Meyer, IEEE Transactions on nanotechnology, Vol.1, N4, pp190- 194, 2002 [2] N. Collaert, P. Verheyena, K. De Meyer, R.Loo and M. Caymax, ESSDERC, pp 263-266, 2002 [3] M.L.Lee, A.Fitzgerald, M.T.Bulsara, M.T.urrie, A.Lochtefeld, Journal of Applied Physics 97, 011101 (2005) [4] P.Majhi, et al., IEEE Electron Device Letters, Vol.29, N1, January 2008 [5] S.H.Lee et al., IEEE Electron Device Letters, Vol.29, N9, September 2008 [6] Loo, et al. ISTDM 2006, pp.168-169 [7] J.M. Hartmann, F. Gonzatti, F. Fillot, T. Billon, Journal of Crystal Growth 310 (2008) 62–70 a) a) b) Si SiGe Si cap Glue 216th ECS Meeting, Abstract #2364, © The Electrochemical Society
description
help for the study of buried si ge
Transcript of Sige Seg Growth
1.0E-12
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
0 200 400 600 800 1000Ion [uA/um]
Ioffs
[A/u
m]
Si
SiGe
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.0 1.1 1.2 1.3 1.4 1.EOT (nm)
Vtli
n_L1
0W1
(V)
Si
SiGe
-210mV
b)
SiGe SEG growth for buried channels p-MOS devices
A.Hikavyy, R.Loo, L.Witters S. Takeoka* , J. Geypen, B.Brijs, C. Merckling, M.Caymax and J. Dekoster
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
*Panasonic, Kapeldreef 75, B-3001 Leuven, Belgium
SiGe buried channel p-MOS devices are being
intensively investigated for future low-power high –performance applications beyond the 22-nm technology generation [1-5]. It has been shown that an improvement of the p-MOS device is two-fold: a favorable Vt shift which depends on Ge content can be achieved; while the device gets an additional boost due to enhanced mobility in the SiGe channel.
The first IMEC’s attempt to incorporate a SiGe
buried channel with Ge concentrations within 20-30% and NO oxide gate dielectric/poly-gate was made in 2002 [1, 2]. This work was initiated by the growing interest in the high mobility channels as an alternative to Si. Later work in which the SiGe buried channel was used together with a poly or FUSI gate and a high-k dielectric was mostly focused on Vt adjustment, though devices improvement due to increased mobility was noticed as well [6]. In both cases devices were made in the IMEC’s 200 mm pilot line. Due to increased interest in the device community, SiGe process has been recently combined with poly/metal gate/high-k in the state-of-the-art 300 mm IMEC’s pilot line and further extended to higher Ge concentrations (45 and 60%).
It must be mentioned that in our integration scheme deposition of SiGe channel is followed by Si capping layer deposition. The purpose of this Si layer is to suppress the scatter of holes in the SiGe channel on the Si/SiO2 interface [1,2] and enable use of a conventional high-k gate dielectric process. Selective deposition of Si capping layer is not straightforward especially on SiGe with high Ge deposition which requires relatively low temperatures in order to avoid the SiGe layer relaxation.
In this contribution, we will firstly discuss different metrology techniques used during the development of epi processes. It will be shown that in order to assure a high layers quality in-line monitoring a combination of different techniques is indispensable.
Secondly we will shortly review the deposition process of Si0.75Ge0.25 buried channel and present results obtained on the devices manufactured in the 300 mm pilot line (Fig. 1).
Fig.1 Electrical results obtained on the devices with Si0.75Ge0.25 buried channel. a) Ion/Ioff comparison with a Si reference; b) measured Vt shift for devices with Si0.75Ge0.25 buried channel.
Thirdly, we will discuss in depth the development of Si0.55Ge0.45 and Si0.40Ge0.60 selective epitaxial growth (SEG) together with Si capping layer processes.
It will be shown that in order to deposit high quality SiGe layers with high Ge concentration (Fig. 2) the process temperature has to be relatively low in order to avoid layer relaxation due to Stranski-Krastanov growth mode.
Fig.2 TEM picture showing a high quality of Si0.55Ge0.45 /SiCap buried channel layers.
We will also elaborate the relation between critical thickness and Ge content. Despite the existing reports [3, 5] stating that SiGe with high Ge content can be grown thicker than the theoretical critical thickness we show that this point should be addressed more carefully (Fig. 3).
Fig.3 SEM pictures of two Si0.60Ge0.40 layers deposited at 6500C. a) 25 nm, b) 15 nm.
Acknowledgement
All epi experiments mentioned in this contribution were performed either on blanket or patterned Si wafers in a single-wafer ASM Epsilon® 3200 reactor.
This work has been done in the frame of IMEC’s IIAP Planar-Emerald program.
References
[1] N.Collaert, P. Verheyen, K.De Meyer, IEEE Transactions on nanotechnology, Vol.1, N4, pp190-194, 2002
[2] N. Collaert, P. Verheyena, K. De Meyer, R.Loo and M. Caymax, ESSDERC, pp 263-266, 2002
[3] M.L.Lee, A.Fitzgerald, M.T.Bulsara, M.T.urrie, A.Lochtefeld, Journal of Applied Physics 97, 011101 (2005)
[4] P.Majhi, et al., IEEE Electron Device Letters, Vol.29, N1, January 2008
[5] S.H.Lee et al., IEEE Electron Device Letters, Vol.29, N9, September 2008
[6] Loo, et al. ISTDM 2006, pp.168-169
[7] J.M. Hartmann, F. Gonzatti, F. Fillot, T. Billon, Journal of Crystal Growth 310 (2008) 62–70
a)
a) b)
SiSiGe Si cap
Glue
216th ECS Meeting, Abstract #2364, © The Electrochemical Society
