1

Role of HighRole of High--K Gate Dielectrics K Gate Dielectrics and Metal Gate Electrodes in and Metal Gate Electrodes in

Emerging Nanoelectronic DevicesEmerging Nanoelectronic Devices

Robert Chau

Intel FellowDirector of Transistor Research

and Nanotechnology

Technology and Manufacturing GroupIntel Corporation

June 22, 2005

2

ContentsIntroduction

Review of physics of high-K on Si

Emerging nanoelectronic devices– III-V nanoelectronics– Carbon nanotube FETs– Semiconductor nanowire FETs

Benchmarking emerging non-Si nanoelectronic devices versus conventional planar and non-planar Si transistors

Role of high-K/metal-gate in emerging nanoelectronic devices for future, potential high-performance and low-power logic applications

Summary

3

Transistor Nanotechnology

Si Substrate

Metal Gate

High-kTri-Gate

S

G

D

III-V

S

50 nm35 nm

30 nm

SiGe S/D PMOS

Uniaxial strain

1.2nm thin gate oxide

90 nm65 nm

45 nm32 nm

20032005

20072009

2011+

Technology Generation

20 nm 10 nm

Manufacturing Development Research

SiGe S/D PMOS

Uniaxial Strain

1.2nm thin gate oxide

Focus of this talk: emerging nanoelectronic devices

5 nm5 nm

5 nm

SemiconductorNanowire Carbon

Nanotube

Emerging Nanoelectronic

Devices

Note: Future options subject to change

Si

4

Experimental 10nm Si MOS Transistor

10nm Si transistors produced in research labs− Still a switch with gain

Need to benchmark emerging non-Si nanoelectronic research devices versus state-of-the-art Si research transistors

LG = 10nm

0

200

400

600

0 0.2 0.4 0.6 0.8DRAIN VOLTAGE [V]

DR

AIN

CU

RR

ENT

[A/µ

m]

00 0.2 0.4 0.6 0.80 0.2 0.4 0.6 0.80.6

0.75V0.65V0.55V

0.45V

0

200

400

600

0 0.2 0.4 0.6 0.8DRAIN VOLTAGE [V]

DR

AIN

CU

RR

ENT

[A/µ

m]

00 0.2 0.4 0.6 0.80 0.2 0.4 0.6 0.80.6

0.75V0.65V0.55V

0.45V

Si

Source: R. Chau et. al., Intel Corp., 61st DRC, June 2003

5

• High-K phonons and gate plasmons modeled as electric dipoles

• Doped polySi gate (~1018 cm-3): When ETO < EGATE-PLASMON < ELO,in-resonance condition occurs which degrades channel mobility

• Metal gate (>1020 cm-3): Off-resonance condition weakens phonon-carrier coupling, hence channel mobility is recovered

TCAD Simulation*Poly-Si Gate

Si channel

High-K dielectric

EG

ELO

E’LO E’GETOT=E’LO+E’G

Poly-Si Gate

Si channel

High-K dielectric

EG

ELO

E’LO E’GETOT=E’LO+E’G

Metal Gate

Si channel

High-K dielectric

EG

ELO

E’LO E’GETOT=E’LO-E’G

Metal Gate

Si channel

High-K dielectric

EG

ELO

E’LO E’GETOT=E’LO-E’G

Poly-Si gate(In resonance)

Metal gate(off resonance)

* Source: R. Kotlyar et. al., Intel Corp., IEDM 2004

Review of High-K Physics on Si

EGATE-PLASMONELO

Mobility dip

ETO

6

Review of High-K Physics on Si

• Surface phonon scattering in high-K is primary source of mobility degradation

• Metal gate is effective for screening phonon scattering and improves channel mobility

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

3.5E-05

4.0E-05

4.5E-05

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

Effective Vertical Field (MV/cm)

d(1/

ueff)

/dT

Si/High-K/PolySi

Si/SiO2/PolySi

Phonon scattering

0

200

400

600

800

1000

1200

0 0.5 1 1.5Effective Vertical Field (MV/cm) Su

rfac

e Ph

onon

Lim

ited

Mob

ility

(cm

2 /V.s

)

P860

T = 25 CSi/High-K/PolySi

Si/SiO2/PolySi

Si/High-K/Metal-Gate

Channel mobility

Experimental Measurements Inverse Modeling

Source: R. Chau et. al., Intel Corp., IEEE EDL, June 2004

7

Review of High-K Physics on Si

NDK

SDK

4.054.15

4.35

4.55

4.75

4.95

5.15

N+

pol

y

P+

pol

y

P-m

etal

N-m

etal

Met

al A

Met

al B

Met

al C

Met

al D

Met

al E

Met

al F

Met

al G

Met

al H

Met

al I

Met

al J

GATE ELECTRODE MATERIALS

WO

RK

FUN

CTI

ON

[eV

] P-type Metal on High-K

N-type Metal on High-K

N+ Poly-Si/SiO2

P+ Poly-Si/SiO2

Mid-gap Metals on High-K

NDK

SDK

4.054.15

4.35

4.55

4.75

4.95

5.15

N+

pol

y

P+

pol

y

P-m

etal

N-m

etal

Met

al A

Met

al B

Met

al C

Met

al D

Met

al E

Met

al F

Met

al G

Met

al H

Met

al I

Met

al J

GATE ELECTRODE MATERIALS

WO

RK

FUN

CTI

ON

[eV

] P-type Metal on High-K

N-type Metal on High-K

N+ Poly-Si/SiO2

P+ Poly-Si/SiO2

Mid-gap Metals on High-K

• Gate electrodes with the “right” work function are required for high-performance CMOS applications

Source: R. Chau, Intel Corp., AVS ICMI, March 2004

8

Review of High-K Physics on Si

• Example of high-performance CMOS transistors on bulk-siliconwith high-K/metal-gate

– Correct VTH’s, high-mobility, low gate leakage

Source: R. Chau et. al., Intel Corp., IEEE EDL, June 2004

9

Conventional Planar and Non-Planar Si Transistors

NMOS

Si Planar

Si Tri-Gate

Si Tri-Gate

Si Planar

NMOS0

0.3

0.6

0.9

1.2

1.5

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

ION / IOFF

GA

TE D

ELA

Y C

V/I

[ps

]

35nm Si Tri-Gate (VCC=1.1V)[High-K/metal-gate]

40nm Si Planar (VCC=1.1V)[Poly/SiO2]

70nm Si Planar (VCC=1.3V)[Poly/SiO2]

60nm Si Tri-Gate (VCC=1.3V)[Poly/SiO2]

NMOS

Need to benchmark emerging non-Sinanoelectronic devices versus these conventional planar and non-planar Si NMOS transistors

10

Conventional Planar and Non-Planar Si Transistors

PMOS

Si Planar

Si Tri-Gate

Si Planar

Si Tri-Gate

Si Planar

PMOS

Need to benchmark emerging non-Sinanoelectronic devices versus these conventional planar and non-planar Si PMOS transistors

0.0

0.5

1.0

1.5

2.0

2.5

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

ION / IOFF

GA

TE D

ELA

Y C

V/I

[ps

]

35nm Si Tri-Gate (VCC=1.1V)[High-K/metal-gate]

40nm Si Planar (VCC=1.1V)[Poly/SiO2]

70nm Si Planar (VCC=1.3V)[Poly/SiO2]

PMOS

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Emerging Nanoelectronic Devices

• Semiconductornanowires withhigh-K gate dielectrics

Lg = 10 nm

(a)

Lg = 10 nm Gate

Source

Sibody

Drain

Gate

Source Drain

Source

CNTSingle -wallD = 1.4 nm

Gate(Pt)

Drain(Pd)

Lg = 75 nm

(d)

Source

CNTSingle -wallD = 1.4 nm

Gate(Pt)

Drain(Pd)

Lg = 75 nm

(d)

Source

CNTSingle -wallD = 1.4 nm

Gate(Pt)

Drain(Pd)

Lg = 75 nm

III-V

Gate

DrainSource

Source

(c)

Multiepitaxial

layersGate

DrainSource

Source

(c)

Multiepitaxial

layersGate

DrainSource

Source

Multiepitaxial

III-V layers5 nm5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

5 nm5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

• Carbon nanotube FETswith high-K gate dielectrics

• III-V quantum-well (Q-W)transistors (high-K gate dielectric is currently absent in III-V but required for logic applications) Role of High-K/metal-gate:

– enabling continued equivalent gate oxide thickness scaling and hence high performance, and controlling gate leakage

– required for high ION/IOFF ratios in III-V Q-W devices for logic

12

Intrinsic Gate Delay CV/I for PMOS

• CNT shows significant p-ch CV/I improvement over Si– CNT has >20X higher effective p-ch mobility than Si

• Si nanowires currently do not show improvement over Si

D = 4 to 35nmD = 1 to 2.5nm

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Energy-Delay Product for PMOS

14

Carbon Nanotube (CNT) p-FET withHigh-K/Metal-Gate

CNT FET exhibits low gate dielectric leakage with the use of high-KAmbipolar leakage identified as the major source of parasitic leakage in CNT (due to metal-CNT Schottky S/D contacts)

Drain current(ID)Source current(IS)

Gate leakage (IG)

15

Capacitance of High-K/Metal-Gate onCarbon Nanotubes (CNT)

High-K dielectric constant has a stronger effect than high-K dielectric thickness in increasing gate capacitance of carbon nanotube FETs

*m/aF400~C

RTR

2ln

K2C

CCC

QM

PHYS

0OX

1QM

1OX

1TOTAL

µ

+πε

=

+= −−−

High-K Dielectric

Metal Gate

TPHYS

D=2R

* Guo et al, Applied Physics Letters 2002

CNT

16

CV/I versus ION/IOFF Ratio

35nm Si Tri-Gate PMOS (VCC=1.1V)

40nm Si PMOS (VCC=1.1V)70nm Si PMOS (VCC=1.3V)

50nm CNT p-FET (VCC=0.3V)[Metal-CNT S/D contactscause ambipolar conduction]

80nm CNT n-FET (Vcc=0.5V)[Chemically-doped junctiondelays ambipolar conduction]

For ION/IOFF < 100, CNT p-FET shows improvement over Si due to higher channel mobility and lower VCC usedHighest ION/IOFF ratio in CNT limited by ambipolar conduction due to metal-CNT S/D contacts; chemically-doped junctions delays ambipolar conduction despite poor CV/I performance

17

Physics of Silicon Nanowires

• Previous understanding: Reducing wire diameter reduces availabledensity of states for elastic scattering (1D), thus improving mobility

• Current understanding of Si nanowires– Impact of phonon scattering becomes significant above 50 K– Mobility at room temperature decreases with reducing diameter (< 10nm)

due to phonon scattering– Performance of Si nanowires limited by phonon scattering at room temp

TCAD Simulation (R. Kotlyar, Intel, APL 2004) Measurements

Room Temp.

3nm5nm

15nm9nm

Increasing temperature

18

• n-channel CNT not as well established as p-channel CNT

• III-V (e.g. InSb) devices show significant CV/I improvement over Si– III-V devices have >50X higher effective n-ch mobility than Si– III-V devices operated at low VCC = 0.5V

Intrinsic gate delay CV/I for NMOS

19

Energy-Delay Product for NMOS

20

III-V Transistors for Low VCC

0

20

40

60

80

100

120

140

160

180

1 10 100 1000Power Dissipation (mW/mm)

Cut

off F

requ

ency

, fT

(GH

z)

InSb Vds=0.3VInSb Vds=0.5VInSb Vds=0.6VInSb Vds=0.7VSi Vds=0.5VSi Vds=0.7VSi Vds=1VSi Vds=1.2V

InSb QWFET(LG=200nm)

Si NMOS(LG=80nm)

5-10XLower PowerDissipation

0.5V 1.2V

0.3V

Teffm

00

f21

vL

gWLC

IWLVC

ICV

π====

GATE

DRAIN

DRAIN

SOURCE

III-V (InSb) Q-W Transistor

(Schottky metalgate with no gate dielectric)

Source: Intel & QinetiQ, ICSICT, Oct 2004

21

IIIIII--V Nanoelectronics:V Nanoelectronics:EnergyEnergy--Delay Product vs Device Gate LengthDelay Product vs Device Gate Length

• InSb QW-FETs have the lowest NMOS energy-delay product(highest mobility and lowest operating VCC)

n-FET

Si MOSFETs

InSbQuantum-well/ Barrier

InSb/AlInSb

22

IIIIII--V Nanoelectronics:V Nanoelectronics:HighHigh--K Required to Eliminate Schottky IK Required to Eliminate Schottky IGATEGATE

0.0001

0.001

0.01

0.1

1

-0.8 -0.6 -0.4 -0.2 0Gate Voltage, VGS [V]

Dra

in a

nd G

ate

Cur

rent

[mA

/µ

m] VDS=0.5V

VDS=50mV

VDS=0.5V

VDS=50mV

IDS

SchottkyIGATE

QWFET

Requires a gate stack to eliminateSchottky IGATE, e.g. high-K/metal-gate

Non Self-aligned Ohmic contacts

Schottky Barrier Metal

s.i. GaAs substrate for epitaxial growth

Remote DopingLayers

High electron mobility InSbquantum well

Higher band-gap matrix AlxIn1-xSb for

reduced junction leakage

metamorphic AlInSb buffer layer

Non Self-aligned Ohmic contacts

Schottky Barrier Metal

s.i. GaAs substrate for epitaxial growth

Remote DopingLayers

High electron mobility InSbquantum well

Higher band-gap matrix AlxIn1-xSb for

reduced junction leakage

metamorphic AlInSb buffer layer

Source: Intel & QinetiQ, ICSICT, Oct 2004

23

IIIIII--V Nanoelectronics:V Nanoelectronics:HighHigh--K/MetalK/Metal--Gate Required to Improve IGate Required to Improve IONON/I/IOFFOFF

Due to SchottkyGate leakage

n-FET

• ION /IOFF ratio of InSb QWFET is limited by Schottky gate leakage

24

One of the Grand Challenges in III-V Nanoelectronics for logic: Compatibility of III-V and High-K/Metal-gate Stack

III-V/High-K/metal-gate

High-K

High-K/metal-gateon III-V

Fast Surface States

2E-7

4E-7

6E-7

8E-7

1E-6

-1 -0.5 0 0.5 1VG [V]

CG [

F/cm

²]

on III-V

25

SummaryHigh-K/metal-gate will be one of the key enablers for emerging non-Si nanoelectronic devices for future potential high-performance, low-power logic applications

High-K/metal-gate stacks are required for improving the Ion/Ioff ratio of III-V quantum-well transistors for future potential low-power, high-speed logic applications