III-V MOSFETs: A Study on High-k Gate Dielectrics · 2.2.2 Electron-beam Evaporation of high-k...

Master thesis

III-V MOSFETs: A Study on High-k

Gate Dielectrics

Supervisor

Professor Hiroshi Iwai

Department of Electronics and Applied Physics

Interdisciplinary Graduate School of Science and Engineering Tokyo Institute of Technology

08M53410

Darius Zade

2

Contents

Chapter 1. Introduction

1.1 On the Scaling Limits of Planar Si MOS Devices

1.2 Properties of Compound Semiconductor MOS devices

1.3 Implementing high-k Dielectric Gate Stacks for III-V

Channels

1.4 Purpose of this Study………………………………………………

Chapter 2. Fabrication and Characterization Method

2.1 InGaAs MOS Capacitors Fabrication

2.2 Fabrication Process

2.2.1 Substrate Cleaning

2.2.2 Electron-beam Evaporation of high-k Dielectrics

2.2.3 RF Sputtering of Gate Electrode

2.2.4 Photolithography and Metal Gate Etching

2.2.5 Thermal Annealing Process

2.2.6 Thermal Evaporation of Al Layer (back contact)

2.3 Characterization Method

2.3.1 Capacitance-Voltage (C-V ) Characteristics

2.3.2 Leakage Current Density-Voltage (J-V )characteristics

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2.3.3 Interface Trap Density Extraction by Conductance Method

Chapter 3. Electrical Characteristics of In0.53Ga0.47As MOS Capacitors

3.1 Introduction

3.2 Leakage Current Density

3.3 C-V Characteristics

3.4 Frequency Dispersion Analysis

3.5 Interfacial State Density

Chapter 4. Surface Analysis

4.1 Introduction

4.2 Surfaces of III-V material

4.3 Electrical Behavior of Interface Passivated Capacitors

Chapter 5. Conclusion

5.1 Conclusion of This Study

5.2 Challenges for III-V MOSFETs

5.3 Discussion on the Extension of the study

References

Acknowledgments

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Chapter 1.

Introduction

1.1 On the Scaling Limits of Planar Si MOS Devices

1.2 Properties of Compound Semiconductor MOS devices

1.3 Implementing high-k Dielectric Gate Stacks

for III-V Channels

1.4 Purpose of this Study

5

1.1 On the Scaling Limits of Planar Si MOS

Devices

Throughout the latter third of the 20th century Moore’s Law has ruled the

growth of the semiconductor industry. This astounding exponential growth

at a compound rate of 40% per year every 40 years has been the product of

higher packing densities and larger chip sizes, where the higher packing

densities have been achieved both by finer lithography patterning as well as

Figure 1-1. Scaling down of the number of bit in DRAM and the number of

transistors in intel’s CPU.

by innovative self aligned device structures. The non-lithographic

contribution has been very substantial, since while feature sizes have been

6

reduced by a factor of ~102 during this time, circuit count has increased by a

factor of ~108 as can be seen in figure 1-1.

Now silicon CMOS is approaching the end of its scaling path, although there

is some uncertainty as to exactly where the endpoint is. A Subset of Frank’s

table is shown in table 1-1 about the relation of CMOS size and their

performance and power consumption. For bulk silicon, scaling can be carried

down to ~15 nm for the high performance designs but only to ~25 nm for the

low-power designs and according to latest ITRS roadmap, this predicament

will be reached before 2014, by which point we will be unable to implement

low-power designs in the most aggressive scaled technology.

Table 1-1 Application-dependant limits for various performance levels and bulk Si or double-gate (DG)

7

1.2 Properties of Compound Semiconductor

MOS devices

As we continue to aggressively scale transistors in accordance with Moore’s

Law to sub-20-nm dimensions, it becomes increasingly difficult to maintain

the required device performance. Currently, the increase in drive currents

for faster switching speeds at lower supply voltages is largely at the expense

of an exponentially growing leakage current, which leads to a large standby

power dissipation. To address the scaling challenge, both industry and

academia have been investigating alternative device architectures and

materials, among which III-V compound semiconductor transistors stand out

as promising candidates for future logic applications because their light

effective masses lead to high electron mobilities (table 1-2) and high

on-currents, which should translate into high device performance at low

supply voltage. Recent innovations on III-V transistors include sub- 100nm

gate-length; high performance InGaAs buried channel and surface channel

MOSFETs.

8

Table 1-2 Electron mobility of various semiconductors

1.3 Implementing high-k Dielectric Gate

Stacks for III-V Channels

A key restriction enabling widespread use of III-V materials is the lack of a

high quality, natural insulator for III-V substrates like that available for the

SiO2/Si materials system. The prospect of impending scaling challenges for

technologies based on silicon metal oxide semiconductor field effect

transistor devices has brought renews focus on the use of alternate surface

channel materials from the III-V compound semiconductor family. The

performance of the traditional MOSOFET device structure is dominated by

defects at the semiconductor/oxide interface, which in turn requires a high

quality semiconductor surface. Hence, the interfacial chemistry has quite a

9

big impact on the resultant device electrical behavior.

As III-V materials lack a good native oxide interface, a great deal of research

is focused on decreasing high-k III-V interface states. Additionally, there are

several other concerns associated with high-k dielectrics. These include

Coulomb scattering from bulk oxide charges and interface fixed charges,

surface roughness scattering, remote phonon scattering, and dielectric

charge trapping associated with reliability problems. A list of issues which

need to be understood and addressed concurrently are listed below:

• the impact of manufacturable ex situ and in situ high-k/higher-k

dielectrics;

• conventional process routes and materials such as HfO2, ZrO2, Al2O3 to

form quality gate stacks;

• engineering the high-k-channel interface by several means including

evaluation of bi-layer schemes to address the dual targets of thin EOT and

low Dit;

• defect states and their influence on device properties via detailed electrical

and physical characterization and helped in the development of schemes to

passivate/eliminate these defects.

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Figure 1-2. a) EOT-Jg of high-k/ In0.53Ga0.47As MOS capacitors in comparison with high-k/Si and polySi/SiO2/Si MOS devices; b) TEM cross-section of InGaAs/ALD ZrO2, Al2O3 and LaAlO3 interfaces with mid-gap Dit.

1.4 Purpose of this Study

InGaAs as one of the most promising candidates of III-V MOSFET with

alternative channel material,needs to overcome the following challenges in

order to acquire a prominent presence in today’s competitive semiconductor

industry.

-MOS interface/gate stack technology

* interfacial control layer

* high-k film formation

* understanding physical origin of interface properties

- Low resistance S/D formation technology

-III-V channel formation technology

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In this study we focus on interface/gate stack issues and on achieving good electrical properties from high-k/III-V capacitors by controlling the surface chemistry of the InGaAs substrates. X-ray studies as well as CV characterization was performed and La and Pr oxides were used to compare the effect of interfacial state densities.

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Chapter 2.

Fabrication and Characterization

Method




13


Figure 2-1 shows the fabrication flow of InGaAs MOS Capacitors. InGaAs

capacitors were fabricated on p-type In0.53Ga0.47As (100) substrate,

epitaxially grown on a p-type InP substrate. The InGaAs layer thickness was

at 100nm doped at a density of 5.2×1017 with Zn. The buffer InP layer below

the InGaAs layer had a thickness of 300nm with a 1.1×1018 Zn dopant

density. The defect density of the InGaAs layer was lower than 10

Particles/cm2 and a uniform doping density confirmed with CV calibration

from the substrate vendor. III-V substrates were chemically cleaned by

acetone- ethanol and later dipped in concentrated hydrofluoric acid,

depending on the experiment passivated by (NH4)2S solution and HMDS and

finally rinsed by de-ionized (DI) water. High-k gate materials (La2O3 , PrOx)

were deposited by electron-beam evaporation in an ultra high vacuum at a

pressure of 10-6 Pa and at room temperature. After high-k deposition, 50

nm-thick tungsten(W) layer was in-situ deposited using sputtering without

exposing the wafers to air to minimize high-k layer moisture absorption or

contamination. W gate electrode was patterned by reactive ion etching (RIE)

using SF6 chemistry to form gate electrode for MOS capacitors. Wafers were

then post-metallization annealed (PMA) using a rapid thermal annealing

(RTA) furnace in forming gas (F.G) (N2:H2=97%:3%) ambient at various

temperatures. Finally, backside Al contacts for ohmic contact were formed.

The device structure is shown in figure 2-2.

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Figure 2-1 Fabrication process flows of high-k gated MOS capacitors

High-k

300nm,p+-InP50nm-Al

100nm,In0.53Ga0.47AsZn:5.2×1017

W,50nm

Figure 2-2 Schematic illustration of fabricated MOSCAP of W/high-k/InGaAs

15


2.2.1 Substrate Cleaning

Various substrates surface treatment methods were experimented to

evaluate the initial cleaning effects on electrical properties of fabricated

MOS capacitors. All the substrates were first cleaned by acetone and ethanol

in ultrasonic environment. Subsequently the substrates were dipped in 20%

HF for 2 minutes until a clean and uniform surface was achieved. To

evaluate the passivation effects some substrates were subjected to a 7%

(NH4)2S solution for 30 minutes at room temperature or for 5 minutes at

50oC. HMDS layer was formed on top of some substrates with indirect

evaporation deposition on a hot plate. To form SiO layers Ozone oxidization

at room temperature for 5 minutes was employed.

2.2.2 Electron-beam Evaporation of high-k

Dielectrics

In this study, high-k gate dielectrics were deposited in ultra high vacuum by

electron-beam evaporation method. The background pressure in growth

chamber reached as high as 10-7 Pa and was approximately 10-6 Pa during

deposition. High-k material tablets are heated by 5kV electron beam near

the source and La-oxide begin to evaporate once the source temperature is

16

high enough and start to deposit on the substrate due to ultra low pressure of

the chamber. Film thickness counter is used for real time physical thickness

of the film calibrated before the experiment. Figure 2-3 shows the schematic

of the experimental setting.

Figure 2-3 Schematic of the chamber for high-k film deposition

2.2.3 RF Sputtering of Gate Electrode

RF sputtering was used for depositing gate metals W. The base pressure of

the sputtering chamber was maintained at 10-6 Pa during the substrate

transfer. Ar gas flow was set to 7sccm while holding the deposition chamber

pressure at of which was set to be 1.33Pa, the 150W RF current power used

to produce plasma.

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2.2.4 Photolithography and Metal Gate Etching

Positive photoresist layer of S1805 (for dry etching) was coated on the

samples by spin coating followed by baking samples at 110 oC for 5 minutes

on a hot plate. The photoresist layered samples were aligned and exposed

through e-beam patterned hard-mask with high-intensity ultraviolet (UV)

light at 405 nm wavelength. Exposed wafers were developed using the

specified developer. Post-baking was done at 130 °C for 5 minutes. Reactive

Ion Etching (RIE) was performed for gate electrode patterning with 50 sccm

SF6 gas at 30W. After the gate metal etching, photoresist layer on top of

metal gate was removed by O2-based ashing method inside the same RIE

system.

2.2.5 Thermal Annealing Process

Thermal annealing was used post gate electrode formation. The annealing

process is a must to minimize defects in dielectric film at the interface or

channel lattice recovery. In this study, low temperature (between

300°C–500°C) thermal treatments utilizing infrared lamp typed rapid

thermal annealing (RTA) system were used. The ambience in furnace was

vacuumed adequately prior to every annealing cycle and then forming gas

was provided with flow rate of 1.5 l/min while preserving the furnace

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pressure at atmospheric pressure. All annealed samples were removed from

the chamber under 100 °C.

2.2.6 Thermal Evaporation of Al Layer (back contact)

In this study, backside electrodes were formed with Al. Al was deposited by

thermal evaporation method in a vacuum chamber at a background pressure

up to 1.0x10-3 Pa. A tungsten (W) filament is used to hold highly pure Al

wires. Chamber pressure during evaporation was kept under 4x10-3 Pa. The

illustration in Figure 2-4 shows the experimental setting.

Figure 2-4 the schematic illustration of Al deposition

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2.3.1 Capacitance-Voltage (C-V) Characteristics

C-V characteristic measurements were performed with various frequencies

(1kHz ～1MHz) by precision LCR meter (HP 4284A, Agilent). The energy

band diagram of an MOS capacitor on a p-type substrate is shown in figure

2-5. The intrinsic energy level Ei or potential φ in the neutral part of device

is taken as the zero reference potential. The surface potential sφ is

measured from this reference level. The capacitance is defined as

dQCdV

= (2.1)

It is the change of charge due to a change of voltage and is most commonly

given in units of farad/units area. During capacitance measurements, a

small-signal ac voltage is applied to the device. The resulting charge

variation gives rise to the capacitance. Looking at an MOS capacitor from the

gate, C = dQG / dVG, where QG and VG are the gate charge and the gate

voltage. Since the total charge in the device must be zero, assuming no oxide

charge, QG = - (QS + Qit), where QS is the semiconductor charge, Qit the

interface charge. The gate voltage is partially dropped across the oxide and

partially across the semiconductor. This gives VG = VFB + Vox + φs , where

VFB is the flat band voltage, Vox the oxide voltage, and φs the surface

potential, allowing Eq. (2.1) to be rewritten as

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s n

ox s

dQ dQCdV dφ

+= −

+ (2.2)

The semiconductor charge density QS, consists of hole charge density Qp,

space-charge region bulk charge density Qb, and electron charge density Qn.

With QS =Qp + Qb + Qn, Eq.(2.2) becomes

1

ox s

s it p b n it

C dV ddQ dQ dQ dQ dQ dQ

φ= −+

+ + + +

(2.3)

Utilizing the general capacitance definition of Eq. (2.1), Eq. (2.3) becomes

( )11 1 )

ox p b n it

ox p b n it

ox p b n it

C C C C CC

C C C C CC C C C C

+ + += − =

+ + + +++ + +

(2.4)

The positive accumulation Qp dominates for negative gate voltages for

p-substrate

devices. For positive VG, the semiconductor charges are negative. The minus

sign in Eq. (2.3) cancels in either case. Eq. (2.4) is represented by the equivalent

circuit in figure 2-6 (a). For negative gate voltages, the surface is heavily

accumulated and Qp dominates. Cp is very high approaching a short circuit.

Hence, the four capacitances are shorted as shown by the heavy line in figure

2-6 (b) and the overall capacitance is Cox. For small positive gate voltages, the

surface is depleted and the space-charge region charge density, Qb = .qNAW,

dominates. Trapped interface charge capacitance also contributes. The total

capacitance is the combination of Cox in series with Cb in parallel with Cit as

shown in figure 2-6 (c). In weak inversion Cn begins to appear. For strong

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inversion, Cn dominates because Qn is very high. If Qn is able to follow the

applied ac voltage, the low-frequency equivalent circuit (figure 2-6 (d)) becomes

the oxide capacitance again. When the inversion charge is unable to follow the

ac voltage, the circuit in figure 2-6 (e) applies in inversion, with

0 /b s invC K Wε= where Winv is the inversion space-charge region width.

Figure 2-5 The energy band diagram of an MOS capacitor on a p-type substrate

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(b) Accumulation (b) Depletion

(c) Inversion Low Frequency

(d) Inversion High Frequency

(b) Accumulation (b) Depletion

(c) Inversion Low Frequency

(d) Inversion High Frequency

Figure 2.6 Capacitances of an MOS capacitor for various bias conditions.

2.3.2 Leakage Current Density-Voltage

(J-V ) characteristics

To measure the leakage current density, J-V characteristics are measured

using semiconductor-parameter analyzer (HP4156A, Hewlett-Packard Co.

Ltd.). The measurement started at 0 V and sweep towards accumulation

region until breakdown occurs.

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2.3.3 Interface Trap Density Extraction by

Conductance Method

The conductance method, proposed by Nicollian and Goetzberger in 1967, is

one of the most sensitive methods to determine Dit. Interface trap densities

of 109 cm-2eV-1 and lower can be measured. It is also the most complete

method, because it yields Dit in the depletion and weak inversion portion of

the band gap, the capture cross-sections for majority carriers, and

information about surface potential fluctuation. The technique is based on

measuring the equivalent parallel conductance Gp of an MOS capacitor as a

function of bias voltage and frequency. The conductance, representing the

loss mechanism due to interface trap capture and emission of carriers, is a

measure of the interface trap density. The simplified equivalent circuit of an

MOS capacitor appropriate for the conductance method is shown in Figure

2.7 (a).

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Figure. 2.7 Equivalent circuits for conductance measurement; (a) MOS capacitor with interface trap time constant τit = RitCit, (b) simplified circuit of (a), (c) measured circuit.

It consists of the oxide capacitance Cox, the semiconductor capacitance CS,

and the interface trao capacitance Cit. The capture-emission of carriers by

Dit is a lossy process, represented by the resistance Rit. It is convenient to

replace the circuit of Figure 2-7 (a) by that in Figure 2-7 (b), where Cp and

Gp are given by

2

2

1 ( )

1 ( )

itp s

it

p it it

it

CC C

G q D

ωτ

ωτω ωτ

= ++

=+

(2.5)

where Cit = q2Dit, 2 fω π= (f = measurement frequency) and it it it = R Cτ .

Dividing Gp by ω makes Eq. (2.7) symmetrical in itωτ . Eq. (2.6) and Eq.

(2.7) are for interface traps with a single energy level in the band gap.

Interface traps at the SiO2-Si interface, however, are continuously

25

distributed in energy throughout the Si band gap. Capture and emission

occurs primarily by trap located within a few kT/q above and below the

Fermi level, leading to a time constant dispersion and giving the normalized

conductance as

2ln 1 ( )2

p itit

it

G qD ωτω ωτ

⎡ ⎤= +⎣ ⎦ (2.6)

Equations (2.7) and (2.8) show that the conductance is easier to interpret

than the capacitance, because Eq. (2.7) does not require Cs. The conductance

is measured as a function of frequency and plotted as /pG ω versus . /pGω ω

has a maximum at 1/ itω τ= and at that maximum 2 /it pD G qω= . For Eq.

(2.8) we find ~ 2 / itω τ and 2.5 /it pD G qω= at the maximum. Hence one can

determine Dit from the maximum /pG ω and determine itτ from ω at the

peak conductance location on the ω -axis.

An approximate expression giving the interface trap density in terms of the

measured maximum conductance is

max

2.5 pit

GD

q ω⎛ ⎞

≈ ⎜ ⎟⎝ ⎠

(2.7)

Capacitance meters generally assume the device to consist of the parallel Cm-Gm combination in Figure 2-7(c). A circuit comparison of Figure 2-7 (b)

to Figure 2-7 (c) gives /pG ω in terms of the measured capacitance Cm, the

oxide capacitance, and the measured conductance Gm as 2

2 2 2( )p m ox

m ox m

G G CG C C

ωω ω

=+ −

(2.8)

assuming negligible series resistance. The conductance measurement must

26

be carried out over a wide frequency range. The portion of the band gap

probed by conductance measurements is typically from flat band to weak

inversion. The measurement frequency should be accurately determined and

the signal amplitude should be kept at around 50mV or less to prevent

harmonics of the signal frequency giving rise to spurious conductance. The

conductance depends only on the device area for a given Dit. However, a

capacitor with thin oxide has a high capacitance relative to the conductance,

especially for low Dit and the resolution of the capacitance meter is

dominates by the out-of-phase capacitive current component. Reducing Cox

by increasing the oxide thickness helps this measurement problem.

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Chapter 3. Electrical

Characteristics of In0.53Ga0.47As MOS Capacitors

3.1 Introduction


3.3 C-V Characteristics



28

3.1 Introduction

For over 30 years, there has been a significant effort on development of MOS

devices with various oxides on compound semiconductors. The electrical

behavior of these MOS devices intimately depends on details of processing

conditions (e.g., substrate type, surface preparation, dielectric deposition

technique, post-deposition anneal). It is the intent of this chapter to

introduce the measured results and attempted methods for improving and

achieving good electrical properties as well as discuss the nature and origin

of non-ideal electrical characteristics.


Figure 3-1 and 3-2 show Jg-Vg characteristics for two capacitors ;La2O3

(12nm thick) and PrOx (12nm thick) with 350 oC , 400 oC and 500 oC PMA in

F.G ambient for 5min. The leakage current pattern changes depending on

the type of oxide used for gate insulator, whereas 500 oC annealing shows

less leakage fro La-based oxide, this temperature shows excessive current

flow for Pr-based oxide. This could mean that the rate of As diffusion into the

oxide and diminishing its dielectric effect by creating defective vacancies and

energy states is more affected by the type of the oxide rather than the

temperature. This in turn would mean that choosing a proper passivation

method to prevent As diffusion could help improve the oxide stability at

29

desired annealing temperatures.

1.00E-08

1.00E-06

1.00E-04

1.00E-02

1.00E+00

1.00E+02

-2 -1.5 -1 -0.5 0

102

100

10-4

10-8

Voltage (V)

Leak

age

Cur

rent

Den

sity

[A/c

m2 ]

10-2

10-6

400oC-5min400oC-30min500oC-5min

@F.G

Figure 3-1 Jg-Vg plots of MOS capacitors with 12-nm PrOx layer at different annealing temperatures.

1.00E-08

1.00E-06

1.00E-04

1.00E-02

1.00E+00

1.00E+02

-2 -1.5 -1 -0.5 0

102

100

10-4

10-8

Voltage (V)

Leak

age

Cur

rent

Den

sity

[A/c

m2 ]

10-2

10-6

400oC-5min400oC-30min500oC-5min

@F.G

Figure 3-2 Jg-Vg plots of MOS capacitors with 12-nm La2O3 layer at different annealing

30

temperatures.

3.3 CV Characteristics

Capacitance-Voltage measurements are a staple in the traditional

characterization of MOS devices and materials. In analyzing III-V material

C-V curves there are three main issues that need to be considered. The first

is the amount of the hysteresis that results when the MOS capacitor is

biased well into accumulation and inversion. The second is the frequency

dispersion on accumulation capacitances, and the third is the controversial

issue of frequency dependant flat-band shift specifically noted in films

annealed at high temperatures.

-PrOx/InGaAs Capacitors

12nm of PrOx was deposited on p-type In0.53Ga0.47As substrates (doping level:

5.2×1012) using molecular beam evaporation. Substrates were cleaned by

concentrated HF solution for two minutes. Annealing was carried out in

350oC, 4000C and 500oC at 45 seconds, 5minutes. The results are shown in

figure 3-3. There is large hysteresis and frequency dispersion noted

irrespective of the annealing temperature and time.

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1kHz

10kHz

100kHz

1MHz

-1.5 -1.0 -0.5 0 0.5 1.0

0.5

1.0

1.5

2.0

2.5

3.5

3.0

-1.5 -1.0 -0.5 0 0.5 1.0

1kHz

10kHz

100kHz

1MHz

0

0.5

1.0

1.5

2.0

2.5

3.5

3.0

0

Voltage (V)

Cap

acita

nce

(µF/

cm2 )

Cap

acita

nce

(µF/

cm2 )

Voltage (V) (a) (b)

-1.5 -1.0 -0.5 0 0.5 1.0

0.5

1.0

1.5

2.0

2.5

3.5

3.0

-1.5 -1.0 -0.5 0 0.5 1.00

0.5

1.0

1.5

2.0

2.5

3.5

3.0

0

Voltage (V)

Cap

acita

nce

(µF/

cm2 )

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

1kHz

10kHz

100kHz

1MHz

(c) (d) Figure 3-3 CV characteristics for capacitor with PrOx: 12nm annealed at (a) 350 oC-45sec (b) 400 oC-45sec (c) 350 oC- 5min (d) 400 oC-5min

Also, although increasing the annealing time doesn’t result in any notable

difference, increasing the temperature causes bigger hysteresis hinting at

Arsenide (As) diffusion into the dielectric layer and increasing the number of

electrically active traps. Further analysis of this behavior will be discussed

in coming chapters. Furthermore, CV behavior of the samples annealed at

500oC could not be measured due to big leakage current. This in turn could

mean the worsening of the dielectric condition due to As atoms diffusion into

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the dielectric. Although the results of As diffusion and their reaction with Pr

atoms has not been directly researched, there are numerous reports in the

literature about the As diffusion effect into oxides.

-LaOx/InGaAs Capacitors

Capacitors with La2O3 as the gate dielectric were fabricated and measured.

La2O3 layer thickness deposited on two separate substrates was 12 nm and

8 nm. The annealing conditions were widely varied in order to find the most

favorable condition to achieve proper CV characteristics. Changing the gate

oxide subsequently results in chemical change of the layers after annealing

hence the same annealing conditions don’t necessarily result the same

behaviors.

Figure 3-4 shows the CV curves for the measured samples.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.3

0.5

0.8

1.0

1.3

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

Voltage (V) Voltage (V) Voltage (V)

500oC-5min@ F.G.

400oC-30min@ F.G.

400oC-5min@ F.G.

Cap

acita

nce

(µF/

cm2 )

(a) (b) (c) Figure 3-4 CV characteristics for capacitor with LaOx: 12nm annealed at (a) 400 oC-5min (b) 400 oC-30min (c) 500 oC- 5min

33


One of the common observed anomalous phenomena in the CV curves

presented in the previous sub-chapter and also III-V results published in the

literature is that of strong frequency dispersion of the CV characteristics in

maximum capacitance. This behavior has been observed on numerous III-V

semiconductors for over 30 years. One of the possible causes for frequency

dispersion in maximum capacitance is that of series resistance (contact,

substrate, cabling) altering the measured CV. However, there are several

reasons that series resistance cannot explain the dispersion behavior here.

The device capacitance (Cc), parallel conductance (Gc) and series resistance

(Rs) and the measured capacitance (Cm) has the following dependence with

measured frequency (ω )

Frequency dispersion due to series resistance depends on 2ω− which is not

observed in the measured results.

Interface traps are associated with frequency dispersion in MOS admittance.

The CV and also GV behavior of the III-V MOS encounter a Frequency

dependant flatband shift. To provide a more solid argument as to why series

resistance cannot by itself explain this particular frequency dispersion, and

the Fermi level pinning due to excess of interfacial states, the following

model is proposed.

2 2 2( 1) ( )

cm

c s c s

CCG R C Rω

=+ +

34

The ideal measured CV curves measured from a SiO2/Si MOS capacitor has

been imposed on an equivalent circuit with series resistance shown in figure

3-4. Equation below shows the relation between the measured Cm and true C

value effected by series resistance insertion.

2 2 2(1 / )ms m s

CCR R C Rω

=+ +

The Rm in the figure corresponds to the conductance part of the circuit and

has been replace by 1

2mm

RfC Dπ

=

where f is the measurement frequency and D is dissipation factor acquired

by measurement.

RmCm RC

Rs

Figure 3-4 Equivalent circuit model with series resistance inclusion

35

-1 -0.5 0 0.5 1 1.5 2

Cap

acita

nce

(µF/

cm2 )

1

2

3

4

5

Voltage (V)

Rs

Rs=100�

Rs=1M�

Frequency:100KHz

Rs increase with afactor of 10

Figure 3-5 Model capacitance with only series resistance effect on frequency dispersion

Figure 3-5 show the results, series resistance mainly results in a decrease in

accumulation capacitance with frequency and will never lead to a frequency

dependant flatband shift. This same effect can be seen on all frequencies

with higher frequencies suffering the biggest decrease in value. Figure 3-6

shows the effect of a constant series resistance value on different measured

frequencies.

36

10 100 1000 10000 100000 1000000

Max

Cap

acita

nce

(µF/

cm2 )

1

2

3

4

5

Frequency (V)

Frequency:100KHz

Rs constant at 1000�

Figure 3-6 Effect of series resistance on maximum measured capacitance at

different freuquencies

The classical theory describing interface traps with an equivalent circuit

including the effect of stretch out is sufficient to explain this CV behavior.

Introducing traps at a specific level within the bandgap, thus a combination

of donor/acceptor could explain this CV anomaly. A new model to simulate

the aforementioned effect on flatband shift according to the frequency is

under study.

37


Quantification of a large density of interface states using the conductance

technique becomes impossible when qDit becomes larger than Cox. Sensitivity

of the conductance to Dit is lost. The same is valid for the use of the CV

technique for if qDit»Cox it will not be possible to sweep the Fermi level

through the entire bandgap and to sense all traps without using excessive

voltages and breaking down the insulator. This problem also intensifies as

the accumulation capacitance varies greatly with the frequency of the

sweeping voltage and thus determining the true Cox value for extracting Dit

becomes crucial. Although this problem is under intensive research among

different III-V research groups there are some methods to bypass this

problem and try to acquire an almost accurate value of the interfacial states.

One of these methods is deriving a time constant from CV curves in

conjuncture with GV curves. The time constant from the CV corresponds to

the frequency at which the maximum G/ω is taken as a function of frequency

at a specific gate voltage at which the capacitance is halfway between the

minimum observed capacitance and the maximum observed capacitance.

Utilizing this approach is still under study and several considerations should

be made before same measurements can be applied for our samples.

The second and more straightforward method is to use the Cox value from the

capacitance measured at low frequency and use the conventional

38

conductance method, provided that the Dit is sufficiently low and weak Fermi

level pinning does not occur.

As discussed in the previous sub-section the measured capacitance value

from low frequency measurement is least effected by series resistance and

exhibits the maximum capacitance, hence the Capacitance of from the least

measurable frequency has been used to extract the Dit values from the

equivalent circuit shown in figure 3-7.

Figure 3-7 Equivalent circuit of a MOS capacitor with interfacial

state capacitance

The results are presented in table 3-7.

HF (NH4)2S HMDS HMDS(3) HF (NH4)2S HMDS HF (NH4)2S(NH4)2S (50oC HMDS350 5.60E+13 7.80E+13 4.90E+13 2.00E+13400 1.40E+13 3.60E+13 2.20E+13 8.50E+12450500 * 1.90E+13 2.70E+13 *350 5.50E+13 6.00E+13 4.20E+13 2.80E+13400 1.40E+13 3.00E+13 1.60E+13 2.70E+13 1.90E+14 1.70E+14 1.50E+14 3.70E+13 2.60E+13450 3.20E+13 2.10E+13 8.20E+13 1.70E+13500 * 1.90E+13 5.90E+13 * 3.50E+13 1.08E+13 2.10E+13350400 9.30E+13 1.90E+14 3.90E+13450500

LaOx (12nm) LaOx (8nm)

45sec

5min

30min

PrOx (12nm)

Table 3-7 summary of interface state densities for various measured samples.

39

The grey areas in this table correspond to the temperatures or times which

the experiment was not performed and the rest are the areas that due to

extremely distorted conductance peaks a reliable evaluation of interface

state densities was not possible.

One common trait that can be seen in all of the samples is that dipping the

samples in (NH4)2S i.e. S-passivation, reduces the interfacial state densities.

Also La-oxide in general shows lower level of Dit compared to Pr-oxide.

As mentioned before the subject of extracting reliable and accurate values of

Dit is still under research by groups both in academia and companies alike.

40

Chapter 4. Surface Analysis

4.1 Introduction


4.3 Oxide Formation and Dielectric Deposition

4.4 Interface Passivation Effects on Surface Chemistry

4.5 Electrical Behavior of Interface Passivated Capacitors

41

4.1 Introduction

Understanding the structural and chemical properties of III-V

semiconductor surfaces is necessary to achieve, control and improve

electrical characteristics of III-V based devices. As compound semiconductors

are not blessed like Si with natural passivating oxide layer extra effort and

research is necessary in order to effectively passivate the compound

semiconductors surface and optimize their electrical performance. In this

chapter we discuss the effects of various passivation methods in XPS

analysis and CV characteristics of the devices. The annealing and dielectric

effects with and without passivation are compared and discussed.


High quality InGaAs is grown on various III-V substrates such as InP using

epitaxial techniques. Since the Indium atom is larger than Gallium, the

maximum indium concentration that can be grown on InP substrate is

limited. Further more the surface of the substrate can change in native oxide

or metal concentration when exposed to different annealing conditions even

in vacuum. To investigate passivation effects on InGaAs Four different

substrates were prepared.

42

First all substrates were initially cleaned with concentrated HF solution

until a clean surface was achieved.

Then three substrates were separately passivated. One substrate was dipped

in 7% (NH4)2S solution for 30 minutes, one substrate was coated with HMDS,

and one substrate after HDMS coating was oxidized in ozone ambient and

another layer of HMDS was subsequently coated. This cycle was repeated for

three times.

The sample dipped in (NH4)2S solution are S passivated, the sample coated

with HMDS is Si passivated while the ozone exposed sample is passivated by

a mixture of Si and SiOx.

Then 12 nm of La2O3 was deposited on the substrates and annealed at

forming gas ambient for 5 minutes. All the samples were measured with

BL46XU at Super Photon ring 8GeV(SPring-8) with an incident angle of 85o.

W4f, In3d5/2, Ga 2p3/2, As2p3/2, Si 1s and C1s peaks were scanned. Figure 4-1

shows the result of the 4 substrates compared to one another at As peaks.

43

1318132013221324132613281330

A:HFA+SA+SiA+SiO

Nor

mal

ized

Inte

nsity

[a.u

.]

Binding Energy (eV)

HF+ HMDS (3-cycle)HF+ HMDS (1-cycle)HF+ (NH4)2SHF

As oxide

As2O3 : +3.6eVAs2O5 : +4eV

As2p3/2 500oC-5min@ F.G.

Figure 4-1 XPS core-level spectra showing that Ga-oxides do not have a strong dependence on the type of passivation used.

As the As 5+, As 3+ are the most stable and easily naturally grown oxides of

the substrate it is important to compare the effects of the passivation on

As-oxide states.

The comparisons from figure 4-1 show that ozone oxidation process during

cyclic coating of HMDS has caused the appearance of notable As-Oxide peak

at roughly 3 eV higher than the As 2p peak. Other passivation methods show

rather similar results, meaning that in concentrated HF solution is effective

in removing native As oxides.

44

11141116111811201122

A:HFA+SA+SiA+SiO

Nor

mal

ized

Inte

nsity

[a.u

.]

Binding Energy (eV)

HF+ HMDS (3-cycle)HF+ HMDS (1-cycle)HF+ (NH4)2SHF Ga 2p 500oC-5min

@ F.G.

Figure 4-2 XPS core-level spectra of Ga 2p peak in various substrates

Same behavior is seen in Ga 2p scan result, showing a bigger G-O related

peak at +2 eV energy regions of the spectra. It has been reported that

As-oxides although easily made, can be also easily removed with chemical or

thermal treatment, this makes the role of the most stable bound Ga native

oxides, GaOx , of importance.

The Ga XPS spectra, was analyzed by peak fitting process for three samples

and is shown in figure 4-3. HF treated, passivated with (NH4)2S solution and

passivated by HMDS solution. As it can be seen from the graphs both

S-passivation and Si-passivation show notable decrease in the formation of

GaOx, also the appearance of a small peak at an energy lower than the Ga 2p

peak could be the result of Ga-La bonds as La atoms have smaller

electronegativity compared to Ga atoms, Ga atoms get negatively charged,

45

these negatively charge atoms would repulse the electron rays hitting the

core levels and therefore increase the kinetic energy of the reflected electrons.

This could explain why the peaks appear at a lower energy level than the

metal peak.

111411151116111711181119112011141115111611171118111911201114111511161117111811191120

500oC-5min@ F.G.

500oC-5min@ F.G.

500oC-5min@ F.G.

Ga-OGa-La

HF treatment S- passivated Si- passivated

Ga-OGa-O

Figure 4-3 XPS core-level spectra showing that Ga-oxides are inhibited by using passivation, Ga-La bond formation also shows less appearance.

Although it has been reported in the literature that detecting In-oxides using

XPS is complicated, XPS analysis results in our show significant In-oxide

peaks by using passivation solutions. The results are shown in figure 4-4.

46

440442444446448450

A:HFA+SA+SiA+SiO

Nor

mal

ized

Inte

nsity

[a.u

.]

Binding Energy (eV)

HF+ HMDS (3-cycle)HF+ HMDS (1-cycle)HF+ (NH4)2SHF In 3d 500oC-5min

@ F.G.

Figure 4-4 XPS core-level spectra showing that In-oxides are notably appeared by using passivation methods.

As it can be seen from the XPS spectra, passivation has the largest impact on

the formation of In oxides. The reason as to why passivation makes it easier

for normally instable In oxides to appear is still under study.

Peak fitting results for the sample passivated with HMDS shows strong

appearance of InOx peaks.

47

442443444445446447448

Nor

mal

ized

Inte

nsity

[a.u

.]

Binding Energy (eV)

500oC-5min@ F.G.

Si- passivatedIn 3d

InOx

Figure 4-5 XPS core-level spectra showing that In-oxides are siginificantly formed due to the use of HMDS as passivation method.

48

4.3 Electrical Behavior of

Interface Passivated Capacitors

CV characteristics of the samples with and without passivation were

measured.

-PrOx-InGaAs samples

Different annealing temperatures and times were tried out. The table

summarizes the annealing conditions with dark- green parts representing

good CV characteristics and red cells representing poor CV characteristics.

350 400 50045sec300sec45sec300sec45sec300sec45sec300sec

A+HMDS(1)

A+HMDS(3)

A: HCL+HF

A+(NH4)2S

The results for annealing at 400oC for 5 minutes at forming gas

ambient are shown in figure 4-6. As it can be seen from the graphs, using

S-passivation shows the biggest effect on the hysteresis of the CV curves,

however frequency dispersion of the samples are practically on effected by

49

employing passivation methods.

1kHz

10kHz

100kHz

1MHz

-1.5 -1.0 -0.5 0 0.5 1.0 -1.5 -1.0 -0.5 0 0.5 1.0-1.5 -1.0 -0.5 0 0.5 1.0

HF+ (NH4)2SHF HF+ HMDS

400oC-5min@ F.G.

400oC-5min@ F.G.

400oC-5min@ F.G.

0.5

1.0

1.5

2.0

2.5

3.5

3.0

0

Cap

acita

nce

(µF/

cm2 )


(a) (b) (c)

Figure 4-6 CV characteristics for capacitor with PrOx: 12nm annealed at 400

oC-5min at F.G. (a) only HF treatment (b) HF treatment and (NH4)2S dip (c)

HF treatment and HMDS coating

-LaOx(12-nm)/InGaAs samples

Samples deposited with 12-nm of La2O3 and annealed at 500oC forming gas

ambient for 5 minutes, showed remarkably improved CV characteristics with

noticeable reduction of frequency dispersion at the accumulation region and

very small hysteresis, although the minority carrier contribution to the

capacitance at inversion regions was still undeniable. The minority carrier

distributed ‘humps’ have been reported by other research groups as well.

Sensitivity of the amount of InGaAs intrinsic carriers to temperatures calls

50

for low-temperature evaluation of the samples which could reveal new and

better insight to the contribution of minority carriers to the capacitance of

the MOS at various sweeping voltages.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

400oC-5min@ F.G.

400oC-5min@ F.G.

400oC-5min@ F.G.



Figure 4-7 CV characteristics for capacitor with LaOx: 12nm annealed at 400



51

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

1kHz10kHz100kHz1MHz

500oC-5min@ F.G.

500oC-5min@ F.G.

500oC-5min@ F.G.






-LaOx(8-nm)/InGaAs samples

Samples prepared by the passivation methods were deposited by 8-nm

La2O3 and were annealed at different conditions. The annealing time at

these samples made significant difference and at temperatures higher than

400oC due to high leakage current a correct evaluation of the capacitance

properties was rendered impossible. The results for the samples annealed at

400oC are shown in the figure 4-9.

The extreme dependence of the capacitance and leakage current to

temperature compared to the samples with 12-nm La-oxide could be due to

the amount of oxide to which the As is diffused into. Samples with thinner

52

La-oxide layer and annealed at higher temperatures could be fully

contaminated by metal As diffusion.

0.0

0.3

0.5

0.8

1.0

1.3

1.51kHz10kHz100kHz1MHz

0.0

0.3

0.5

0.8

1.0

1.3


0.0

0.3

0.5

0.8

1.0

1.3


400oC-5min@ F.G.

400oC-5min@ F.G.

400oC-5min@ F.G.


Voltage (V) Voltage (V) Voltage (V)-1.5 -1.0 -0.5 0 0.5 1.0 -1.5 -1.0 -0.5 0 0.5 1.0 -1.5 -1.0 -0.5 0 0.5 1.0




53

Chapter 5. Conclusion

5.1 Conclusion of This Study



54

5.1 Conclusion of This Study In this work, we studied the electrical characteristics of InGaAs MOS device

with high-k gate dielectrics. RE-oxide capacitors revealed large leakage

current however La-oxide showed promising properties for reducing

frequency dispersion effect. Using La based oxides in conjuncture surface

passivation methods which reduce the hysteresis of the CV curves can

become a formidable candidate for future employment in III-V MOSFETs.

Arsenide diffusion showed a notable sensitivity to annealing temperatures

which should be fully considered in order to reduce the leakage current and

thermal stability of the high-k dielectrics when deposited on InGaAs

substrates. Also Indium native oxides shows strong dependence on the

passivation material, this finding can be used to deeper analysis of the

surface chemistry of III-V and its interaction with La-oxide.


Three of the most important technological hurdles facing III-V MOSFET

development are: high quality, low EOT gate dielectrics, damage-free low

resistivity junctions, and hetro-integration on a VLSI compatible silicon

substrate. For any technology, improvement of one parameter results in

degradation of other parameters, therefore choice of design and technology is

a subject of trade offs and optimization. Superior electron transport

55

properties are a major reason why III-V are considered for advanced CMOS

circuits. However, placing the semiconductor channel in close proximity to

high-k gate oxide reduces mobility significantly in a similar way as in Si

channel due to interface charges, roughness and soft phonon scattering.

These are some of the main problems that still need much work and research

to overcome.


In this study we attempted to achieve proper CV characteristics using high-k

gate dielectrics and various passivation methods. Frequency dispersion is a

hurdle that must be understood and overcome in order to successfully

fabricate high performance MOSFETs, analyzing electrical effects of the

MOS capacitors such as active traps, border traps, or interfacial traps

becomes unclear. Understanding the true CV values of the InGaAs

substrates and implementing more accurate equivalent circuits is of outmost

importance. This should be the main area of the focus for the next step of this

study, parallel work to search for other passivation methods, surface

chemistry control, junction formation and ultimately fully functioning field

effect transistors are the problems that should be and will be dealt with in

the future.

56

References [1.1] International Technology Roadmap for Semiconductor (ITRS), 2008 up data [1.2] D.-H. Kim, J. A. del Alamo, J.-H. Lee, and K.-S. Seo, Tech. Dig. - Int. Electron Devices Meet. 2005, 767. [1.3] P. D. Ye, G. D. Wilk, B. Yang, J. Kwo, H.-J. L. Gossmann, M. Hong, K. K. Ng, and J. Bude, Appl. Phys. Lett. 84, 434 _2004_. [1.4] M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit, and R. Chau, Tech. Dig. - Int. Electron Devices Meet. 2007, 625. [1.5]. M. W. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, Science 283, 1897 (1999). [1.6]. F. Ren, M. W. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, Y. K. Chen, and A. Y. Cho, Tech. Dig. IEDM. p. (1996) [1.7]. J. K. Yang, M. G. Kang, and H. H. Park, J. Appl. Phys. 96, 4811 (2004). [1.8]. P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H.-J. L. Gossmann, M. Frei, S. N. G. Chu, J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, IEEE Electron Device Lett. 24, 209 (2003). [1.9]. Y. Xuan, P. D. Ye, H. C. Lin, and G. D. Wilk, Appl. Phys. Lett. 89, 132103 (2006). [1.10]. W. E. Spicer, Z. Liliental-Weber, E. Weber, N. Newmann, T. Kendelewicz, R. Cao, C. McCants, P. Mahowald, K. Miyano, and I. Lindau, J. Vac. Sci. Technol. B 6, 1245 (1988). [1.11]. Goel.N et al., Appl. Phys. Lett., 89, 163517 (2006) [2.1] Dieter K. Schroder, Semiconductor Material and Device Characterization 3rd Edition, John Wiley & Sons, Inc., 2005. [2.2] S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices 3rd Edition, John Wiley & Sons, Inc., 2007.

57

Acknowledgement The author would like to thank his supervisor at Tokyo Institute of Technology, Professor Hiroshi Iwai, for his excellent guidance and continuous encouragement, as well as financial support of the project. The author also benefited greatly from suggestions and discussions with Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Akira Nishiyama, Prof. Nobuyuki Sugii, Prof. Kazuo Tsutsui of Tokyo Institute of Technology for reviewing the thesis and for valuable advice. The author would like to thank Associate Professor Kazuo Tsutsui and Nobuyuki Sugii for their valuable advices and discussions, Professor Takeo Hattori for his valuable advice on XPS and constant support and show of interest in this study. Special thanks to Dr. Kakushima for kind guidance and discussion at literally every step of the study. The author would like to thank all members of Professor Iwai’s Laboratory, for the kind friendship and help and advice at experimental procedures. The author would like to express sincere gratitude to laboratory secretaries, Ms. M. Karakawa, Ms. A. Matsumoto. This research was supported by Strategic International Cooperative Program, Japan Science and Technology Agency (JST).

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