Preliminary LumiCAL FEE Specification Presented by Alexander Solin NC PHEP [email protected] FCAL...
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Transcript of Preliminary LumiCAL FEE Specification Presented by Alexander Solin NC PHEP [email protected] FCAL...
Preliminary LumiCAL FEE Specification
Presented by Alexander Solin
FCAL collaboration meeting, February 12-13, 2006,Krakow (INP PAS), Poland
February 12-13, 2006, Krakow A.Solin
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Contents
Preliminary LumiCAL FEE Specification ASICs for FCAL detectors prototypes (main parameters
measurement setup, bench and beam tests)
February 12-13, 2006, Krakow A.Solin
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Preliminary LumiCAL FEE Specification
February 12-13, 2006, Krakow A.Solin
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Estimation of the pad Si-sensor capacitancies
80 mm 280 mm
15 deg
15 deg
280 mm80 mm
10 pads
22 pads
B
B
295pF/1413 sq. mm
42pF/201 sq. mm
98pF/471 sq. mm
137pF/655 sq. mm
Cmax/Cmin=295pF/42pF=7
Rough segmentation parts
Fine segmentation part
February 12-13, 2006, Krakow A.Solin
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Estimation of the strip Si-sensor capacitancies
30 deg
80 mm 280 mm
3 deg
80 mm 280 mm
64concentric
strips
120 radial strips
B
B
28pF/133 sq.mm
395pF/1885 sq. mm
For the bonded concentric strips: Cmin=168 pF, Cmax=571 pF
95pF/455 sq.mm
Cmax/Cmin=395pF/28pF=14
The large difference of capacitance is problem for apreamplifier noise optimization.
February 12-13, 2006, Krakow A.Solin
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Estimation of the maximum Si-sensor charge collection
(1-1000)MIP channel signal rangefrom B.Pawlik’s talk
Cfb=3.2pF
2VCSP
1000MIP
February 12-13, 2006, Krakow A.Solin
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LumiCal Si-sensor parameters
Material Si
Think, 500
si 11.8
Depletion voltage, V 155
Collection charge time, ns 28
MIP,e 40000
Capacitance range calculation(look previous pictures )
Minimum value Maximum value
Pad option 42pF 295pF
Strip option isolated concentric sectors 28pF 395pF
bonded concentric strips 168pF 571pF
February 12-13, 2006, Krakow A.Solin
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LumiCAL ASIC requirementsSignal to Noise Ratio (SNR) 5
Maximum ENC, e 8000
Maximum signal, MIP 1000
Dynamic range, bit 12-13
Shaping time, ns 70
Amplitude output, V 2
Gain, mV/fC 0.31
Channel structure of the first prototype Preamplifier - Shaper
Number of channels per chip (rough estimation)
Detector mounting surface area, cm2 3956 (for 22.5 cm detector length)
Chip mounting surface area, cm2 4
Total number of chips 989
Number of channels per chip
Pad option 12
Strip option 14 (4 in case of bonded concentric strips)
Number of channels per chip fixed by tile size 22 (cheap package), 44
February 12-13, 2006, Krakow A.Solin
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ASIC technologies
Minsk 1.5µ design rules Bi-JFET0.8µ design rules CMOS
0.6µ design rules Bi-CMOS
Leading European and Asiatic FABs up to deep submicron design rules (if it is reasonable)
Next four pictures can help to estimate noises of frond end electronics. Calculations are done for Bi-JFET technology (see picture).
Same calculations can be done for other technologies. Preamplifier noises will be similar to the presented calculations.
February 12-13, 2006, Krakow A.Solin
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Capacitance of Si-sensor vs its area
572pF
28pF
February 12-13, 2006, Krakow A.Solin
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ENC vs preamplifier power consumption
8000e
February 12-13, 2006, Krakow A.Solin
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ENC vs shaping time
8000e
February 12-13, 2006, Krakow A.Solin
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ENC vs Si-sensor Capacitance
572pF
February 12-13, 2006, Krakow A.Solin
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ASICs for FCAL detectors prototypes(main parameters measurement setup, bench and beam tests)
February 12-13, 2006, Krakow A.Solin
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Tetrode-BT, Tetrode-JFET ASICs
1996 year, CMS ECAL
Two designs CSP were made in Minsk NC PHEP with slightly different circuits for amplifying of signals from Hamamtsu R2149 vacuum phototetrode:“TETRODE-BT” with bipolar input transistor;“TETRODE-JFET” with p-JFET input transistor.
February 12-13, 2006, Krakow A.Solin
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Design requirements to Tetrode CSPs
Hamamtsu R2149 parameters:
CSP requirements:
Ca 15pF
Anode dark current 0.1 nA
Typical gain (HV= -900V, B= 0 T) 30
Quantum eff. at 500 nm 10%
ENC, e <1000
Dynamic range, bit 13
Output signal width (base-to-base), ns 100ns
February 12-13, 2006, Krakow A.Solin
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CSP based on Tetrode JFETENC=320e+18e/pF, Tp=800ns
ENC vs Vsupplies at Cd=0Tetrode JFET based CSP
0
100
200
300
400
500
600
5 6 7 8 9 10
Vsupply, V
EN
C, e
ENC vs Cd at Vsupplies=+/-8VTetrode JFET based CSP
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0 20 40 60 80 100
Cd, pF
EN
C, e
February 12-13, 2006, Krakow A.Solin
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AS01PDA, AS01T ASICs
2002 year, TESLA THCAL
Next AS01PDA ASIC were designed and manufactured in Minsk NC PHEP for amplifying of signals from photodetectors.The AS01PDA ASIC is a development of the “Tetrode BT” design line. It additionally contains a shaper and shaper gain control stage.
February 12-13, 2006, Krakow A.Solin
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AS01PDA main parameters
Number of channels 1
Circuit structure Preamplifier + Shaper +
50 Ohm Driver
Additional property Shaper Gain Control
Shaper peaking time 90ns
Max. Gain 9mV/fC
ENC, e 1000+14.1e/pF
Shaper output +/-1.5V
Power consumption 18mW
Package SOP16
February 12-13, 2006, Krakow A.Solin
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AS01PDA block diagram
Preamplifier- Shaper- 50 Ohm Driver
Reference level (Vref)
Gain control(Gain_ctrl)
Signal input(In)
Ct 0.2pF
Test input(In_t)
Positive output (Op)
Negativeoutput(On)
Bias block
February 12-13, 2006, Krakow A.Solin
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AS01PDA tests October, 2002 Output signals were digitalized with theTDS3032 scope.
AS01PDA ASIC response at Vcc=+6VCtest=1.2pF, Vin=45mV, Gain=3.5mV/fC
-0,25-0,2
-0,15-0,1
-0,050
0,05
-1,00E-06 -5,00E-07 0,00E+00 5,00E-07 1,00E-06 1,50E-06
Time, s
Vo
ut,
V Cd=0
Cd=68pF
February 12-13, 2006, Krakow A.Solin
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AS01PDA noise curves February, 2006 Noise is measured with the Infiniium 54830B scope.
ENC vs Cd and Vcc
ENC = 14,123e/pF + 1000e
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
0 50 100 150 200 250 300
Cd, pF
EN
C, e
5V
6V
7V
8V
9V
Trend line
February 12-13, 2006, Krakow A.Solin
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ASIC for large capacitance detectorsAS01T is optimazed for using with large capacitance detectors. It has the same structure as AS01PDA. The package is the same too. Both chips (AS01T and AS01PDA) are placed on the same wafer
and are manufactured in one process.
ENC vc CdAS01T
ENC = 6,6343e/pF + 2159,1e
0
2000
4000
6000
8000
10000
12000
0 200 400 600 800 1000 1200
Cd, pF
EN
C, e
6V
9V
Trend line
ENC of AS01PDA, AS01T ASICs
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
0 200 400 600 800 1000 1200
Cd, pF
ENC,
e 6V_AS01PDA
6V_AS01T
February 12-13, 2006, Krakow A.Solin
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Conclusion
The next steps of development of FEE for FCAL
Making of readout electronics for immediate beam tests (Tetrode, AS01 ASICs)
Qualification of LumiCAL ASIC specification and design of new prototype of 22 channel preamplifier-shaper ASIC for amplifying of Si-detector signals.
Creation of multichannel readout electronics for larger FCAL prototypes.