Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

Martijn Snoeij1,*, Albert Theuwissen1,2, Johan Huijsing1

and Kofi Makinwa1

1 Delft University of Technology, The Netherlands2 Harvest Imaging, Belgium* Now with Texas Instruments, Germany

4th Fraunhofer IMS Workshop on CMOS ImagingMay 6th, 2008

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Outline

• Why column-level A/D conversion?

• Application of existing ADC architectures• Development of new ‘custom’ Architectures:

– Multiple-Ramp Single-Slope (MRSS) ADC– Multiple-Ramp Multiple-Slope (MRMS) ADC

• Conclusions

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Why A/D Conversion in CMOS Imagers?

• A key advantage of CMOS imagers is co-integration of analog & digital signal processing ⇒ ‘Camera-on-a-chip’

• On-chip A/D converter essential! Properties:– Complex analog function– Important factor in overall quality– Significant fraction of overall power consumption

• System-level of ADC is of key importance:– Place of ADC within signal processing chain– ADC architecture

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Chip-Level ADC approach

+ Single ADC: Robust, simple solution

+ ADC separate from imager: ‘standard cell’ can be used

− Single ADC: bottleneck for high readout speeds

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Column-Level ADC Approach

+ ≈1000 ADCs working in parallel⇒ allows for higher speeds

+ Shorter analog signal path

− Ensuring uniformity between ADCs design problem

− More chip area

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Pixel-Level ADC Approach

+ ≈1 million ADCs per chip ⇒extremely high frameratespossible

+ Very short analog signal path+ Digital processing within array

possible

− Ensuring uniformity between ADCs design problem

− Very large chip area ⇒impractical for most applications

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Chip-level ADC (1/chip)

Column-level ADC (≈1k/chip)

Pixel-level ADC (≈1M/chip)

• Power efficiency rather than absolute speed limitations often decisive

• Number of pixels strongly increasing in mainstream imagers ⇒Trend from chip-level towards column-level ADC

Approaches for CMOS Imager A/D Conversion

TotalADC

speed

Complexity /Chip area

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Architectures for Column ADCs

• What are column ADC requirements:– Small circuit– Uniformity between columns– Good power/speed ratio

• Existing ADC Architectures used in column ADCs:– Cyclic/algorithmic [1-2]– Successive approximation [3-4]– Single-Slope [5-8]

• Custom ADC Architectures for column ADCs:– Multiple-Ramp Single-Slope (MRSS)– Multiple-Ramp Multiple-Slope (MRMS)

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Single-Slope ADC Architecture

NB ramp generator is implemented centrally ⇒comparator only analog part in column

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Single-Slope Architecture Pros & Cons

Advantages:• Simple column circuit• Easy to correct for non-

uniformities

Disadvantage:• Conversion time takes 2n

clocks for n-bit ⇒ poor power/speed ratio

• Long conversion time can force designer to reduce resolution to increase speed [8]

• Existing, faster solutions are the Successive Approximation (SAR) or Cyclic ADC

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SAR ADC Architecture

DAC output depends on input signal ⇒Each column needs its own DAC!

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Cyclic (Algorithmic) ADC Architecture

Every circuit block function depends on input ⇒Apart from Vref, no central circuitry possible

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SAR/Cyclic Architectures Pros & Cons

Advantages:• Conversion takes n

clocks for n-bit

Disadvantages:• Column circuit too

complex• Uniformity between

columns major issue

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Problems of Conventional ADC Architectures

• Single-slope very suited for use in parallel system (central ramp generator), but too slow

• SAR good improvement in conventional ADC applications, but difficult in parallel system

• Some ‘compromise’ between single-slope and SAR would be good

• Idea for new architecture found at LinköpingUniversity [9] and Delft University [10][11]

• First prototype presented Feb. 2007 [10]

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SAR & Single-Slope Common Principle

• Comparator basis of both architectures

• Reference signal fed to comparator different

• SAR requires feedback from comparator to DAC

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SAR & Single-Slope Common Principle

• Comparator basis of both architectures

• Reference signal fed to comparator different

• SAR requires feedback from comparator to DAC

Approach:• comparator only analog in

column ⇒ no feedback• Multiple reference outputs

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Multiple-Ramp Single-Slope (MRSS) Concept

Input signal is compared to ramp voltage

To increase speed, use multiple ramps concurrently

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MRSS Concept: Coarse & Fine Phase

2-step Conversion:1. Coarse phase:

Determine which ramp should be connected to comparator

2. Fine phase:Multiple ramps run concurrently

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MRSS Concept: Overlap in Fine Phase

Small error in coarse phase can cause comparator being connected to wrong ramp ⇒

Some overlap between ramps required to prevent dead-bands

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MRSS ADC Block Diagram

Number of ramps is trade-off between ramp generator power and ADC speed ⇒

First prototype uses 8 ramps

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MRSS Column Circuit

Compared to single-slope, only additional circuitry are switches + some logic ⇒Small column circuit

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MRSS ADC Block Diagram

Column-level additions for MRSS are simple

⇒

Increased design complexity mainly in ramp generator

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Ramp Generator Requirements

Main Requirements:1. All ramps need a well-

defined offset2. All ramps should have

same slope

⇒

Ramp generator implemented as 8 matched DACs

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Multiple Ramp Generator Principle

Generator consists of:• 1 coarse ladder• 8 fine ladders

Common coarseladder ensures matching between ramps

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Chip Micrograph

Specifications:• 400 x 330 pixels• 7.4µm pixel pitch • 20MHz system clock• 0.25µm 1P3M process• 2.5V/3.3V supply• Die size: 5mm x 5mm

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Image Captured in Single-Slope Mode

• Single-slope image for comparison

• 10-bit resolution• A/D conversion time

=1060clks @ 20MHz=53µs ⇒50 frames / second

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Image Captured in MRSS Mode

• 10-bit resolution• A/D conversion time

=320clks @ 20MHz=16µs ⇒142 frames / second

Speed increase:• 3.3x conversion time• 2.8x frame rate

• 16% power increase

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MRSS Architecture Pros & Cons

Advantages:• In theory, conversion

takes ≈ 2p + 2q clocks for n-bit, n = p + qin practice some more clocks needed

• Simple column circuit• Easy to correct for non-

uniformities

Disadvantages:• Ramp generator more

complex• Slight increase in digital

overhead

• More details can be found in [10] & [11]

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Extending the MRSS ADC: MRMS ADC

• All imagers exhibit photon shot noise, which has unique property of increasing with signal

• In principle, any ADC can exploit this property to reduce power and/or increase speed

• In practice, few ADC architectures are suited for this – some implementations shown in single-slope ADCs [12][13]

• The MRSS concept is very suited ⇒Multiple-Ramp Multiple-Slope (MRMS) ADC

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Exploiting Photon Shot Noise in ADC

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Exploiting photon shot noise in ADC

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Reducing ADC Performance

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Reducing the Number of Quantization Steps

• By increasing quantization step, total number of steps is reduced:

51087254169Number of steps:

Total:42 1Step size (LSBs):

• Table shows number of steps needed for 10b resolution ⇒ 2x smaller then normal quantization

• If effectively implemented, this means 2x less power or more speed, without visible image quality loss

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A Multiple-Ramp Multiple-Slope ADC

• In an MRSS ADC, quantization step defined by increase of ramp voltage per clock

• Photon shot noise exploitation by changing ramp slopes:Multiple-Ramp Multiple-Slope (MRMS) ADC

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MRMS Measurement results

• 10-bit resolution• A/D conversion time

=256clks @ 20MHz=12.8µs frame rate not increased due to digital limitation

Speed increase:• 25% compared to MRSS• 4.1x compared to single-

slope

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MRMS Architecture Pros & Cons

Advantages:• Further reduction in

conversion time compared to MRSS

• Simple Column circuit• Easy to correct for non-

uniformities

Disadvantages:• Ramp generator more

complex compared to MRSS

• Perceptual impact not fully studied (digital still vsvideo)

• Slight increase in digital overhead

• More details can be found in [11]

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Summary

• Column-Level ADC provides good trade-off between power-efficiency and complexity for high resolution CMOS image sensors

• Existing ADC architectures have either too complex column circuits or are too slow

• MRSS architecture significantly increases speed and power efficiency of column-level ADC

• Further increase in speed & power efficiency by exploiting photon shot noise with MRMS ADC

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References

[1] S. Decker, R.D. McGrath, K. Brehmer, and C.G. Sodini, “A 256 x 256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output”, IEEE Journal of Solid-State Circuits, vol 33, no. 12, pp. 2081-2091, Dec. 1996

[2] M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, “A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters”, IEEE Journal of Solid-State circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005

[3] Z.Zhou, B. Pain, and E.R. Fossum, “CMOS active pixel sensor with on-chip successive approximation analog-to-digital converter”, IEEE Transactions on Electron Devices, vol. 44, no. 10, pp. 1759-1763, Oct. 1997

[4] B. Mansoorian, H. Yee, S. Huang and E. Fossum, “A 250mW 60 frames/s 1280 x 720 pixel 9b CMOS digital image sensor”, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 312-313, Feb. 1999

[5] W. Yang, O-B. Kwon, J-I. Lee, G-T. Hwang and S-J. Lee, “An integrated 800 x 600 CMOS imaging system”, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 304-305, Feb. 1999

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References

[6] T. Sugiki et al. , “A 60 mW 10b CMOS image sensor with column-to-column FPN reduction”, IEEE International Solid-State Circuits Conference, vol. XLIII, pp. 108-109, Feb. 2000

[7] K. Findlater et al. , “SXGA pinned photodiode CMOS image sensor in 0.35ìm technology”, IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 218-219, February 2003

[8] Y. Nitta et al. , “High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor”, IEEE International Solid-State Circuits Conference, vol. XLIX, pp. 500-501, Feb. 2006

[9] L. Lindgren, “A new simultaneous multislope ADC for array implementations”, IEEE Trans. On Circuits & Systems II¸ vol. 53, pp. 921-925, September 2006

[10] M.F. Snoeij, P. Donegan, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing , “A CMOS image sensor with a column-level multiple-ramp single-slope ADC”, ISSCC Dig. Tech. Papers¸ pp. 506-507, February 2007

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References

[11] M.F.Snoeij, A.J.P. Theuwissen, K.A.A. Makinwa, and J.H. Huijsing, “Multiple-Ramp Column-Parallel ADC Architectures for CMOS Images Sensors”, IEEE Journal of Solid-State Circuits, Vol. 42, No. 12, pp. 2968-2977, December 2007

[12] O-B. Kwon et al. , “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640x480 CMOS Imaging System”, IEEE Int. Conference on VLSI and CAD, pp. 335-338, October 1999

[13] T. Otaka et al., “12-Bit Column-Parallel ADC with Accelerated Ramp”, IEEE Workshop on CCDs and Advanced Image sensors 2005, pp. 173-176, Karuizawa, Japan, June 2005.