ADCs for CMOS Image Sensors (an overview) · ADCs for CMOS Image Sensors (an overview) Deyan Levski...
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ADCs for CMOS Image Sensors (an overview) Deyan Levski — Column-parallel ADC Readout Architectures for CMOS Image Sensors — 1/35
Transcript of ADCs for CMOS Image Sensors (an overview) · ADCs for CMOS Image Sensors (an overview) Deyan Levski...
ADCs for CMOS Image Sensors
(an overview)
Deyan Levski — Column-parallel ADC Readout Architectures for CMOS Image Sensors — 1/35
Topics
Deyan Levski — Column-parallel ADC Readout Architectures for CMOS Image Sensors — 2/35
● Requirements on ADCs for imaging (LDR visible light)
● Common architectures
— Single-Slope (Ramp) → TODAY— Cyclic— SAR— Delta-Sigma
● Some issues with Ramp ADCs and their solutions
But not really in that order…
Requirements on ADCs for imaging
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● Resolution: 10 — 14-bits- driven by pixel temporal noise in low-light conditions
● A/D output noise- linked with pixel temporal noise- ideally < 1 LSB RMS
source: Arnaud Darmont, Aphesa
Resolution — Output Noise
Deyan Levski — Column-parallel ADC Readout Architectures for CMOS Image Sensors — 4/35
source: Photon Transfer, James Janesick, SPIE Press, 2007Dark + ADC noise
Speed
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● Speed- application dependent: ~1 µs to 100s µs
● GS High-Speed/Res ● Multi-Line HDR ● HCG low T-int imager for low-light microscopy● Pill camera
- single: analog charge shifting is complex- column-parallel: shares similarity with time-interleaved ADCs- group-parallel / 3D stacked: (new field)
source: Keysight Labs
Single vs Column vs Group-Parallel
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● Speed- group-parallel, offers higher speed-power efficiency
(not in all architectures)
source: Forza Silicon
● 163 Mpixel, 20 fps, 12-bit
● 39 ADCs for 4056 cols= 104 cols per ADC
● Inherent “zero” CFPN● Group-to-group offset
even more visible: challenge
Group-Parallel Offset (GFPN/CFPN)
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● Group-parallel offset issues- group-group ADCs use different references
source: Forza Silicon
(contrast enhanced)
Electrical / IO
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● Input- single ended, unless PGA drives differentially- range between Vdsat(ipix) – Vth(sf) : 0.5 – 2.8 (depends)
● Output- shadow SRAM- serial output- high-speed LVDS (sLVDS) output interface - ~100s Mbps to 1 Gbps - multiple output taps (reconfig) - various output interfaces: MIPI, DVP, LVDS, custom
● Area / form factor / power
- narrow/high, e.g. 2.4µ x 800µ →crosstalk
- CIS FSI → limited metal routing - power: typ: 10 – 200 µW / column
Linearity and Offset
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● Integral nonlinearity
- can tolerate some amount — human eye- INL gain errors may confuse vision algorithms(auto exposure / HCG-LCG combine in HDR cameras)(metering mode confused – constant switch b/w 1x, 2x, 4x etc...)
● Differential nonlinearity — BAD- very easy to see in image histogram- reduces ENOB of converter- non-uniform quantization noise
● Offset - column FPN easily detectable by the human eye <1% - DCDS helps in CFPN
Row (H) Noise
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● Row noise: - normally caused by:
● poor PSRR of array/pixel ● sampling and/or row driver pulse non-uniformity ● aliasing with sys. clocks
- but can also be ADC-induced:● settling issues in S/H
- PSRR and GRR very important: (noise on VDD / GND not white!!!)
- internal (high-bandwidth) LDOs may help but cost power / heat issues
- other analog tricks: cap bias coupling, star ground, supply separation etc...
Common Architectures
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● Single-slope (Ramp) ADC
● Successive Approximation Register (SAR) ADC
● Cyclic ADC
● Dual/Multi-stage Cyclic ADC
● Delta Sigma (max 3-rd order)
● Hybrid coarse-fine
● Hybrid residual e.g. Delta-Sigma—Cyclic; SAR—Ramp etc…
● PTC-Inspired
● (Pipelined and Folding architectures: not practical)
Column-ParallelSingle-Slope (Ramp) ADCs
Not covering ACDS, PGA, VLN, SH etc.
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An overly simplified Ramp ADC
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● Voltage-to-Time conversion
● Time-Digital conversion
Why ramp most common?
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● Low area
● Simple (it depends) analog side- no need for capacitor matching / linearity (has no capacitors)- DNL guaranteed to be <1 LSB - one continuous-time comparator (vs x2 + OTA in cyclic)- reference settling is not an issue, although: - comparator ramp kickback is difficult with continuous-time comparators - noise on ramp directly translates to output noise: - e.g. in SAR CDAC noise on references is divided (seen later)
● Mostly digital: easy to integrate with DCDS / post-processing ALU (e.g. CMS, HDR DCG combine, TDI accumulation etc...)
● Very easy to design if conversion time is not an issue
Why ramp most common?
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● If Tconv and resolution requirements are high - difficult
- high-res = high clock count = high clock frequency (or tricks)- fast clock leads to interference problems: - e.g. CMV50000 uses a 2.4 GHz ADC clock - sensor becomes a processor
- distribution of fast clocks difficult
- transient behaviour of ramp reference hard to model (in presence of interference noise)
● However:
— high-speed hi-res is a challenge with any architecture— no right or wrong approach in choice of architecture
Classic image sensor ramp ADC
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Ramp ADC Blocks and Specifics
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● Ramp reference schemes:
— Resistive Flash
— CDAC
— SC Integrator + Buffer
— CT integrator
● Counting methods and noise impact
● Comparator
● Noise
● Tricks to increase speed
Resistive Flash Ramp Topology
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+ easy to model
- high therm noise- high area- matching- need driver- t° drift
C-2C, CDAC Topologies
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+ low area+ noise (excl buffer)+ low t° drift
- matching- need driver
+ excellent noise+ no driver+ linear+ low t° drift
- very high area
Switch-Cap Integrator-Based
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+ easy to sync with count clock frequency
+ low area+ good linearity(as long as OTA is linear)+ good matching
- noise integration- need driver
PhiRst : Cf - shortPhi1 : Cs(V1-Vcm) Cf - lockedPhi2 : Cs(V2-Vfb) Cf - integrate
Continuous-Time Integrator-Based
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+ low area
- bad linearity- noise integration- need driver- t° drift
+ passive (almost)+ no driver needed
- low noise(if caps are large)- t° drift- reset jitter sensitiveboth need clock synchronization
and calibration (F-to-I converter)
Counter Methods
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● Latch vs Counter
● Low-area, low-power,- but can’t do post-processing (DCDS, CMS, DCG comb., etc…)
● More area, but dynamic (“crowbar”) current in column becomes an issue- but can do arithmetic operations
Counter Methods (Inversion)
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● Counter DCDS methods: inversion vs countdown
Source: OmniVision US 8576979
current spike
Counter Methods (Countdown)
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● Counter DCDS methods: inversion vs countdown
Source: Sony US 20090046190
current consumption identical
Counter Methods (Constant Power)
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● Counter array power consumption critical for crosstalk- impact on noise and accuracy
● A solution — full constant power:
Source: CMOSIS US 20110115663
Column Comparators
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● Power restricted MAX ~100ish µW● BW-limit 1st stage to improve noise (DCDS helps in 1/f noise)● Use Friis rule● Eliminate kickback noise (various schemes)● Comparator propagation time approaches Tconv (in very
fast ADCs)● Gain requirement usually met by 2-stages, PM not an issue
Kickback Noise Problem
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● Worst at uniform illumination
● ...and minimal comp offset
● To reduce kickback (typically):
— good comparator design— power penalty (depends)— low-ohmic reference line— OR high ramp load damping— OR extremely high-ohmic reference line (usually by in-column buffering and comes at cost of power)
Noise in Single-Slope (Ramp) ADCs
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● Wiener process (random walk) on ramp● Direct translation to DN● Signal-dependent● dV/dT improves translation
Noise in Single-Slope (Ramp) ADCs
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Clock Speed Limitation
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● Conversion time (DDR counting)
Tricks to increase speed
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● Grey code counting
● ~3x faster counting (current example)
- depends on the number of Grey interpolation clocks
Tricks to increase speed
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● Johnson counting (Flash TDC-interpolation)
Tricks to increase speed
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● Increase quantization step above a threshold● Count to e.g. 10-bits (instead of 12)● Fill LSBs with artificial noise from an LFSR
● PTC-Inspired ramp
PTC-inspired Ramp
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Ram
p V
olt
age
Time
T1 T2 T3
LSB
Threshold levels
Skip Counts
Add noise from LFSR
Other hybrid speed increase tricks
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● Coarse-fine multiple ramp scheme
● Look-ahead ramp
● Dual-counter based ramp (one-shot DCDS)
● PTC-inspired ramp
● TDC-interpolated ramp
● Dual-slope oversampling ramp
● Nutt interpolated ramp
● Vernier/Time-stretching TDC-interpolated
● Many more
