PLL (Tsmc 0.18 process)
17
EE486 Digital VLSI- Final Project Clock Multiplying DPLL Chen Zhai Klipsch School of Electrical and Computer Engineering New Mexico State University [email protected]
description
Class presentation
Transcript of PLL (Tsmc 0.18 process)
EE486 Digital VLSI- Final Project
Clock Multiplying DPLL
Chen ZhaiKlipsch School of Electrical and Computer Engineering
New Mexico State [email protected]
Presentation Outline
o Block Diagram
o Specification
o Loop Filter Parameters
o Sub-blocks
o Simulation
o Comments and Questions
Block Diagram
Specification
o TSMC 0.18 Standard CMOS
o Supply Voltage 1.8V
o Input Frequency 150MHz
o Output Frequency 750MHz
o Load 1pF
o Lock Time ~ micro seconds
Loop Filter
Spec:
Input Frequency
Natural Frequency (~Bandwidth)
Damping Factor
Results:
Design Values: R, C1, C2, Ipump
Performance: Lock time, etc
Linearized Current-Starved VCO with Output Buffers
Linearized Current-Starved VCO Tuning Curve
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
200
400
600
800
1000
1200
Vin/V
Fre
quen
cy/M
Hz
Vin_max=1.8VVin_min=Vtn=0.5V
Fmax=1.068GHzFmin=83.26MHz
Kvco=758MHz/V
Divide by 5 Circuit
Sequence:
000001010011100
Synchronous Reset
High-speed Phase Frequency Detector
Charge-pump
DPLL Schematic
DPLL Test-bench
Simulation Result
Simulation Result
Simulation Result
Simulation Result-Locked
Measurement Result
Output Frequency 750.00MHz
Jitter 10.2ps
Lock time ~0.5 us
Key Parameters of DPLL:
Natural Frequency (Bandwidth)Matching (delay, current of charge-pump)Speed (Divide-by-5)
