Progress on enabling EUV Lithography for high volume...

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Progress on enabling EUV Lithography

for high volume manufacturing

Jack Chen

5 October 2015

2015 EUVL Symposium, Maastricht

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© 2015 TSMC, Ltd

1

Jack Chen@ EUVL Symposium 2015, Maastricht

Acknowledgements

The EUVL development in TSMC is a big project

involving many people from EUVL one team between

TSMC and ASML(including Zeiss, Cymer & Trumpf),

EUV mask, Resist, OPC, Metrology, Integration/Etch,

and with great supports from infrastructure

suppliers including mask blanks and resist

materials.

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EUVL simplifies patterning process!

Example for multi-patterning techniques:

Andrea Wüest, et al., SPIE 2009

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EUVL is capable of random 2D layout

NA=0.25 NA=0.33

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Similar Electrical Uniformity as SADP

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Metal Sheet Resistance (arb. unit)

ArFi + SADP

EUV site1

EUV site2

cu

mu

lative

%

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Mask 1

Mask 2

Mask 3

Mask 4

Immersion Etch

Immersion 4 masks vs EUVL 1 mask

EUV single patterning

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Challenges for HVM insertion

1. Productivity (CoO)

2. Mask infrastructure (defectivity)

𝑾𝑷𝑫 ∝𝑷𝒐𝒘𝒆𝒓 ∗ 𝑨𝒗𝒂𝒊𝒍𝒂𝒃𝒊𝒍𝒊𝒕𝒚

𝑫𝒐𝒔𝒂𝒈𝒆

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Laser-produced-plasma EUV source

Courtesy of

ASML

Intermediate

Focus

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Progress has been made on the EUV source E

UV

Pow

er

(W)

Operating settings for

the 125 wph source

are being finalized

Year

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8 weeks of productivity on a NXE3300

Process Conditions

Wafers of various lot sizes and required doses

8-week-average WPD: 203 wafers

Total wafers processed: 11375

Average Tool Availability: 55%

Data shown are prior to source upgrade to 80W

One bar represents a single day

Q4 2014 data, as presented by Tony Yen at 2015 SPIE, San Jose

After 80W

upgrade: 1022

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Recent Productivity Improvement on NXE3300

Process conditions

Wafers of various layers/lot sizes with required dose, CD, and overlay

4-week-averaged WPD: 518 wafers

Total wafers processed: 15040

4-week-averaged tool availability: 70.2 %

One bar represents a single day

WP

D

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Stable CD/Overlay in the 4 weeks

12

6

0

-6

-12

Ov

erl

ay m

ax

/min

(nm

)

2

1

0

-1

-2

CD

err

or(

nm

)

Due to correction mistake

Mix-Match overlay to an ArFi scanner

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Dose to size(mj/cm2) 25 13 20 30 15 40

Target

Progress on Resist Sensitivity

35

ILLU-1

Tuning nobs:

-- Image contrast

-- Resist performance

-- Smoothing techniques

LW

R (

arb

.)

Inorganic resist

(Inpria >80mj/cm2)

by PSI, 2012

ILLU-2

Sm

oo

thin

g

smoothing

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Opportunity by developing metal resists

S. Chakrabarty, C. K.

Ober, Cornell university, SPIE 2014

Resolution/LWR vs Sensitivity

Inpria

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Challenges for HVM insertion

1. Productivity (CoO)

2. Mask infrastructure (defectivity)

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Native defects on sampled mask blanks

0 1 2 3 4 5 6 7 8 9 10 11 122014 2016 2015

Defe

cts

per

Bla

nk

Resolution of inspection:

23nm SEVD

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Native defect mitigation is in place

Pre-conditions:

1. Very low blank

defect counts

2. Precise blank

defect map

3. EBMW alignment

capability

Pattern to be written

Blank defect map

Hide defects under the absorber!

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Piecemeal cluster

21nm

ML defect inspection is challenging!

Wafer Image Mask Image

Mask ML ~2-3nm step height can already

cause dark phase defect!!

ML defects can only be detected without

absorber.

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SEM Image Scanning

Route

Fall–on Particles on Mask Surface

Repeaters from wafer

defect inspection

Fall-on particle

on mask

~1mm

The others were

mask defects.

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Prototype pellicle was tested in NXE3100

w/o pellicle

LWR: 4.0 nm

Dose to size = 21.7 mJ/cm2

Half-sized Si

membrane

with pellicle

LWR: 3.7 nm

Dose to size = 30.2 mJ/cm2

𝑇𝑟𝑎𝑛𝑠𝑚𝑖𝑠𝑠𝑖𝑜𝑛 =21.7

30.2= 85.5% 𝑇ℎ𝑖𝑐𝑘𝑛𝑒𝑠𝑠 = 55𝑛𝑚

Joint work with ASML

(Per single pass)

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TSMC EUV Pellicle Development

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

5mmx5mm 10mmx10mm 20mmx20mm 30mmx20mm 70mmx30mm 80mmx80mm 143x110mm

Full size

demonstrated

Membrane Dimension

Me

mb

ran

e A

rea

(mm

2)

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Summary EUVL processes, including scanner, resist, and mask, have been

intensely developed for insertion in high volume manufacturing.

The premium resolution of EUV lithography can drastically

simplify the complex ArFi+SAxP processes, reduced cycle time

and remove design constrains at sub-10nm nodes.

We have demonstrated productivity of average >500 good-wafer-

per-day for consecutive 4 weeks, with good CD and overlay

performance, on NXE3300.

Although some progress has been made, productivity (>250W

source and <20mJ/cm2 resists) and mask defectivity ( 0 ML

defects and fall-on particles) remain to be the key topics for

further development.

Progress on EUV pellicle development is convincing. However,

implementation of the pellicle is at cost of >20-30% of

productivity!

Progress on enabling EUV Lithography for high volume...

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