PhD SEMINAR 2004 - Nikhefd90/gossip/choermann_phd_se… · · 2005-03-15five metal layers for...

PhD SEMINAR 2004University of Zuerich, 6. - 7. October 2004

The Read Out Chip of the Compact Muon Solenoid Pixel Detector

Christoph Hörmann(University of Zuerich/ Paul Scherrer Institut)

� LHC and CMS environment

� CMS Pixel Detector Read Out Chip (ROC) PSI46

� architecture and general functionality of PSI46

� parameters of PSI46

� testbeam results of September and December 2003

� data loss mechanisms

� modifications from PSI46 to PSI46 version 2

� Single Event Upset capability

� prototype module and first results

Overview

Christoph Hörmann 204/10/07PhD Seminar 2004 University of Zürich


Compact Muon Solenoid

Pixel DetectorSilicon Tracker

Very-forwardCalorimeter

Electromagnetic Calorimeter

HadronicCalorimeter

Preshower

Muon Detectors

Superconducting Solenoid

Radius # Modules # Chips # Pixels Area [cm]

4 2`304 9.6 0.157 3`840 16 0.26

11 5`888 24.5 0.42total 12032 50.1 0.83

[× 106] [m2]

128 + 32½224 + 32½352 + 32½

800 (704 +96½)

CMS Detector

CMS Pixel Detector

Pixel Module

innermost tracking detector

basic building block of the barrel

CMS Pixel Detector

LHC environment and requirements on the ROC


� LHC and CMS environment:

� 40 MHz bunch crossing frequency (

�

t = 25 nsec)

� flux up to 40 MHz/cm2 (4 cm layer) at high luminosity (1034 cm-2 sec-1)

� 100 kHz Level 1 trigger rate

� Requirements on the pixel detector Read Out Chip under LHC conditions:

� zero-suppression because of large number of channels involved

� ROC must register pixel addresses and bunch crossing numbers during the latency of L1 trigger (128 bunch crossinges

�

3.2 �sec)

� continuous data taking and simultaneous readout operation

� radiation hard design (10 MRad/year for the innermost layer at high luminosity)

� low power consumption (50 Mpixels)

� analog pulse-height information to improve accuracy of hit reconstruction by signal interpolation

Deep Sub Micro (DSM) CMOS technology


Deep Sub Micron (DSM) technology:

� smallest feature size 0.25 �m

� Complimentary Metal Oxide Semiconductor technology (CMOS) (pFET & nFET)

� well known standard process also used by conventional chip industry

� can be designed radiation tolerant

� five metal layers for routing

� 8 inch wafers (standard material; same number of process steps but more chips)

� higher speed and lower power consumption (half supply voltage, half current) compared to former used DMILL technology

� 2002: development of a cell library, test structures on Multi Project Wafers

� PSI43 (DMILL technology) translation: September 2002 - June 2003

PSI46 received in August 2003

Parameters of PSI43 and PSI46


chipname DMILL_PSI43 IBM_PSI46

technology 0.8 µm BiCMOS, SOI, 2 metals IBM 0.25 µm, CMOS, 5 metals

size of final ROC layout 7950 µm x 10800 µm 7900 µm x 9800 µm

pixel array 52 x 53 = 2756 pixels 52 x 80 = 4160 pixels

pixel size (rϕ x z) 150 µm x 150 µm 100 µm x 150 µm

number of transistors 430 k 1280 k

number of supply pads 42 pads (150 µm pitch) 35 pads (175 µm pitch)

number of external capacitors 6 3

number of supply voltages 4 (5 V, 3.5 V, 3 V, 2.5 V) 2 (2.5 V, 1.75 V)

total supply current 160 mA 60 mA

Read Out Chip PSI46 overview


pixel array:

� 52 columns * 80 rows = 4160 pixels

� organised in 26 double columns

� pixel size: 100 �m * 150 � m (r � * z)

double column peripheri:

� pixel – column interface (column drain mechanism)

� 32 data buffers

� 12 timestamp buffers

global part:

� control interface block, I2C, 27 DACs,

� 6 regulators, counters, 35 supply pads

doublecolumn

doublepixels

databuffers

timestampbuffers

7900 µm

9800

µm

Read Out Chip PSI46 architecture


readout

Data:pulseheight+ addresses Time-stamps

Trigger

� pixel:

� waits for hits (10-3 per bc), notifies periphery to set time-stamp and start column drain mechanism

� no clock, no counter and no data buffer in the pixel

� column periphery:

sets time-stamps (10-1 per bc)

collects data from pixels, buffers data during the latency of the CMS trigger

until confirmed by the CMS trigger or latency passed

�

readout of triggered data (100 kHz) after token enters the chip

Pixel Unit Cell of PSI46


� analog:

� pre-amplifier, shaper, sample-hold mechanism, comparator

� threshold:

� 8 bits global

� 4 bits local trim

� pixel address:

� 3 * 3 bits digital

� 251 transistors per pixel

X1

D

Pixel address

Mask bit

globalthreshold

Trim 4 bit Double column bus

analogpart:

test pulse,1.6 fF, 0-1V

A

9

100

�m

150 � m

Analog Readout of PSI46


� differential analog output driver

� frequency: 40 MHz, 20 MHz fallback implemented

� 3 cycles header per chip

� addresses are analog coded in 6

levels

2 cycles double column (dc)

3 cycles pixel row

� 1 cycle analog pulse height

� repeated for each hit

� each readout pass returns data

for only one trigger number

eye diagramm to check uniformity of levels: generated from digital addresses at readout, readout frequency 40 MHz�

6 discrete levels clearly distinguishable

header dc pixel aout


� beamline �E1 at PSI:

� �- -beam, 300 MeV/c, 50 MHz bunch structure, chip operated with synchronized 40 MHz

� beam intensity variable up to 80 MHz/cm2 track density (40 MHz/cm2 @ 4cm layer and high luminosity)

� scintillators:

� size 2*2*2 mm3 cubes

� reduce trigger rate of scintillators by coincidence with random signal of radioactive source to ∼10kHz

� goal of testbeam:

data loss under LHC equivalent conditions

� general functionality of DSM ROC

PSI Testbeam Setup September and December 2003

PSI46 Performance


010

2030

4050

010

2030

4050

6070

800

100

200

300

400

500

600

h50

Entries 181989Mean x 22.08Mean y 36.24

RMS x 11.37RMS y 17.33

h50

Entries 181989Mean x 22.08Mean y 36.24

RMS x 11.37RMS y 17.33

clusters

0 10 20 30 40 50 60 70 80 90 1000 10 20 30 40 50 60 70 80 90 1000

0.005

0.01

0.015

0.02

0.025

0.03 PSI46 inefficiency

Hit rate (MHz/cm^2)

Inef

ficie

ncy

� single PSI46 ROC bump-bonded to a 280 �m thick silicon sensor

� hit map for events triggered with scintillators (2mm*2mm)

� beamspot 10 mm * 20 mm FWHM

� chip clock frequency 40 MHz

� comparator threshold 2500e-

� inefficiency defined as ratio of # 0-pix readouts to all triggered readouts� inefficiency like expected according to simulations e.g. 1.3% @ 40 MHz� PSI43: 5% @ 25 MHz/cm2

�

overall judgement: Chip works very well !!!

Data Loss Mechanisms of PSI46


Data Buffer full [24 � 32]0.1% � 0.15%

Timestamp Buffer full [8 � 12]3.1% � 0.17%

Waiting for Readout0.59% � 0.51%Double column readout

Pixel-column interface

Pixel waiting 0.3% � 0.2%

Column busy [2 � 3]1.4% � 0.25%(second & third hit capability)

CD setup [1 � 0] 3.9% � 0%

� Data loss simulations for LHC conditions for 4 cm layer @ high luminosity: PSI43 � PSI46

�

PSI46 acceptable for inner layer @ high luminosity

Modifications from PSI46 to PSI46 version 2


� PSI46 works very well, but still a few problems:

� oscillation of voltage regulator system

� problem with large charge injection

�

generates two hits!

� readout of analog pulse height

� analog pulse height variation from pixel to pixel and from double column to double column

� noise of analog pulse height

� DAC ranges adjustment and uniformity

� token_out driver too slow

� changed storage cells of ROC to improve Single Event Upset (SEU) capability

PSI46 V2 submitted to IBM end of August 2004 (production time ! 12 weeks!)

motivation


"

Single Event Upset (SEU) is the flipping of one bit, caused by a high energy deposition in a small sensitive volume of the electronics chip

# well known problem in space applications

# neglected in accelerator physics so far but LHC has increased radiation level

# SEU is more dangerous in Deep Sub Micron (0.25µm) technology (smaller node caps, faster circuits, lower supply voltage)

$

no problem for data (neglectable)

$

problem for detector control functions due to memory upset (regulators, trimbits for threshold, mask bit, ...)

$

SEU requires permanent reloading of storage cells (data traffic!)

SEU mechanism


IN OUT1 0

1

1

0

0

+V

011

threshold

t∆t ≥70ps

%

%_

& hadronic interaction of p/n/ ' with nuclei in lattice (displacement of lattice atoms by elastic and inelastic scattering...)( permanent material changes (rad. damage) Non Ionizing Energy Loss = NIEL (~3 Me- ) ~10 MeV)*

responsible for Single Event Upset*

reverse biased p/n junctions most sensitive

+ interaction with electron cloud+ transient effect+ Minimal Ionizing Particle = MIP (~70e-/1 ,m - ~22 ke- . 80 keV in sensor)/

used for regular particle detection in sensor

latch = storage cell for one bit e.g. nFET

p++

n+SiO2

UDSGate

Drain

Source

p-substrate

depletion zone Si

incomingparticle

nuclear recoil(~10 MeV, ~10 0 m)

+ -+ -+ -+ -+ -+ -

ionisation(3.62eV/e- hole Si)

teststructure for testbeam at PSI


1 teststructure designed in Deep Sub Micron Technology (0.25 2 m)

1 500 Flip Flops (FF) per shift register (one FF = two latches)

1 SEU testbeam: 300 MeV/c π+ beam, (flux ∼ 1.3*109 Hz/cm2)

3

purpose of testbeam: effect of protection mechanism

IN

Write

Dual Interlock Storage Cell = DICE(Calin, Nicolaidis, Velazco, IEEE Trans.Nucl. Sci., Vol43, No.6, 1996)4

needs simultaneous write to two nodes in order to flip4

due to design error doesn't work!

capacity forprotection

1 m

m

3 mm

650 5m585 6m

650 7m 830 8m

testbeam result 1


9 spatial distribution of SEU (0 : 1) for run_1400:

; 1.5 V, 160 read outs, every 5 min, stored bit = 0

0

2

4

6

8

10

12

14

16

0 2 4 6 8 10 12 140

5

10

15

20

25

30

shift reg 0 (nocap) sum SEU: 3471shift reg 0 (nocap) sum

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 2 4 6 8 10 12 140

5

10

15

20

25

30

shift reg 1 (cap) sum SEU: 59shift reg 1 (cap) sum

0

2

4

6

8

10

12

14

16

0 2 4 6 8 10 12 140

5

10

15

20

25

30


0

0.5

1

1.5

2

2.5

3

0 2 4 6 8 10 12 140

5

10

15

20

25

30


0

2

4

6

8

10

12

14

0 2 4 6 8 10 12 140

5

10

15

20

25

30


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 2 4 6 8 10 12 140

5

10

15

20

25

30


0

2

4

6

8

10

12

14

0 2 4 6 8 10 12 140

5

10

15

20

25

30


0

0.5

1

1.5

2

2.5

3

0 2 4 6 8 10 12 140

5

10

15

20

25

30


summary SEU_0to1 of run: 1400 voltage: 1.50V

testbeam result 2


< spatial distribution of SEU (1 = 0) for run_1400:

> 1.5 V, 160 read outs, every 5 min, stored bit = 1

0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.5

1

1.5

2

2.5

3

SEU: 274shift reg 0 (nocap) sum

0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

SEU: 0shift reg 1 (cap) sum

0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.5

1

1.5

2

2.5

3

3.5

4


0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5


0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5


0 2 4 6 8 10 12 140

5

10

15

20

25

30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


summary SEU_1to0 of run: 1400 voltage: 1.50V

testbeam result 3


? standard FF @ 2.0 V:

@

σ = 2.87*10-13cm2 (0 A1)

B

σ = 1.15*10-14cm2 (1 C0)

D protected FF @ 2.0 V:

E

σ =1.86*10-15 cm2 (0 F1)

G

σ = 8.39*10-17cm2 (1 H0)

I gain of protection:

J

0 K1: ~ 150 @ 2V

L

1 M0: ~ 135 @ 2V

N asymmetry (0 O1)/(1 P 0):

Q

standard FF: ~ 25

R

protected FF: ~ 22

S PSI46: mask all pixels and look how many pixels are switched on after e.g. 12 h beam

T

sligthly different layouts in teststructure and ROC!

U

gain of protection π+ (0 V1): σ+/σ+= 94;

W

asym π - (0 X1)/(1 Y 0): σ−/σ−= 120 (standard)

supply voltage [V]1.4 1.6 1.8 2 2.2 2.4 2.6

]2cr

oss

sec

tio

n [

cm

10-16

10-15

10-14

10-13

10-12

1 no prot→ 0 σ: +π

0 no prot→ 1 σ: +π

1 prot→ 0 σ: +π

0 prot→ 1 σ: +π

1 no prot PSI46→ 0 σ: -π

1 no pro PSI46→ 0 σ: +π

1 no prot PSI46→ 0 σp:

0 no prot PSI46→ 1 σ: -π

0 no prot PSI46→ 1 σ: +π

1 prot PSI46→ 0 σ: +π

0 prot PSI46 (upper limit)→ 1 σ: +π

ROC PSI 46

measured cross sections for SEU

testbeam result 4


Z

problem with asymmetry π- (0 [1)/(1 \ 0):

σ−/σ−= 120

] PSI46 mask bit of pixels:

masked = 1 stored

enabled = 0 stored

^

minor operational problem

_ PSI46 trim bits of pixels:

not trimmed = 0 stored

trimmed = 1 stored`

more problematic, because trimming lowers comperator thresholds a

busy pixels

b

data traffic!!

c

changed logic of trim bits to use benefit of asymmetry in PSI46V2

fluxproton = 157 MHz/cm2

d

145 SEU in 13.5 h

psi46 pixel map

SEU improved storage cell


1 e 01

00

00

110

1

1 0

rev. biasedjunction (1 stored)

rev. biasedjunction (0 stored)

f background: reverse biased p/n junctions are sensitive for SEU

g reduce # of rev. biased junctions from 5 h 3 but in sensitive area the gain is factor of 4 (drain and source of ring transistor is sensitive for SEU!)

i

should cause reduction of flipping rate in both directions

j

implemented in PSI46V2 (trim & mask bit) pixel unit cells

idea to reduce flipping rate of latches (storage cell):

prototype module with PSI46


k assemblied prototype module consisting of:

l base plate stripes instead of solid base plate (material budget!) with decoupling capacitors

m 16 PSI46 ROCs bump bonded to sensor

n High Density Interconnect (HDI) for signal and power routing to ROCs

o Kapton cable for control signals and power cable

p no Token Bit Manager (TBM) chip

q first time of operation of 16 ROCs (fclock = 10 MHz, 20 and 40 MHz)

r simultaneous readout and data taking works

s power consumption: Iana = 400 mA, Vana = 1.6 V; Idig = 600 mA, Vdig = 2V

t

total power consumption u 2.3 W not optimized (TDR: 2 W)

v some minor design errors on HDI, but manageable!

measurements with prototype module


Summary and Outlook


w Read Out Chip PSI46 works very well

x improved version PSI46V2 submitted end of August and will be back until end of November

y received Token Bit Manager Chip this week

z first complete module with 16 PSI46 and Token Bit Manager next weeks

{ testbeam in December 04 or spring 05 at PSI with single ROC or/and module with PSI46/PSI46V2

| start production of 400 modules for layer 1 & 2 in spring 2005

PhD SEMINAR 2004 - Nikhefd90/gossip/choermann_phd_se… · · 2005-03-15five metal layers for...

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