Novel chip last method for embedded actives in

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 63

Novel Chip-Last Method for Embedded Actives inOrganic Packaging Substrates

Baik-Woo Lee, Venky Sundaram, Scott Kennedy, Dirk Baars, and Rao Tummala, Fellow, IEEE

Abstract— Embedded actives are to bury thinned active chipsinto package substrates, as opposed to surface mounted devices(SMDs), which can achieve smaller form factor, better electricalperformance and higher functionality than the SMD technology.While many embedded actives have been explored so far, they arebased on chip-first and -middle approaches, in which the activechips are embedded before and during the build-up processes ofpackage substrates, respectively. The most concern with those twocurrent approaches is the loss accumulation associated with thebuild-up layer processes carried out right on top of the embeddedchips, which is highly likely to lose the embedded chips duringtheir packaging process. The reworkability to replace the faultychips embedded with good ones and thermal management ofthe embedded chips are also issues since the embedded chipsare totally surrounded by hard-cured polymers. In this paper,chip-last embedded active has been proposed to address someof the issues that are reported in current chip-first and -middleapproaches, in which chips are embedded after all the packagesubstrate processes including the build-up layers are completed,just like conventional SMD packaging. In the chip-last approach,a cavity is introduced within the build-up layers of packagesubstrate and a chip is directly embedded into the cavity. A firstproto-type of the chip-last embedded active will be demonstratedby developing various cavity formation processes within the build-up layers and then embedding 100 µm thick chips into the definedcavities.

Index Terms— Chip scale packaging, electronics packaging,embedded actives, flip-chip, organic laminate.

I. INTRODUCTION

GREATLY increasing demand for highly integrated andmicrominiaturized convergent electronic systems require

effective system integration solutions to incorporate the nec-essary technologies, including digital, analog, radio frequency(RF), optical and bio-sensing. System-on-package (SOP) con-cept has been a strong contender in facilitating the effectivesystem integration, which realizes all the system functions onan ultraminiaturized, multi-functional, and high-performance

Manuscript received February 17, 2011; revised July 2, 2011; acceptedAugust 19, 2011. Date of publication November 29, 2011; date of currentversion January 5, 2012. This work was funded by the EMAP consortiummembers at Packaging Research Center, Georgia Institute of Technology,Atlanta. Recommended for publication by Associate Editor C. Gurumurthyupon evaluation of reviewers’ comments.

B.-W. Lee is with Samsung Institute of Technology, Suwon 440-600, SouthKorea (e-mail: [email protected]).

V. Sundaram and R. Tummala are with 3-D Systems Packaging ResearchCenter, School of Electrical and Computer Engineering, Georgia Institute ofTechnology, Atlanta, GA 30332-0560 USA (e-mail: [email protected];[email protected]).

S. Kennedy and D. Baars are with the Rogers Corporation,Rogers, CT 06263 USA (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2011.2167013

package, by integrating both active and passive componentsinto a single high-density package substrate [1]–[2]. Embeddedactives, in which thinned active chips are directly buried intopackage substrates, not merely mounted on their surface, areof great interest for next generation advanced SOP.

Currently, active chips can be embedded in many differentways within categories of chip-first and -middle, depending onthe approaches involved. Although the first demonstration ofchip-first embedded active technology dates back to 1975 [3],more recent chip-first embedded actives have been developedby General Electric [4], Intel [5], Fraunhofer [6], and others[7]–[11] since the early 1990s. In the chip-first embeddedactives, chips are first buried into various types of organiccore and then build-up layers, which are alternating layersof patterned metal forming signal or power/ground planelayers and organic dielectric to electrically isolate the metallayers, are disposed on top of the chips and the core. Forthe chip-middle embedded active, where chips are embeddedin the middle of build-up layer processes, Shinko ElectricIndustries Co., Ltds approach is a representative example[12]. A chip is placed face down onto a build-up layer likethe surface mount technology process and fully embeddedafter subsequent build-up layers.

While current chip-first and chip-middle embedded activeapproaches offer many advantages such as small form factors,increased functionality, and better electrical performance, theyalso have a few drawbacks: 1) lower package process yieldsand higher costs; 2) poor reworkability; and 3) thermal man-agement problems.

To address some of these issues for chip-first and -middleembedded actives, we have proposed a chip-last approach forembedded actives, in which a cavity is formed to accommodateactive integrated circuits within the build-up layers of packagesubstrates and then a chip is embedded directly into the cavitywith appropriate electrical interconnections to the build-uplayers. In fact, chips are embedded after all substrate processesare finished. The chip-last approach for embedded activesthus offers many advantages over chip-first or -middle onesfrom the standpoints of process and yield, reworkability, andthermal management since its processes are more similar toconventional packaging processes. In this paper, an emphasis isespecially put on the process development of cavity formationand chip assembly into the cavities for the first demonstrationof chip-last embedded active.

II. CHIP-LAST EMBEDDED ACTIVE

Fig. 1 shows the schematic cross-section of the embeddedactives by noble chip-last approach, which has been proposed

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64 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012

Embeddedinductor

Solderinterconnects

Embeddedcapacitor

Blind-via

Embeddedchip

Chip

EmbeddedresistorUnderfill

Build-up dielectricOrganic corePlated through holes

Metal traces

Fig. 1. Schematic of chip-last embedded actives and passives.

by the authors at Packaging Research Center of Georgia Insti-tute of Technology. The chip-last embedded active processesare realized on typical organic build-up package substrates,in which one or more of build-up layers are laminated oneither side of a single- or multi-laminated core. The basecore materials can be a glass-fiber reinforced epoxy resin likebismaleimide triazine (BT) or FR-4. The core has circuitry onits surface and plated through holes for connecting circuitryon one side of the core to the opposite side. The build-uplayers are accomplished by repeating dielectric lamination andmetallization processes on the core, as needed. Fig. 1 alsoshows that thin-film passive components such as capacitors,resistors, and inductors can be embedded during the build-up processes, enabling higher functionalized module package,even though it will not be demonstrated in this paper. In orderto embed or bury active chips into the organic build-up pack-age substrates, a cavity structure is introduced within the build-up layers during or after the build-up processes. This cavitystructure is the unique aspect enabling the chip-last embeddedactives. While the cavity is defined, the metal pads patternedon the core or inner build-up layers are exposed inside thecavity. Embedded chips are connected to the metal pads withvarious low-profile interconnect technologies including solderand metal pillar bumps, followed by filling with underfill andengineered adhesive materials. If needed, heat spreaders orsinkers can be placed on the exposed back side of chips.

The chip-last approach for embedded actives offers manyadvantages over chip-first or -middle technologies from thestandpoints of process yield, reworkability, and thermal man-agement. 1) Lower loss accumulation and higher process yieldare expected in the chip-last embedded actives because chipsare embedded after all the package substrate processes arecompleted just like conventional surface mounted device pack-aging. The build-up layer processes that are carried out afterchip embedding in chip-first and -middle embedded activesaccumulate their process losses on the embedded chips, ulti-mately leading to losses of the chips. In addition, high-pressurebuild-up lamination processes on top of the embedded chipshave been reported to induce chip cracking [13]. In our chip-last approach, no complex processing after chip embeddingis needed that could otherwise damage the chip. 2) Defectivechips can be replaced in the chip-last embedded actives ifreworkable interconnects and appropriate selection of underfilland encapsulation materials are employed. 3) Because thebackside of chip-last embedded active is exposed to air, manyconventional thermal management solutions can be applied.

(a)

(b)

(c)

(d)

Fig. 2. Schematic process flow of photolithography defined cavity substrates.(a) Circuitized BT core. (b) Solder mask layer. (c) First cavity layer.(d) Second cavity layer.

To realize these chip-last embedded actives, there are,however, some challenging issues like cavity formation,embedding of chip into the cavities and reworkable ultrathininterconnections with fatigue resistance. This paper focusesmainly on the cavity formation process and chip assembly intothe cavity for the first prototype of chip-last embedded actives.

III. CAVITY SUBSTRATES

A. Fabrication of Cavity Substrates

Three different kinds of cavity formation processes inpackaging substrates are explored including photolithography,plasma-etching, and laser-drilling. All of these processes arebased on micro-via formation processes, thereby enabling theuse of existing equipments with well-verified materials andprocesses.

1) Photo-Cavity Substrates: Photolithography is expectedto be among low-cost and mass cavity-generationprocesses. Photoimageable dielectric (PID) Probelec-81/7081(Huntsmann–Vantico Inc.) was used for build-up dielectriclayers and copper-clad BT of 500 µm thickness was used forcores. The Probelec dielectric materials were diluted to be75% with propylene glycol methyl ether acetate. Fig. 2 showsthe schematic cavity formation process flow through pho-tolithography. First, the Cu-clad BT was curcuitized [Fig. 2(a)]and then the PID materials were spin-coated on the circuitizedBT core for a solder mask layer. Then, the solder mask andvias opening needed were made through photolithographyprocesses, comprising drying of coated PID materials, patternexposure, post-baking, developing, and last curing. The overall

LEE et al.: NOVEL CHIP-LAST METHOD FOR EMBEDDED ACTIVES IN ORGANIC PACKAGING SUBSTRATES 65

(a)

(b)

(c)

(d)

Fig. 3. Schematic process flow of plasma defined cavities. (a) Dielectric andmetal mask layer lamination. (b) Metal mask patterning. (c) Plasma–etching.(d) Via metallization.

photolithography process was conducted according to man-ufacturer’s process recommendation. The thickness of soldermask layer coated could be controlled by the viscosity, spin-coating speed, and number of spin-coatings of PID materials.The solder mask layer here was 25 µm in thickness. Once viaand solder mask openings were finished, the open vias weremetallized by conventional semi-additive Cu plating (SAP)[Fig. 2(b)]. The metal layers were 10 µm thick. On top of thissolder mask layer, the PID materials were again coated andcavities together with vias needed were then defined throughphotolithography [Fig. 2(c)], similar to the solder mask and viaopenings in Fig. 2(b). The cavity dielectric layer was 50 µmin thickness. The opened vias around cavities were againmetallized by SAP process. The exposed metal pads within thecavities were protected from the via metallization with photo-resist films. Then, a second cavity layer was built-up over thefirst cavity layer, resulting in about 100 µm in total cavitydepth [Fig. 2(d)]. The second cavity layer was fabricated to beslightly larger than the first cavity layer since photolithographyprocess tolerances between layers need to be considered. Inthis paper, 50 µm were given to all four edges of the cavitiesas the tolerances. Depending on the required cavity depth,the cavity layer processes can be further repeated. The photo-cavities could be basically created without any additional costincrease while the vias were formed in the build-up layers.

2) Plasma-Cavity Substrates: Plasma-etching is alsoassumed to be cost-effective in generating high volumes ofcavities in dielectric layers since panels are loaded into aplasma chamber and etched simultaneously. Fig. 3 showsthe schematic process flow of cavity formation by plasma-etching. Two layers of RXP-4 dielectric (Rogers Corporation)were laminated on a circuitized BT core, leading to 100 µmthick build-up layers on the core. During the RXP-4 layerlamination, 18 µm thick copper layer was also placed ontop of the RXP-4 layers, as shown in Fig. 3(a). The plasma-etching mask was created on the copper by applying typicallithography processes [Fig. 3(b)]. The metal mask defines theposition and size of cavities as well as vias and unmaskeddielectrics are eroded by the plasma. Plasma was generatedin a partial vacuum filled with a mixture of oxygen andchlorofluoro (CF4) gases. Because plasma cavity formationis based on an etching process, careful process conditioningis needed to minimize undercutting. It was confirmed that theundercut could be minimized with a 3:1 ratio of oxygen toCF4 at a substrate temperature of 100 °C and the RF powerof 450 W. With these plasma conditions, the plasma-etchingrate was about 1 µm/min. Once cavities were formed byplasma-etching, as shown in Fig. 3(c), the copper metalmask could be easily peeled off by hand since any surfacetreatments on the RXP-4 materials were not made before thecopper lamination. Good lamination between copper and theRXP-4 materials requires some special surface treatmentson the RXP-4 materials [14]–[18]. The vias formed duringplasma-etching were filled by SAP plating [Fig. 3(d)]. Theplasma-cavities could also be created without any additionalcost increase while the vias were formed in the build-uplayers.

3) Laser-Cavity Substrates: Laser drilling, which uses afocused laser beam to create small vias, is considered to be themost promising via-formation technology and its equipmentsare also well-established for high-volume production. Severallaser processes, including excimer, YAG, and CO2, have beendeveloped to generate small vias. The smallest feature sizedepends primarily on the laser wavelength, beam energydensity, and thickness of the drilled materials. In this paper,UV laser has been used for the cavity process, which wasconfirmed to be able to ablate large area of RXP-4 build-up materials with cost competiveness. The application oflaser drilling to cavity formation in build-up layers is verystraightforward. The laser removes the dielectric materialsto form cavities. Better cavity shape can be achieved with-out the undercut, which was one of main concerns in theplasma-cavity formation methods. The laser-cavity process isalso relatively simple because it needs neither a complicatedphotolithography process in photo-cavities nor metal maskpatterning/removal in plasma-cavities.

Fig. 4 shows the schematic process flow for laser-cavityformation. Laser-cavity was formed on the RXP-4 layerslaminated on a patterned BT core like plasma-cavity substrate.Laser drilling was performed in two steps. Cavity area wasfirst laser-drilled until the laser beam reached about 90 µm.Then the second laser-drilling was applied only over thecopper pads, generating about 10 µm thick solder mask layer,


(a)

(b)

(c)

Fig. 4. Schematic process flow of laser defined cavities. (a) Dielectric layerlamination. (b) Laser drilling of cavity and via. (c) Via metallization.

as shown in Fig. 4(b). During cavity process, vias werealso created around the cavities and later metallized by SAPprocess [Fig. 4(c)].

B. Fabricated Cavity Substrates

Fig. 5 shows all three kinds of the cavity substrates fabri-cated by photolithography, plasma-etching, and laser-drilling,respectively. They were all well defined according to eachprocess detail described in the previous section, measuringabout 100 µm in depth. The photo-sensitive dielectric usedfor photo-cavity substrates is shown in dark brown color[Fig. 5(a)], while the low loss dielectric RXP-4 materials usedfor both plasma- and laser-cavity substrates are shown in alight green color [Fig. 5(b) and (c)].

As can be seen in Fig. 5, the metal pads, on which thesolder bumps of chips will be placed, are clearly seen insideall the fabricated cavities. The patterned pads on BT Cu cladlaminate had been covered by either photo-sensitive or RXP-4dielectric materials while the dielectric materials were coatedor laminated. When the dielectric materials were removed toform cavities by either photolithography, plasma-etching orlaser-drilling, the metal pads buried under the dielectric layerswere successfully again exposed.

Each cavity-substrate contains 32 cavities on it. Half ofthem are rectangular shaped for embedding 4.5 × 9.0 mmchips and the other half is square shaped for 7.0 × 7.0 mmchips. For the cavities of each shape, four different sizes ofcavities were fabricated by giving the four cavity edges anequal clearance varying from 50, 100, 200 to 400 µm toconsider various tolerances, such as chip size tolerances, cavityprocess tolerances, and chip placement tolerances inside thecavities. The electrical connection of vias, metal traces, and

(a)

(c)

(b)

Fig. 5. Cavities on 6 × 6 inch BT substrates fabricated by (a) photolithog-raphy, (b) plasma-etching, and (c) laser etching.

pads on all the cavity substrates was confirmed by daisy chaintesting.

Fig. 6(a)–(c) shows the shape of cavity edges dependingon the cavity formation processes. No cavity shape distortionwas observed in all the cases. Photo-cavities had the smoothestand sharpest edges. The edges of plasma-cavities were not as


(a)

(b)

(c)

Fig. 6. Enlarged view of cavity edge shape (a) photo-cavities, (b) plasma-cavities, and (c) laser-cavities.

sharp as those of photo-cavities, since the plasma undercutwas inevitable even though the undercut was minimized byoptimizing plasma processing parameters. In the laser-cavities,two of four edges were relatively smooth, while the other twoedges were saw-toothed, as shown in the horizontal cavityedges of Fig. 6(c). It was found that laser drilling started orended at either of these two saw-toothed edges. Fig. 7(a)–(c)shows the inside of each cavity. Solder mask layer could beformed on the photo- and laser-cavity substrates, while it couldnot be created on the plasma-cavities with current plasma-cavity process scheme.

Fig. 8 compares the sizes of the cavities fabricated for7.0 × 7.0 mm chip embedding with those designed on masks.It is observed that the photo-cavities had almost the samedimension with the ones drawn on the mask (<5 µm in sizedifference). The laser-cavities were, on average, 50 µm largerthan the cavities designed on the mask. The plasma-cavitieswere always much larger than the ones on the mask (about190 µm in size difference, almost double of the laminated

(a)

(b)

(c)

Fig. 7. Pad openings inside of the cavity (a) photo-cavities, (b) plasma-cavities, and (c) laser-cavities.

layer thickness) due to plasma-etching undercut, as describedearlier. It can be summarized that most accurate and precisecavity dimension control is possible with photo-lithographyprocess, followed by laser-drilling and plasma-etching.

IV. EMBEDDING OF CHIPS INTO CAVITY SUBSTRATES

A. Embedding Process Details

Thin chips of two different sizes were embedded and assem-bled into their corresponding sized/shaped cavities: rectangularchips of 4.5 × 9.0 mm in size with two-side peripheral I/Osand square chips of 7.0 × 7.0 mm in size with full-areaarray I/Os. As interconnections, solder bumps of 70–80 µmin height were used for both chips. Chips were fabricatedby conventional wafer bumping processes. Table I shows thedetails of chips used in this paper. Both chips had daisy chainsand were thinned to 100 µm by mechanical back grinding.

The chips were placed onto the metal pads within all thefabricated cavities with Fineplacer (Finetech GmbH & Co.),


6.6

6.8

7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

400 µmclearance

100 µmclearance

200 µmclearance

50 µmclearance

Cav

ity s

ize

[mm

]

DesignedPhotoPlasmaLaser

Fig. 8. Cavity size comparison.

TABLE I

CHIPS USED IN THIS PAPER

Rectangular chips Square chipsSize 4.5 mm × 9.0 mm 7.0 mm × 7.0 mmChip size tolerance ±2.5 µm ±2.5 µmSolder bump pitch 200 µm 150 µmSolder bump height 70–80 µm 70–80 µmNo. of I/Os 60 1936

which is known to provide placement accuracy of ±0.5 µm.No-clean flux (NR200, Alpha metals) was used to reducepossible flux residue in the gap between chips and substrateswithin the cavities. Solder was reflowed in a conventionalsolder reflow oven with a Sn-3.5Ag solder reflow profile(a peak temperature of 250 °C).

B. Embedded Chips in Cavity Substrates

Fig. 9(a) shows the fabricated photo-cavity substrates.Chips were embedded within the photo-cavities, as shown inFig. 9(b). With no disturbances from cavity structures, chipscould be successfully placed into any sized photo-cavities thathave the chip-cavity clearances varying from 50 to 400 µm.The X-ray images of Fig. 10 shows both rectangular andsquare chips assembled within the photo-cavities having thesmallest chip-cavity clearance of 50 µm. The rectangularchips have two rows of peripheral solder bumps with 200 µmpitches, while the square chips have area array solder bumpswith 150 µm pitches. The X-ray images also show that nosolder bridge or missed balls have been observed in bothcases. Daisy chain testing also confirmed that the electricalinterconnections from chips to cavity-substrates have beensuccessfully made.

While chips could be assembled into the plasma-cavities,solder bridge was observed (not shown here) since solder masklayer could not be introduced during plasma cavity formationprocess. For the successful chip embedding into the plasma-cavity substrates, it is thought that the plasma-cavity process tobe able to introduce a solder mask layer needs to be developed.

(a) (b)

Fig. 9. Photo-cavities (a) before chip embedding and (b) after chipembedding.

Solderbumps

Daisy chaintest pads

Vias

Solderbumps

Vias

Daisy chaintest pads

(a)

(b)

Fig. 10. X-ray images of the chips placed within the photo-cavities. (a) 4.5 ×9 mm2 rectangular chips with peripheral solder bumps. (b) 7 × 7 mm2 squarechips with area array solder bumps.

Similar to the chip embedding within the photo-cavities,successful chip embedding into the laser-cavities was achievedwith all the chip-cavity clearances varying 50 µm to 400 µm.Since solder mask layer could be created inside the laser-cavities, the solder bridge that was observed in the plasma-cavities did not occur.

V. CONCLUSION

The concept of chip-last embedded actives, in which activechips were embedded into package substrates after the fab-rication of the package substrates was completed, has been


proposed and its first prototype has also been demonstrated. Toenable these noble chip-last embedded actives, cavities havebeen introduced within the build-up layers of package sub-strates and the active chips have been placed into the cavitiesand electrically interconnected with circuits in them. Threedifferent cavity formation processes have been developedby applying commonly used micro-via drilling technologiesincluding photolithography, plasma-etching, and laser-drilling.The photolithography could define best shape of cavities andhave good cavity-dimensional controllability, while it alwaysrequires the usage of photo-sensitive dielectric for the build-up layers. The plasma- and laser-cavities do not need thephotosensitivity in the dielectric materials used. The plasma-cavity revealed considerable undercut during cavity formation,which resulted in bad controllability of cavity dimension. Thelaser drilling process was confirmed to enable to moderatelycontrol the cavity shape and dimension. Chip embedding intoall these three kinds of fabricated cavities was not so muchdifferent with conventional surface mount flip-chip assembly.Chip assembly could be successfully achieved within thephoto-cavities and the laser-cavities, while solder bridge hasbeen observed in the plasma-cavities since they do not containsolder mask layer within the cavities. Reliability evaluation forthese chip-last embedded actives was under study includingunderfilling process development within the cavities.

ACKNOWLEDGMENT

The authors would like to thank the Institute of Microelec-tronics, Singapore, for providing the chips used for this paper.

REFERENCES

[1] R. Tummala and M. Swaminathan, Introduction to System-on-Package.New York: McGraw-Hill, 2008, pp. 3–37.

[2] R. Tummala, “Moore’s law meets its match (system-on-package),” IEEESpectrum, vol. 43, no. 6, pp. 44–49, Jun. 2006.

[3] S. Yokogawa, “Method of manufacturing the same,” U.S. Patent 3 903590, Sep. 9, 1975.

[4] R. Fillion, C. Woychik, T. Zhang, and D. Bitting, “Embedded chip build-up using fine line interconnect,” in Proc. 57th Electron. Comp. Technol.Conf., May–Jun. 2007, pp. 49–53.

[5] R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, and G. Vandentop,“Emerging directions for packaging,” Intel Technol. J., vol. 6, no. 2, pp.62–75, May 2002.

[6] L. Boettcher, D. Manessis, A. Ostmann, S. Karaszkiewicz, and H.Reichl, “Embedding of chips for system in package realization - tech-nology and applications,” in Proc. 3rd Int. Microsyst., Packag., AssemblyCircuits Technol. Conf., Taipei, Taiwan, Oct. 2008, pp. 383–386.

[7] R. J. Wojnarowski, T. B. Gorczyca, and S. E. Weaver, “High densityinterconnected circuit module with a compliant layer as part of stress-reducing molded substrate,” U.S. Patent 5 866 952, Feb. 2, 1999.

[8] T. Rapala-Virtanen, T. Perälä, R. Tuominen, and P. Palm, “Embeddingpassive and active components in PCB-solution for miniaturization,” inProc. ECWC Conf., 2005, pp. S16-1–S16-7.

[9] Z. Liang, J. D. van Wyk, F. C. Lee, D. Boroyevich, E. P. Scott, Z. Chen,and Y. Pang, “Integrated packaging of a 1 kW switching module usinga novel planar integration technology,” IEEE Trans. Power Electron.,vol. 19, no. 1, pp. 242–250, Jan. 2004.

[10] W. Christiaens, E. Bosman, and J. Vanfleteren, “UTCP: A novelpolyimide-based ultrathin chip packaging technology,” IEEE Trans.Comp. Packag. Technol., vol. 33, no. 4, pp. 754–760, Dec. 2010.

[11] J.-C. Souriau, O. Lignier, M. Charrier, and G. Poupon, “Wafer levelprocessing of 3-D system in package for RF and data application,” inProc. 55th Electron. Comp. Technol. Conf., vol. 1. May–Jun. 2005, pp.356–361.

[12] M. Sunohara, K. Murayama, M. Higashi, and M. Shimizu, “Develop-ment of interconnect technologies for embedded organic packages,” inProc. 53rd Electron. Comp. Technol. Conf., May 2003, pp. 1484–1489.

[13] D. Manessis, S.-F. Yen, A. Ostmann, R. Aschenbrenner, and H. Reichl,“Technical understanding of resin-coated-copper (RCC) laminationprocesses for realization of reliable chip embedding technologies,” inProc. 57th Electron. Comp. Technol. Conf., Reno, NV, May–Jun. 2007,pp. 278–285.

[14] G. Krishnan, F. Liu, V. Sundaram, R. Pucha, S. Kennedy, D. Baars, J.Dobrick, D. Guo, J. Neill, S. Paul, and R. Tummala, “High performanceorganic dielectrics and high density substrates for next generation systemon a package (SOP) technology,” in Proc. 58th Electron. Comp. Technol.Conf., Lake Buena Vista, FL, May 2008, pp. 2101–2104.

[15] S. Kennedy, A. Horn, G. Bull, F. Liu, H. Chan, V. Sundaram, andR. Tummala, “An overview of material options suitable for today’scommercial millimeter wave designs,” Circuitree, vol. 22, no. 5, pp.16–21, May 2009.

[16] S. Hwang, S. Min, M. Swaminathan, V. Sundaram, H. Chan, F. Liu,S. Kennedy, D. Barrs, B. Lacroix, Y. Li, and J. Papapolymerou,“Characterization of next generation thin low-K and low-loss organicdielectrics from 1 to 110 GHz,” IEEE Trans. Adv. Packag., vol. 33,no. 1, pp. 180–188, Feb. 2010.

[17] S. Hwang, S. Min, H. Chan, V. Sundaram, and M. Swaminathan, “Acompact third-order 5 GHz bandpass filter with enhanced stopbandcharacteristics in ultrathin organic substrate,” in Proc. IEEE RadioWireless Symp., New Orleans, LA, Jan. 2010, pp. 452–455.

[18] D. Athreya, V. Sundaram, M. Iyer, and R. Tummala, “Ultrahigh Qembedded inductors in highly miniaturized family of low loss organicsubstrates,” in Proc. 58th Electron. Comp. Technol. Conf., Lake BuenaVista, FL, May 2008, pp. 2073–2080.

Baik-Woo Lee received the Ph.D. degree in materialscience and engineering from Seoul National Uni-versity, Seoul, Korea, in 2004.

He has been a Researcher with the Samsung Insti-tute of Technology (SAIT), Suwon, South Korea,since 2009, working on the advanced packagingstructural designs, materials and processes for bio,medical, and energy power applications. Prior tojoining SAIT, he was a Research Engineer withthe Packaging Research Center, Georgia Institute ofTechnology, Atlanta, focusing on system-on-package

technology, which includes embedded active integrated circuits, fine-pitchinterconnects, 3-D chip stacking, and embedded capacitors. He has severalU.S. patents and has authored over 30 publications in refereed journals andconferences.

Venky Sundaram (M’10) received the B.S. degreein metallurgical engineering from the Indian Instituteof Technology, Mumbai, India, and the M.S. andPh.D. degrees in materials science and engineeringfrom the Georgia Institute of Technology (GeorgiaTech), Atlanta.

He is the Director of Research with the Pack-aging Research Center (PRC), Georgia Tech, andalso serves as the Program Manager for the Siliconand Glass Package Consortium. He has been withPRC since 1997, focusing on system-on-package

technology, ultra-high density substrates, and systems integration research. Heis advising iNEMI on the new wiring density initiative. He is a Co-Founder ofJacket Micro Devices, Atlanta, GA, a radio frequency substrate and moduleGeorgia Tech PRC Spin-off Company acquired by AVX. He has several U.S.and international patents and has more than 100 publications in the systemspackaging technology space.

Dr. Sundaram has won several Best Paper and Poster Awards and servesas Session Chair for advanced packaging topics at international conferences.He is a member of the IEEE Components, Packaging, and ManufacturingTechnology Technical Committee of High Density Substrates.

Scott Kennedy photograph and biography not available at the time ofpublication.

Dirk Baars photograph and biography not available at the time of publication.


Rao Tummala (M’88–SM’90–F’94) received theB.S. degree from the Indian Institute of Science,Bangalore, India, and the Ph.D. degree from the Uni-versity of Illinois at Urbana-Champaign, Urbana.

He is a Distinguished and Endowed Chair Pro-fessor and the Founding Director of the NationalScience Foundation Engineering Research Center,Georgia Institute of Technology (Georgia Tech),Atlanta, the most comprehensive academic centerin microsystems packaging pioneering system-on-package vision since 1994. Prior to joining Georgia

Tech, he was an IBM fellow, pioneering major technologies such as thefirst plasma flat panel display based on gas discharge, the first and nextthree generations of multichip packaging. He is known as the Father oflow-temperature co-fired ceramic (LTCC) having developed 61-layer LTCCwith copper and copper-polymer thin film materials. He has published 426technical papers, holds 74 patents, and inventions. He has authored thefirst modern packaging reference book Microelectronics Packaging Handbook(Van Nostrand, 1988), the first undergraduate textbook Fundamentals ofMicrosystems Packaging (McGraw Hill, 2001), and first book introducing theSystem-on-Package technology.

Prof. Tummala has received many industry, academic, and professionalsociety awards including the Industry Week’s Award for improving U.S. com-petitiveness, the IEEEs David Sarnoff, Major Education, and Sustained Tech-nical Awards, the Dan Hughes Award from International Microelectronics andPackaging Society (IMAPS), the Engineering Materials Achievement Awardfrom DVM and ASM-International, the Total Excellence in ManufacturingAward from SME, the John Jeppson’s Award from the American CeramicSociety, as well as the Distinguished Alumni Awards from the Universityof Illinois and Georgia Tech. In 2011, he received the ISA TechnovisionaryAward from the Indian Institute of Science and the highest IEEE Award inpackaging at the 61st Electronic Components and Technology Conference forhis contributions in package integration research, cross-disciplinary education,and globalization of packaging. He is a fellow of IMAPS and the AmericanCeramic Society, and a member of the National Academy of Engineeringin U.S. and India. He is a past President of both the IEEE Components,Packaging, and Manufacturing Technology Society and IMAPS Society.

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