Electrical Characterization DesignOptimizationof Embedded ...paper discusses the electrical design...

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Nithya Sankaran, Baik-Woo Lee, Venky Sundaram, Ege Engin, Mahadevan Iyer,Madhavan Swaminathan and Rao Tummala

Packaging Research CenterSchool of Electrical and Computer Engineering, Georgia Institute of Technology

813 Ferst Drive, Atlanta, GA 30332-0560, USAEmail - gth874e(mail.gatech.edu, Phone: (404) 694 -1788

AbstractEndless demands for digital convergence by ultra-

miniaturization, increased functionality, better performanceand low cost in both mobile and desktop systems are drivingthe needs for new and unique solutions in system integration.The requirements of future electronic systems include faster,smaller, lighter and thinner products. Advanced electronicpackaging caters to these ultra-miniaturization andperformance needs. The approach of embedding passivecomponents has been in the fray for a while now and therelatively newer perspective to sustain the miniaturizationtrend efficiently is by embedded active chips as well. Thispaper discusses the electrical design aspects of embeddedactives dealing with the chip-last methodology of embeddingdies in particular. The various issues that are expected tosurface are made clear through electromagnetic simulationsusing 3D solver tools. The transmission lines forming thesubstrate wiring when the cavities are made are analyzedcomprehensively. A test vehicle is fabricated based on thisnew approach and preliminary measurement results are alsoincluded in this paper.

1. IntroductionSystem-in-Package (SIP) and System-On-Package

(SOP) are key enabling technologies for digital and RF microminiaturization and system integrations on silicon, ceramicand organic substrate platforms, offering diverse functionalityin a single module. There is also a continuing demand for theminiaturization of this module [1]. The 3D integration andstacking of components are also methods that are applied toachieve the miniaturization of systems. [2]. One of theinnovative approaches adopted to achieve this 3D integrationis embedding active and passive components. Embedded chiptechnology is being accepted for miniaturization of RF, baseband and other mixed signal modules. The trend ofembedding active chips in substrates has been initiated byGeneral Electric Co [3], Intel [4], Shinko [5], FraunhoferInstitute [6] and others. Embedded actives are sought after asthey are expected to reduce the parasitic effects ofinterconnects (reduced interconnect length) resulting in lowerpower dissipation, provide better electromagnetic shielding.They also offer smaller and thinner package profiles. TheEmbedded actives can be broadly classified into Chip first andChip last approaches. In the Chip First approach, the wiringand build-up layers are formed above the chip. This approachsuffers from the following limitations: (1) The chip, once it isembedded is subjected to a whole lot of processing steps andit can be affected due to the fabrication (2) Serial chip-to-build-up processes accumulate yield losses associated witheach process. (3) Defective chips cannot be easily reworked in

current embedded package structure. This needs 100% KGDs(Known Good Die). (4) The interconnections in chip-firstapproach which are direct metallurgical contacts canencounter fatigue failures due to thermal stress. (5) Thermalmanagement issues are also evident since the chip is totallyembedded within polymer materials of substrate or build-uplayers processes. In the Chip Last approach the chip is placedin a cavity after all the wiring and build-up layers have beencompleted. This method is to almost relieve all the stresses ofthe fabrication that chip is put through in the earlier case. Thefinal component to go in the system package is the die.

Most of the published works on embedded actives aremainly from materials and process technology perspective.Electrical analysis of the embedded active technologies hasnot been well reported and documented to date. This papergives insight into the issues likely to be faced in the electricalfront when the chip last methodology of embedding dies isbeing followed and also on the ways that can be sought toimprove the performance. A comparison with Chip firstapproach is also done in this study. This is to show that theproblems of impedance variation and matching also surface inthe substrate wiring of the Chip-first case.

2. Embedded Chip Cavity DesignsThe transmission lines determine signal propagation

characteristics in a package and the behavior of these whenresorting to SIP/SOP with embedded chips needs specialattention. Primarily this analysis includes investigation oflines inside the cavities, buried transmission lines, thetransition of surface micro strip lines to buried lines, theproximity of the transmission lines to the dielectric cavitywall, and the influence of the cavity sizes. This includes aparametric study to show what kind of variations one canexpect when adopting embedded actives and also to quantifyhow much of variation the system requirements can tolerateand if it is feasible to adapt to this new method of packaging.

Trace withiiithe cavity

Trace oin thestibstiratestiiiface

b

a - cavity deptlb - ikt of suibste

below the tace

Fig 1. Cross-section of substrate with Cavity

992 2007 Electronic Components and Technology Conference1-4244-0985-3/07/$25.00 02007 IEEE

When the die is embedded in the cavity all theinterconnects need to be routed out of the cavity to join thesubstrate wiring. In this, the performance of surface microstriptransmission lines, buried lines and those within the cavity arecompared.

Fig. 1 shows the schematic of the transmission linesinvestigated in embedded chip cavity design. The three casesof transmission lines listed below are investigated in thedesigns.

1) A surface microstrip line on a substrate of thicknessa+b

2) A surface microstrip line on a substrate of thicknessb

3) Microstrip line on the surface of a cavity (of depth a)with the substrate height below the cavity as b (Thisconfiguration is shown in the figure)

The design involves a parametric study including thecavity depths, buried lines in substrates with cavities, routingof traces in and out of the cavities and cavity lateraldimensions for chip last method and routing buried traces forchip first method.

2.1 Cavity depthFor a given substrate height when the cavity depth is

changed (i.e. a (as shown in figl) is changed), the substrateheight below the trace on the cavity surface will also change(b (as shown in figl) changes as well) and this will cause alllines to have widths of varying values. When we look at usingembedded actives for commercial systems packaging it is verynatural to consider embedding more dies as against one. Inthese scenarios, using dies of different thicknesses will causecavities of different depths and the issue of varying tracewidth will become a concern.

2.2 Buried lines running under cavitiesAnother aspect to be considered is when there are multiple

cavities in the same substrate with traces running beneaththem. When pursuing embedded actives, the substrate wiringgains prominence. The behavior of these buried lines isdependent on the height of the substrate above them and whenthis height keeps changing, the line width will needmodification at all the regions where the line crosses thecavity. This happens across the substrate demanding designrules restrictions. The design rules should be flexible toinclude the tolerances in line width variation. Generally it isnot preferred to have the physical dimension of wiring to keepchanging often, but this is one concern that needs to beaddressed when resorting to embedded actives.

2.3 Routing traces in and out of the cavityAll the lines which are laid within a cavity need to be

extended out in order to be routed to different layers. Theselines become buried micro strips when extended outside thecavity. The line widths will have to be reduced to obtain goodimpedance matching. The transition can be of a tapered line ora stepped impedance transformation. These are discussedmore in section 4.

2.4 Cavity lateral dimensionsNext are the cases where we have the cavity width

changing, and the proximity of the dielectric wall to thetraces. A chip will have sizeable number of interconnects and

it is not possible to route all the traces in the centre region ofthe cavity. Also not all cavities in a substrate will necessarilyhave the same lateral dimensions. When surface microstriplines are analyzed, the ground is spaced wide enough, with thetest line usually centered over the ground patch. When thecavity width changes, the above configuration which isusually employed for testing is not sufficient. As will be seenin section 4, cases where the cavity width and the proximity ofthe traces to the walls of the cavity are analyzed for the lossresponses of the transmission lines.

2.5 Chip first embedded activesSubstrates with chip-first approach of buried dies are also

being analyzed as to how the buried transmission lines areaffected by the presence of the embedded die. There seems tobe variations in the impedance of the traces running overthem. So the issues of impedance matching will surface andsubsequent trace width changes will be required to solve thisproblem.

3. Design, Fabrication and Electrical characterization ofTest vehicle

3.1 Test Vehicle ModelThe test vehicle cross section is as shown in the figure

below

CavityBuildlu-tpdielectriclayer 2

Build-updiele triclayer I

lMetal Layer 4Metal Layer 3MMetal Layer 2Metal Layer I

S ibstrateEBT- 500 imicroiis

Fig2. Cross section of test vehicle

Fig3. HFSS model of the test vehicle

The test vehicle is a 4 metal layer build up structure. Forsubstrates, Cu-clad BT (Bismaleimide Triazine) of 500 pim inthickness was used and the build up dielectric layers are of thephoto-imageable dielectric material, Probelec-8 1/7081(Huntsmann-Vantico Inc.) The build up layers are each 50microns thick; the lateral dimension of the board is 6 X 6inches. The layer stack up consists of three build-up dielectriclayers and four metal layers. The metal lines are 10 pim thick.

993 2007 Electronic Components and Technology Conference

3.2 SimulationThe tool used for modeling the test vehicle structure is

ANSOFT HFSS, a 3D electromagnetic solver. This tool canwell support the creation of the test vehicle geometry.

The figure below shows the HFSS model of the testvehicle used for simulation. The transmission line is modeledinside the cavity in the 3rd metal layer. This is transitioned outof the cavity and is brought to the top metal layer for probingthrough vias. The probe pads can also be seen in the model.The ports for the excitation of the model are lumped ports andthey are declared at the probe pads on either side.

3.3 FabricationThe transmission line based structures are a part of a larger

board. The layout of the test vehicle design is given by Fig5and Fig4 shows the zoomed region consisting of the cavitiesand the transmission lines. As it can be seen in the figure,there are four cavities each with 3 lines. These are differentvariations of trace width. The cavities are formed on the 3rdbuild-up layer and the 2nd metal layer serves as the ground.The depth of the cavities is the same as that of the build-uplayer, 50 ptm. The 3rd metal layer is patterned to form thetransmission lines within the cavity. These lines transition outof the cavity (they become buried microstrip lines) and theyare pulled up to the final metal layer to join the probe padsthrough vias. The cavities are opened in the dielectric materialby photo-lithography [7]. The build-up process includes spin-coating of liquid Probelec material, drying, exposure forpatterning, post-baking, developing and finally curing. Thethickness of the build-up layers is controlled by spin-coatingspeed, number of spin-coatings and viscosity.

The metal layer process used is semi-additive. Not all thetransmission lines in the cavities could be preserved and asseen in the figure only a few of them have survived theetchant action during the removal of the electroless platingseed layer. For the via metallization, semi-addictive methodswere applied using electroless and electrolytic plating.

Fig4. Image of the fabricated test vehicle with cavity

The following figure shows the layout of the transmissionlines and the cavities.

Fig5. Layout of the test vehicle with the cavities and theDe-embedding structures

3.4 MeasurementsThe transmission lines in the test structure were measured

using a 2 port Vector Network Analyzer from AgilentTechnologies. SOLT calibration was performed prior tomeasurements. The transmission losses in the existing lineswere measured and Fig6 shows the results of simulationmodel and measurement.

The fabricated transmission line had some constrictionsalong its length. These non-uniformities on the line haveresulted in some impedance variations and hence we can seeabout 1 dB difference between the simulation model responseand the measured values. . The measured results also showthat above 5 GHz the losses are substantial and this isattributed to the reflections at the discontinuities. Thesechanges along the line are due to some process repeatabilityissues. Further experiments are being conducted to probe intothis.

0-

Magn

tude -

(dB:)

Measurement

-/.

Se+009 2e+009 3e+O09 4e 009 5e 0D9 6e+009 7e-009 se+009 Se+QS9 1e+010

¢e4dSoffim-ei C, Frequency (Hz)

Fig6. Simulated and measured Insertion loss for thetransmission lines in the test vehicle structure (Fig 3)


*Z.5

Simulation

-2-

4. Parametric studies - Results and DiscussionIn this section the simulation results for the various design

parameters that were introduced earlier are presented anddiscussed.

When active dies are embedded in the substrate, modelingthis arrangement, and extracting the loss responses and otherpackage characteristics could become very challengingbecause the set-up requires a high degree of Chip-packagecodesign environment. Though 3D electromagnetic solversare quite complicated in terms of setting up the model,requiring a large number of parameters to be setupappropriately to obtain the correct result, we resort to thesesolvers as they support the exact reproduction of the designgeometry. The software used for generating the graphs here isANSOFT HFSS. The frequency sweep is done in the range of1-10 GHz.

In all the models discussed here the substrate used is FR4with dielectric constant 4.6 and loss tangent of 0.02 unlessmentioned. The dielectric materials used for the purposes ofpackaging (FR4, BT, BCB, Polyimide, etc) are of very lowdielectric constant as compared to the materials used fordielectric cavity based resonators. So there are no issues ofresonances with these.

4.1 Cavity DesignThis section deals with the comparison of loss responses

of surface microstrip lines and the microstrip lines inside thecavity. When using HFSS, it is common to go for waveportsto compute the loss responses of microstrip lines. When thelines are not extending across the entire length of thesubstrate, the option with waveports is to use de-embedding.But the feature of de-embedding is such that the results arevaried based on the length of the line that is de-embedded;this will not recognize a change in the type of the line. That isin this case the line is a surface microstrip in the cavity regionand outside of it, it becomes a buried line. So for the cavitybased transmission line models we have used lumped ports.

Fig7. HFSS model of cavity based substrate with traceinside the cavity

The Figs 8 and 9 show the return and insertion losses fortransmission lines on substrates of thicknesses 0.5mm (nocavity), 0.25mm (no cavity), and 0.5mm thickness with acavity of 0.25mm. The insertion loss for the line inside thecavity is the same as that with the thin substrate. The analysis

of the results for the models of transmission lines within thecavity show that the line will behave similar to a surfacemicrostrip provided the substrate height below the trace inboth cases is maintained the same.

-20.00-

30ocavity-O.5 "m-30.00- V

-40.00-

-50.00-

--=:XSI---7 A

X a

m l

I

it=.5

0. 0 20.bOFreq [GHz]

30.bO 40.bo

Fig8. Plot of the return losses (dB) for the cases with0.5mm substrate (no cavity), 0.25mm substrate (no cavity),0.5mm substrate with 0.25mm deep cavity

0.00

-2.00-

-3.00-

-4.00- _

-5.00-0. 0

I[10O.bo 20.b0

Freq [GHz]

_ 0.25 mmF-* substrate

(no cavity)

L= 0.5mmsubstratewith 0.25mmcavity

r-* 0.5mmsubstrate

X (no cavity)30.bO 40. 0

Fig9. Plot of insertion loss (dB) for 0.5mm substrate (nocavity), 0.25mm substrate (no cavity) and 0.5mm substratewith 0.25mm cavity

4.2 Influence of cavity depthThis section deals with how the cavity depth affects the

impedance of the buried transmission lines forming thesubstrate wiring. In the models analyzed here, the total heightof the substrate is maintained the same as 1.2mm. The traceheight above the ground plane is made 0.2mm (Fig.11) and0.3mm (Fig.13) with the cavity depths being varied as shownin the plots. In these cases, as we can see from the Figs. 11and, as the cavity comes closer to the buried line the returnloss deteriorates, so the trace width needs to be modified toreduce the reflection loss (Figs. 12 and 14). The trace widthchange is such as to improve the return loss better than -30 dBthrough most of the 1 - 10 GHz range. It is recommended toroute the buried traces with a distance of about 0.2mm fromthe cavity base.


-5uV.uu l

-10.001-T

-1 .00-

0

Substrate Cavity

Trace

FiglO. HFSS model of a trace passing beneath a cavity

0

-10

-20m

-.3cn

-40

-50 '

-60

2 3 4 5 6 7 8 9 1

--

-- nocavityC 0.2mm cavity

0.4mm cavity0.6mm cavity0.8mm cavity0.9mm cavity

Frequency (GHz)

Figll. Return Losses (Sil dB) for different cavity depthsfor a 1.2 mm substrate - trace is placed at 0.2mm fromground

-10

-20m'--30C',co

-40

-50-- no-cavity

0.1mm cavity-60 0.5mm cavity

Frequency (GHz) 0.6mm cavity31*0.7mm cavity+0.8mm cavity+0.3mm cavity

Figl3. Return Losses (Sil dB) for different cavity depthsfor a 1.2 mm substrate - trace is placed at 0.3mm fromground

01 2 3 4 5 6 7 8 9 10

-10

m-20

T"-30

-40

-50Frequency (GHz)

+ no-cavity,trace width -0.38mm

0.8mm cavity,trace width -0.38mm

* 0.8mm cavity,trace width -0.43mm

0

-5

-10

-15

-20

1 2 3 4 5 6 7 8 9 10

-30

-35

-401.2mm subs

-45 -0.9mm cavity trace

-50 width - 0.23mm0.9mm cavity - trace

Frequency (GHz) width - 0.26mm

Figl2. Improved return loss with trace width changed

Figl4. Improved return loss with trace width changed

4.3 Transition of transmission lines in and out of the cavityAnother challenge is when analyzing the transition from

surface to buried line. The interconnect lines in the packageshould be of 50 ohms through out. To obtain this the widths ofthe surface and buried regions of the microstrip line aredifferent. Modeling a tapered transition between two linesegments of different widths but of the same impedance valueis not very effective and the additional length added to the linein the form of the taper does not help achieve good matching.So to achieve the matching as shown in Figl5, step transitionwas used.

The figures below show the return losses for the transitionof the line from surface to buried microstrip. This is presentedfor two different substrates - FR4 and BTFR4 - Dielectric constant - 4.6, Loss tangent - 0.02BT - Dielectric constant - 3.9, Loss Tangent - 0.013Width of the surface microstrip on FR4 - 0.64mm, Width ofthe buried microstrip on FR4 - 0.54mm, Width of the surface


mco5_. 13

c

I ~~~~~~~~~~~iIi z

I,

,&.'A.PW " I

microstrip on BT- 0.725mm and Width of the buriedmicrostrip on BT - 0.63mm

-14.00-

-16.00-

-18.00-

-20.00-

0.0o02.60 4.dO 6.O0 8.0 10. 0Freq [GHz]

Figl5. Return loss (S1t, S22) for transition of surfacemicrostrip line to a buried microstrip - without line widthchange (FR4)

Frequency (GHz)-9mm Cavity width 3mm Cavity width

1mm Cavity width Trace position shifted (1)Trace position shifted (2) - No cavity - subs 0.25mm

Figl7. Return Loss for different cavity sizes and differenttrace positions within the cavity

0 116_

0

-10

-0.21 2 3 4 5 6 7 8 9 10

-20

-30

-40

-50

-60

-0.4

m -0.6

v-

c, -0.8

-1

Frequency (GHz)

Figl6. Return loss for step transition of surface microstripline to a buried microstrip

With this type of transition as can be seen from Figs 15and 16, an improvement of 20 dB is obtained in the returnloss. So, when chips are embedded in cavities this type oftransition will be required to route any of its interconnectsoutside the cavity.

-1.2

-1.4Frequency (GHz)

9mm Cavity width 3mm Cavity width1mm Cavity width Trace position shifted (1)Trace position shifted (2) No cavity - subs 0.25mm

Figl8. Insertion loss for different cavity widths anddifferent trace positions

There is not considerable variation in the return loss(Fig.17) and the insertion loss (Fig.18). So the variationsconsidered here have not shown to cause any substantialchange in the responses of the traces that necessitate anycorrective measures in the physical dimensions of the lines.

4.4 Influence of Cavity lateral dimensionsThis section is to investigate the effect of cavity width on

the transmission lines within the cavity and the effect ofdielectric wall proximity.

The figures below show the loss responses for variation ofcavity sizes (lateral dimensions) and change in the lineposition within the cavity.

4.5 Modeling the Chip first embedded dieWhen the effect of the die inside the cavity needs to be

taken into account, chip-package codesign environment isneeded. The EM solvers for package modeling do not supportdie modeling in general. The chip here is modeled as a silicontile. The substrate and the die traces, individually, are

optimized to an acceptable return loss and insertion lossvalues. This is shown in figs 21 - 24 below. When we includeboth the die and the substrate trace in the same design, there isvariation in the return loss and the impedance of the tracerunning over the buried chip (Chip first method ofembedding) as shown in figs 25 and 26.


-10

-20

-30'C,-n

-40

-50

-60

....

Figl9. HFSS model of Chip first embedded die - Side view

0

-10

m -20

u' -300-J

- -40

z -50

-60

-70Frequency (GHz)

Fig23. Return loss for trace on the embedded die

Fig2O. HFSS model of Chip first embedded die

Fig2l. Return loss for buried substrate trace (without thedie embedded in the substrate)

0

-0.02

-0.04

-0.06

_ -0.08> -0.1cn

-0.12

-0.14

-0.16

-0.18Frequency (GHz) -+-S21 (dB)

Fig24. Insertion loss for trace on the embedded die

When the die is embedded in the substrate below a buriedtrace, the comparison of their return losses (Fig. 24) showhow the die trace doesn't seem to show any appreciablechange but the substrate trace return loss deteriorates. Thiscan be more magnified when there are multiple traces gettingexcited on the die and when the trace runs above severalembedded dies. We can also see an impedance change(Fig.25) in the substrate trace. A rise time of about 500 ps wasassumed for this case.

-5

-10

m -15

a20-JE -25

w -30

-35

-40

-45

.a

Frequency

v -I S11 (dB) - DieTrace

S11 (dB) -

(GHz) Substrate Trace

Fig25. Comparison of Return Losses when both traces(substrate and on die) are excited


1 2 3 4 5 6 7 8 9 10

/ ~~~~~~~~~~~~~~~~~~~~~~~~-9

-+-S11 (dB)+S22 (dB)

0 X

1 2 3 4 5 6 7 8 9 10-0.005

-0.01X0)0

-j -0.0150-1 -0.0250)

-0.025

-0.03Frequency (GHz) -|+S21 (dB)

0

-10

m -20

tn -300-J

L -40Zz -50

-60

-70 --.-S11 (dB)

Frequency (GHz) S22 (dB)

Fig22. Insertion loss for buried substrate trace (withoutthe die embedded in the substrate)

*11 13 10

'.Il

N-

I

I&-

"In,

\Im

I m

VI.-

60

50

40

E

_- 300

N 20

10

0

0 50 100 150 200 250 300 350 400 450 500

Time (psec)

Fig26. Comparison of ZO of both traces (buried substrateline and on-die trace)

5. ConclusionsChip-last methodology of embedding chips has been

studied from an electrical perspective, in particular frominterconnect standpoint. A detailed parametric study of cavitydesigns has been carried out and the behavior of transmissionlines in cavities, effect of cavity depth and lateral dimensions,and the proximity of the transmission lines to the walls of thedielectric cavity are analyzed through simulations. The resultsshow that the transmission lines in the substrates needmodifications in their physical dimensions when cavities are

formed in the substrate. The standard substrate wiring layouthas to be customized based on the cavity size and location,since the proximity of the cavities influences the lossresponses of the transmission lines. An analysis of thebehavior of substrate transmission lines in the chip firstmethod of embedding chips is also presented to indicate thatthe issues of changes in transmission line physical parametersand routing arise in this as well. This study will be continuedto fabricate more test vehicles and look into other aspects ofoptimized chip package co-design involving embedded chipcomponents.

AcknowledgmentsThe Authors would like to thank Prof. Swaminathan for

providing access to VNA measurement set-up, AbdemanafTambawala for helping with the measurements and BoydWiedenman for fabrication guidance.

References1. Pienimaa S.K., Martin N.I.,"High-Density Packaging for

Mobile Terminals", IEEE Transactions on AdvancedPackaging, Vol. 27, No. 3, Aug. 2004, pp. 467-475.

2. Lim, S.K.,"Physical design for 3D system on package",Design & Test of Computers, IEEE, Volume 22, Issue 6,Nov.-Dec. 2005 Page(s):532 - 539

3. Wolfgang Daum, William E. Burdick Jr., and RaymondA. Fillion, "Overlay High-Density Interconnect: A Chips-First Multichip Module Technology", IEEE, April 1993

4. Steven N. Towle, Henning Braunisch, Chuan Hu, RichardD. Emery, and Gilroy J. Vandentop, Intel Corporation,"Bumpless Build-Up Layer Packaging", ASME, 2002

5. Sunohara, M, Murayama, K, Higashi, M and Shimizu, M,"Development of Interconnect Technologies forEmbedded Organic Packages", 2003 ElectronicComponents and Technology Conference, New Orleans,May 27-30 (2003) pp. 1484-1489

6. Ostmann, A.; Neumann, A.; Weser, S.; Jung, E.; Bottcher,L.; Reichl, H.,"Realization of a stackable package usingchip in polymer technology". Polymers and Adhesives inMicroelectronics and Photonics, 2nd International IEEEConference on 23-26 June 2002 Page(s):160 - 164

7. Baik-Woo Lee, Venky Sundaram, Boyd Wiedenman,Chong K Yoon, Mahadevan Iyer and Rao R Tummala,"Chip-last Embedded Active for System-On-Package(SOP)", 2007 Electronic Components and TechnologyConference, Reno, May 2007 (to be published)


-- Die Trace - ZO

Substrate Trace -ZO

Electrical Characterization DesignOptimizationof Embedded ...paper discusses the electrical design...

Documents

Transcript of Electrical Characterization DesignOptimizationof Embedded ...paper discusses the electrical design...