Measurement of the latest Tesla wafers at Udine
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Transcript of Measurement of the latest Tesla wafers at Udine
Measurement of the latest Tesla wafers at Udine
Summary by Diego Cauz
on behalf of the Udine Group
12th February 2003
2
New Tesla wafers
• We have received 4 Tesla wafers from 2 batches in February:
• 8414-14, 8414-16, 8697-04, 8697-10
Visual inspection (VIS) February
• 8414-14 4-4 4-4 4-4 4-4
correct
• 8414-16 4-4 4-4 4-4 4-4
correct
• 8697-04 4-4 4-4 4-4 4-4
correct
• 8697-10 4-4 4-4 4-4 4-4
correct
mask align (H-V) ID marking Wafer n-side L n-side R p-side L p-side R
Legenda:-“4” means that the 4th vernier (ME-PASS) has problems, specifically the passivation part.-Normal face means lines are bad-Boldface means very bad lines (as sampled on thenext two slides) or lines missing altogether.
4
Wafer 8697-104th pair, horizontal
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Wafer 8697-104th pair, vertical
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I-V on diode w/ guard ring (IVD)
• 8414-14 5002.73
• 8414-16 5005.78
• 8697-04 5005.29
• 8697-10 5003.16
Wafer Vbd (V) Iop (nA)
Iop = I(Vop)
February
Vbd = max V(I < 25 nA)
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C-V on diode w/ guard ring (CVD)
• 8414-14 100 3.6 150 2207
• 8414-16 90 3.7 150 2414
• 8697-04 105 3.7 155 2045
• 8697-10 105 3.7 155 2090
Wafer Vdep Cdep Vop (V) (pF) (V) ( cm)
30 < Vdep (V) < 120 2000 < ( cm) < 5000
Vdep = V(kink in C-V curve)
Cdep = C(Vdep)
Vop = max(150 V, Vdep + 50 V)
February
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I-V on tiles
• 8414-14 70 500 500 - 1.06 1.06 2
• 8414-16 500 500 490 1.09 1.05 1.05 3
• 8697-04 10 500 500 - 1.05 1.05 2
• 8697-10 60 500 500 - 1.04 1.07 2
Wafer Vbd (V) S good tiles
Vbd > Vop S = I(Vop) / I(Vop-50) < 2
February
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I-V on SC’s: percent yieldVbd > Vop S = I(Vop) / I(Vop-50) < 2
Wafer good/total
February
• 8414-14 5/6
• 8414-16 6/6
• 8697-04 6/6
• 8697-10 5/6
Total: 91.7 %
10
I-V on MC’s: percent yield
• 8414-14 4/4
• 8414-16 4/4
• 8697-04 4/4
• 8697-10 4/4
Vbd > Vop S = I(Vop) / I(Vop-50) < 2
Wafer good/total
February
Total: 100 %
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I-t on good tiles (ITS)
• 8414-14-02 1.1
• 8697-10-02 1.05
Wafer-tile S
S = Iend / Istart < 1.3
February
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I-V on MOS (BOX)
• 8414-14 100 8
• 8414-16 100 8
• 8697-04 100 8
• 8697-10 100 8
Vbd > 50 V
Wafer Vbd (V) delay (s)
regular delay = 2 sVbd = max V(I < 100 pA) > 50 V
February
But funny shapes in three over four cases: see next slide
0 20 40 60 80 100
0.0
10.0p
20.0p
30.0p
40.0p
50.0p
reverse Bias (V)
Cur
rent
(A)
BOX measurementTesla 8697-10, OTS 23
8-s delay
0 20 40 60 80 100
0.0
5.0p
10.0p
15.0p
20.0p
25.0p
30.0p
35.0p
reverse Bias (V)
Cur
rent
(A)
BOX measurementTesla 8697-04, OTS 23
8-s delay
The test is passed, but the shapeis not very nice
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C-V on MOS (COX)
• 8414-14 278 5.1 53.1 4
• 8414-16 273 5.5 62.6 4
• 8697-04 274 5.2 54.5 4
• 8697-10 269 5.2 53.8 4
Wafer Cox (pF) Cmin (pF) CFB (pF) VFB (V)
Cox = Cmax VFB = V(C nearest to CFB)
February
15
I-V on gate-controlled diode (IVG)
Itop = I(VFB +3 V) Ibot = I(VFB – 3 V)
• 8414-14 282 24.3 258
• 8414-16 862 53.8 808
• 8697-04 414 17.7 369
• 8697-10 482 15.0 467
Wafer Itop (pA) Ibot (pA) Iox(pA)
February
16
I-V on MOSFET (MFE)Wafer Vth p dose
(V) (1012 cm-2)
• 8414-14 30 2.95
• 8414-16 30 2.90
• 8697-04 30 2.91
• 8697-10 30 2.85
2.2 < p (1012 cm-2) < 3.5
February
Vth = max V(I < 100 nA) > 0
But funny shapes in twoe over four cases: see next slide
-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160-7.0µ
-6.0µ
-5.0µ
-4.0µ
-3.0µ
-2.0µ
-1.0µ
0.0
1.0µ
2.0µ
3.0µ
4.0µ
5.0µ
Gate Bias (V)
Sou
rce
Cur
rent
(A)
MFE measurementTesla 8414-16, MOSFET # 26
-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
-14.0µ
-12.0µ
-10.0µ
-8.0µ
-6.0µ
-4.0µ
-2.0µ
0.0
2.0µ
Gate Bias (V)
Sou
rce
Cur
rent
(A)
MFE measurementTesla 8697-10, MOSFET # 26
The test is passed, but there isthat funny spike
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Vpix-V on punch-thru structure (PUT)
Wafer Vpt (V)
• 8414-14 2.92
• 8414-16 2.08
• 8697-04 2.35
• 8697-10 2.50
Vpt = Vpix(Vop) > 3 V
February
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Planarity measurement (PLA)
• 8414-14 8.4
• 8414-16 11.8
• 8697-04 9.0
• 8697-10 25.5
February
Wafer aplanarity (m)
A < 40 m
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Conclusions
• Generally the measurements are good, with the following exceptions:– VIS: the passivation lines of the 4th verniers in
the mask alignment pad are very poorly done.– BOX, MFE: funny shape of the data.– PUT: punch-through voltage is less than 3 V,
but this can be due to the known problems we have with this measurement.