Measurements of the first ON Semiconductor production wafers at Udine Prepared by Diego Cauz on...

Measurements of the first ON Semiconductor production wafers

at Udine

Prepared by Diego Cauz

on behalf of the group of Udine

April 2004

Udine

Atlas Pixel Italia Apr 2004 2

Measurement speed-up

• Doctor Sergey Gorokhov is back in Udine since April 14th.

• He will stay for 3 months


ON-Semic wafers in Udine

• We have received 11 ON Semiconductor wafers in April:– 2 partially measured for quick shipping to AMS


Visual inspection (VIS)(1/3)

9688-07 Y-Y Y-Y Y-Y Y-Y correct





Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking









Mask Align (H-V) Wafer n-side L n-side R p-side L p-side R ID marking

Bad passivation vernier in the 4th vernier pairon all 4 monitors, both H and V, all wafers.See next slide


Many defects, probably scratcheson the tiles of 9688-07

Tile 1: 8 scr.s -93 pixTile 2: 4 scr.s -20 pixTile 3: 9 scr.s -122 pix


Wetting residue


Wafer Vernier

Passiv.

Bump openings

9688-07 bad bad*

9688-10 bad bad

9688-15 bad bad

9688-18 bad bad

9688-21 bad bad

Wafer Vernier

Passiv.

Bump openings

1201-07 bad good

1201-10 bad good

1203-11 bad good

1203-26 bad ~good

1203-27 bad ~good

1203-34 bad


*: AMS communication~: bad on limited areas


9688-10


1203-11


Thickness measurement (THI)

9688-07 251 252 -1

9688-10 254 254 0

9688-15 253 252 +1

9688-18 254 253 +1

9688-21 253 252 +1

Wafer th1 th2 (m)

220 m < th < 260 m th < 10 m

1201-07 253 254 -1

1201-10 254 253 +1

1203-11 253 253 0

1203-26 254 253 +1

1203-27 253 252 +1

1203-34 253 252 +1

Wafer th1 th2 (m)


I-V on diode w/ guard ring (IVD)

1201-07 500 0.98

1201-10 475 3.34

1203-11 480 8.74

1203-26 375 5.53

1203-27 500 4.21

1203-34 500 5.27

Wafer Vbd (V) Iop (nA)

Iop = I(Vop)Vbd = max V(I < 25 nA)

9688-07 500 2.01

9688-10 500 1.33

9688-15 500 0.99

9688-18 500 1.48

9688-21 500 2.20

Wafer Vbd (V) Iop (nA)


C-V on diode w/ guard ring (CVD) (1/2)

Vdep Cdep Vop Wafer (V) (pF) (V) ( cm)

30 < Vdep (V) < 120 2000 < ( cm) < 5000

Vdep = V(kink in C-V curve)

Cdep = C(Vdep)

Vop = max(150 V, Vdep + 50 V)

9688-07 115 4 165 1850

9688-10 95 4.7 150 2290

9688-15 95 4.8 150 2250

9688-18 130 4.0 180 1660

9688-21 105 3.3 155 2040

Measurementvery noisy. One cablefound defective.Large incertitudeon Vdep.


C-V on diode w/ guard ring (CVD) (2/2) Vdep Cdep Vop

Wafer (V) (pF) (V) ( cm)

30 < Vdep (V) < 120 2000 < ( cm) < 5000

Vdep = V(kink in C-V curve)

Cdep = C(Vdep)

Vop = max(150 V, Vdep + 50 V)

1201-07 105 3.8 155 2050

1201-10 70 4.6 150 3100

1203-11 120 4.8 170 1800

1203-26 105 3.6 155 2050

1203-27 90 4.9 150 2380

1203-34 40 4.3 150 5350

See next slide


I-V on tiles (1/2) Wafer Vop (V) Vbd (V) S good tiles

Vbd > Vop S = I(Vop) / I(Vop-50) < 2

9688-07 165 500 385 80 1.13 1.44 - 1-2-x

9688-10 150 85 500 230 - 1.21 4.08 x-2-x

9688-15 150 500 75 500 1.34 - 1.17 1-x-3

9688-18 180 500 500 75 1.15 1.15 - 1-2-x

9688-21 155 295 500 70 1.80 1.12 - 1-2-x


I-V on tiles (2/2) Wafer Vop (V) Vbd (V) S good tiles


1201-07 155 500 500 75 1.23 1.23 - 1-2-x

1201-10 150 455 500 70 1.15 1.15 - 1-2-x

1203-11 170 310 75 205 1.18 - 1.71 1-x-3

1203-26 155 265 310 70 1.77 1.21 - 1-2-x

1203-27 150 145 345 85 25.7 1.13 - x-x-x

1203-34 150 170 220 205 7.27 1.63 3.21 x-2-x

Bad I-t


I-V on SC’s


Wafer good/total

Only half of the SC’s are being measured

9688-07 3/3

9688-10 3/3

9688-15 3/3

9688-18 3/3

9688-21 3/3

1201-07 3/3

1201-10 3/3

1203-11 3/4

1203-26 3/5

1203-27 3/3

1203-34 3/4

Wafer good/total


I-V on MC’s


Wafer good/total

Only half of the MC’s are being measured

9688-07 2/2

9688-10 2/2

9688-15 2/2

9688-18 2/2

9688-21 2/3

1201-07 2/2

1201-10 2/2

1203-11 2/2

1203-26 2/3

1203-27 2/2

1203-34 2/2

Wafer good/total


I-t on good tiles (ITS)

Wafer-tile S

S = Iend / Istart < 1.3

9688-07-01 1.06

1201-10-02 1.01

1203-27-02 bad

1203-26-02 1.05


I-V on MOS (BOX)

9688-07 100

9688-10 100

Wafer Vbd (V)

delay = 4 s

Vbd = max V(I < 100 pA) > 50 V

1201-07 100

1201-10 96

1203-11 80

1203-34 100

Wafer Vbd (V)


C-V on MOS (COX)Wafer Cox (pF) Cmin (pF) CFB (pF) VFB (V)

Cox = Cmax VFB = V(C nearest to CFB)

9688-07 273 4.8 56.8 16

9688-10 278 8.0 52.3 8

1201-07 265 7.3 54.1 4

1201-10 267 5.7 46.1 12

1203-11 273 9.9 57.5 14

1203-34 269 8.5 36.4 4.5


I-V on gate-controlled diode (IVG)

Itop = I(VFB +3 V) Ibot = I(VFB – 3 V)

Wafer Itop (pA) Ibot (pA) Iox(pA)

9688-07 883 14 869

9688-10 218 26 192

1201-07 414 22 392

1201-10 516 18 498

1203-11 789 55 734

1203-34 269 35 234

-10 0 10 20 30 40 50 60

0.0

50.0p

100.0p

150.0p

200.0p

250.0p

300.0p

Bias (V)

corr

ect

ed C

ap

acita

nce

(F

)COX measurementON Semic 9688-07, OTS 22

inverted bias

-2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

0.0

200.0p

400.0p

600.0p

800.0p

1.0n

Vgate (V)

Iox

(A)

IVg measurementON Semic 9688-07, GCD on str 22temperature normalized

pos 2_1

VFB is around 16 V

VFB is around 4 V

COX, IVG discrepancy


I-Vg on MOSFET (MFE)

Wafer Vth (V) p-dose (x 1012 cm-2)

9688-07 28 2.7

9688-10 26 2.6

1201-07 26 2.4

1201-10 26 2.5

1203-11 26 2.5

1203-34 bad -

2.2 < p (1012 cm-2) < 3.5 Vth = max V(I < 100 nA) > 0

Vth is usually good,but I beyond thresholdis very low.See next slide.


-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160

0.0

20.0n

40.0n

60.0n

Gate Bias (V)

Sou

rce

Cur

rent

(A

)

MFE measurementON Semic 1201-07

MOSFET # 26 lower


Vpix-V on punch-thru structure (PUT)

9688-10 1.64

9688-15 2.09

9688-18 3.45

9688-21 2.53

Wafer Vpt (V)

Vpt >3 V

1201-07 1.88

1201-10 1.75

1203-11 bad

1203-26 2.37

1203-27 2.17

Wafer Vpt (V)


Conclusions• 11 wafers are being measured

– Missing measurements: VIS, PLA– Some measurements need to be done again

• Wafer quality :– bad passivation in the mask alignment monitor for all

4th vernier pair, wafers 9688-07, 1203-34– Many scratches on the tiles of 9688-07– Bad bump pads for 9688-10 (and 9688-07)– wafer 1203-34 does not pass MFE test– wafer 1203-34, 9688-10 have only one good tile– wafer 1203-27 has no good tile– Almost all wafers do not pass PUT test


Wafer

acceptance

reasons

9688-07* BO,

9688-10 BO,PUT,1GT

9688-15 BO,PUT

9688-18 BO,

9688-21 BO,PUT

Wafer

acceptance

reasons

1201-07 PUT

1201-10 PUT

1203-11 ,PUT

1203-26 PUT

1203-27 It,PUT,0GT

1203-34* ,1GT

Conclusions


Project Progress Tracking

• Dortmund 145/250 58%

• New Mexico 0/250 0%

• Prague 250/250 100%

• Udine 212/250 84%

• This tool is not trustable.

Laboratory tiles meas/total percent


Tile pool

• In reality the 4 labs have received a total of 1121 tiles, 1060 of which have been accepted:– Dortmund: 250

– NM: 265

– Prague: 250

– Udine: 212

• The missing tiles are to be finished measuring by Udine (14 wafers) and Dortmund.

Measurements of the first ON Semiconductor production wafers at Udine Prepared by Diego Cauz on...

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