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UG-PCI10605-2014.08.18

User Guide

IP Compiler for PCI Express

Document publication date: August 2014

IP Compiler for PCI Express User Guide

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IP Compiler for PCI Express User Guide August 2014 Altera Corporation

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respectiveholders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordancewith Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility orliability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Alteracustomers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products orservices.

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August 2014 Altera Corporation

August 2014

1. Datasheet

This document describes the Altera IP Compiler for PCI Express IP core. PCI Express is a high-performance interconnect protocol for use in a variety of applications including network adapters, storage area networks, embedded controllers, graphic accelerator boards, and audio-video products. The PCI Express protocol is software backwards-compatible with the earlier PCI and PCI-X protocols, but is significantly different from its predecessors. It is a packet-based, serial, point-to-point interconnect between two devices. The performance is scalable based on the number of lanes and the generation that is implemented. Altera offers both endpoints and root ports that are compliant with PCI Express Base Specification 1.0a or 1.1 for Gen1 and PCI Express Base Specification 2.0 for Gen1 or Gen2. Both endpoints and root ports can be implemented as a configurable hard IP block rather than programmable logic, saving significant FPGA resources. The IP Compiler for PCI Express is available in 1, 2, 4, and 8 configurations. Table 11 shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 IP Compilers for PCI Express for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5 giga-transfers per second for Gen2. Because the PCI Express protocol uses 8B/10B encoding, there is a 20% overhead which is included in the figures in Table 11. Table 11 provides bandwidths for a single TX or RX channel, so that the numbers in Table 11 would be doubled for duplex operation.

f Refer to the PCI Express High Performance Reference Design for bandwidth numbers for the hard IP implementation in Stratix IV GX and Arria II GX devices.

FeaturesAlteras IP Compiler for PCI Express offers extensive support across multiple device families. It supports the following key features:

Hard IP implementationPCI Express Base Specification 1.1 or 2.0. The PCI Express protocol stack including the transaction, data link, and physical layers is hardened in the device.

Soft IP implementation:

PCI Express Base Specification 1.0a or 1.1.

Many device families supported. Refer to Table 14.

The PCI Express protocol stack including transaction, data link, and physical layer is implemented using FPGA fabric logic elements

Table 11. IP Compiler for PCI Express Throughput

Link Width

1 2 4 8

PCI Express Gen1 Gbps (1.x compliant) 2 4 8 16

PCI Express Gen2 Gbps (2.0 compliant) 4 8 16 32

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12 Chapter 1: DatasheetFeatures

Feature rich:

Support for 1, 2, 4, and 8 configurations. You can select the 2 lane configuration for the Cyclone IV GX without down configuring a 4 configuration.

Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

Extensive maximum payload size support:

Stratix IV GX hard IPUp to 2 KBytes (128, 256, 512, 1,024, or 2,048 bytes).

Arria II GX, Arria II GZ, and Cyclone IV GX hard IPUp to 256 bytes (128 or 256 bytes).

Soft IP ImplementationsUp to 2 KBytes (128, 256, 512, 1,024, or 2,048 bytes).

Easy to use:

Easy parameterization.

Substantial on-chip resource savings and guaranteed timing closure using the IP Compiler for PCI Express hard IP implementation.

Easy adoption with no license requirement for the hard IP implementation.

Example designs to get started.

Qsys support.

Stratix V support is provided by the Stratix V Hard IP for PCI Express.

Stratix V support is not available with the IP Compiler for PCI Express.

The Stratix V Hard IP for PCI Express is documented in the Stratix V Hard IP for PCI Express User Guide.

Different features are available for the soft and hard IP implementations and for the three possible design flows. Table 12 outlines these different features.

Table 12. IP Compiler for PCI Express Features (Part 1 of 2)

FeatureHard IP Soft IP

MegaCore License Free Required

Root port Not supported Not supported

Gen1 1, 2, 4, 8 1, 4

Gen2 1, 4 No

Avalon Memory-Mapped (Avalon-MM) Interface Supported Supported

64-bit Avalon Streaming (Avalon-ST) Interface Not supported Not supported

128-bit Avalon-ST Interface Not supported Not supported

Descriptor/Data Interface (1) Not supported Not supported

Legacy Endpoint Not supported Not supported

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

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Chapter 1: Datasheet 13Release Information

Release InformationTable 13 provides information about this release of the IP Compiler for PCI Express.

Transaction layer packet type (TLP) (2)

Memory read request

Memory write request

Completion with or without data

Memory read request

Memory write request

Completion with or without data

Maximum payload size 128256 bytes 128256 bytes

Number of virtual channels 1 1

Reordering of outoforder completions (transparent to the application layer) Supported Supported

Requests that cross 4 KByte address boundary (transparent to the application layer) Supported Supported

Number of tags supported for non-posted requests 16 16

ECRC forwarding on RX and TX Not supported Not supported

MSI-X Not supported Not supported

Notes to Table 12:

(1) Not recommended for new designs.(2) Refer to Appendix A, Transaction Layer Packet (TLP) Header Formats for the layout of TLP headers.

Table 12. IP Compiler for PCI Express Features (Part 2 of 2)

FeatureHard IP Soft IP

Table 13. IP Compiler for PCI Express Release Information

Item Description

Version 14.0

Release Date June 2014

Ordering Codes

IP-PCIE/1IP-PCIE/4IP-PCIE/8

IP-AGX-PCIE/1IP-AGX-PCIE/4

No ordering code is required for the hard IP implementation.

Product IDs

Hard IP Implementation

Soft IP Implementation

FFFF

100A9400AA800AB

Vendor ID

Hard IP Implementation

Soft IP Implementation

6AF7

6A66

August 2014 Altera Corporation IP Compiler for PCI Express

14 Chapter 1: DatasheetDevice Family Support

Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with IP core versions older than one release.Table 14 shows the level of support offered by the IP Compiler for PCI Express for each Altera device family.

Device Family Support

f In the Quartus II 11.0 release, support for Stratix V devices is offered with the Stratix V Hard IP for PCI Express, and not with the IP Compiler for PCI Express. For more information, refer to the Stratix V Hard IP for PCI Express User Guide .

General DescriptionThe IP Compiler for PCI Express generates customized variations you use to design PCI Express root ports or endpoints, including non-transparent bridges, or truly unique designs combining multiple IP Compiler for PCI Express variations in a single Altera device. The IP Compiler for PCI Express implements all required and most optional features of the PCI Express specification for the transaction, data link, and physical layers.

Table 14. Device Family Support

Device Family Support (1)

Arria II GX Final

Arria II GZ Final

Cyclone IV GX Final

Stratix IV E, GX Final

Stratix IV GT Final

Other device families No support

Note to Table 14:

(1) Refer to the What's New for IP in Quartus II page for device support level information.

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Chapter 1: Data