PCI Express 2.0 (5.0 PCI Express 2.0 (5.0 Gb/s) Electrical ...

PCI Express 2.0 (5.0 Gb/s) Electrical Standard [optional]

RPT119 (v1.0) June 18, 2009 [optional]

Virtex-5 FPGA RocketIO GTX Transceiver Characterization ReportPCI Express 2.0 (5.0 Gb/s) Electrical Standard

RPT119 (v1.0) June 18, 2009

PCI Express 2.0 Electrical Standard Report www.xilinx.com RPT119 (v1.0) June 18, 2009

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RPT119 (v1.0) June 18, 2009 www.xilinx.com PCI Express 2.0 Electrical Standard Report

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

06/18/09 1.0 Initial Xilinx Release.


PCI Express 2.0 Electrical Standard Report www.xilinx.com RPT119 (v1.0) June 18, 2009


PCI Express 2.0 Electrical Standard Report www.xilinx.com 5RPT119 (v1.0) June 18, 2009

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

PCI Express 2.0 (5.0 Gb/s) Electrical Standard Characterization ReportIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Transceiver Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Electrical Characterization Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Transmitter Output Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Transmitter Output Jitter and Peak Differential Output Voltage . . . . . . . . . . . . . . . . . 11Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Transmitter Differential and Common Mode Return Loss . . . . . . . . . . . . . . . . . . . . . . 16Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Receiver Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Receiver Differential and Common Mode Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . 22Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table of Contents


6 www.xilinx.com PCI Express 2.0 Electrical Standard ReportRPT119 (v1.0) June 18, 2009



PCI Express 2.0 (5.0 Gb/s) Electrical Standard Characterization Report

IntroductionThis characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against revision 2.0 PCI Express® specifications published in the PCI Express Base Specification Revision 2.0 and the PCI Express Card Electromechanical Specification Revision 2.0. Testing is based on a line rate of 5.0 Gb/s across voltage, temperature, and worst-case transceiver performance corners.

This report includes test results for the PCI Express 2.0 specifications listed here:

• Transmitter Unit Interval

• Transmitter Output Jitter

• Transmitter Peak Differential Output Voltage

• Transmitter Differential and Common Mode Return Loss

• Receiver Input Jitter Tolerance

• Receiver Differential and Common Mode Return Loss

Test ConditionsTable 1 and Table 2 show the supply voltage and temperature conditions used in the PCI Express specification tests, respectively.

Table 1: Supply Voltage Test Conditions

Condition MGTAVCC (V) MGTAVCCPLL (V) MGTAVTTRX (V) MGTAVTTTX (V)

VMIN 0.95 0.95 1.14 1.14

VMAX 1.05 1.05 1.26 1.26

Notes: 1. Other FPGA voltages stay at their nominal values.

Table 2: Temperature Test Conditions

Condition Temperature (°C)

T-40 –40

T0 0

T100 100



Transceiver Selection

Transceiver SelectionTransceiver channels are chosen to represent a mixture of transmitters and receivers having worst-case and typical performance based on volume generic characterization data. Transceivers with the absolute worst-case transmitter output jitter and receiver jitter tolerance are selected from the corner silicon used during generic volume characterization. The histograms in this characterization report do not show a true statistical representation that is normally present in a random (or even typical) population. The histograms are skewed toward the worst-case performance because of the transceiver selection and are not representative of the typical production silicon.

Summary of ResultsTable 3 shows a comparison of the tested GTX transceiver performance against the revision 2.0 PCI Express specifications. The data reported in Table 3 represents values obtained under worst-case voltage, temperature, and performance corner conditions.

Electrical Characterization DetailsThis section describes the test methodology used to characterize the GTX transceiver performance against the revision 2.0 PCI Express specifications. The results for each test are summarized in Table 3. The GTX transceiver is configured using version 1.5 of the

Table 3: Revision 2.0 PCI Express Specification Characterization Summary of Results

Test Parameter SpecificationWorst-CaseTest Result

Units Compliant

Transmitter Unit Interval Min 199.94 200.01 ps Yes

Max 200.06 200.01 ps Yes

Transmitter Output Eye Width Eye Width(1) 123 145.86 ps Yes

Transmitter Output Deterministic Jitter DJ(1) 57 17.34 ps Yes

Transmitter Output Total Jitter TJ(1,2) 77 54.14 ps Yes

Transmitter Peak Differential Output Voltage

Min 380 Programmable mV Yes

Max 1200 Programmable mV Yes

Transmitter Differential Return Loss Frequency Profile See Figure 12, page 18 dB Yes

Transmitter Common Mode Return Loss Frequency Profile See Figure 13, page 18 dB Yes

Receiver Input Jitter Tolerance TJ(not including SJ)

SeeTable 10, page 20(3)

SeeTable 10

UI Yes

SJ @ 22.8 MHz(2) Not Defined 0.266 UI Yes

Receiver Differential Input Return Loss Frequency Profile See Figure 18, page 23 dB Yes

Receiver Common Mode Input Loss Frequency Profile See Figure 19, page 23 dB Yes

Notes: 1. With crosstalk.2. BER = 10-12.3. Jitter components and amplitude settings from the table called “5.0 GT/s Limits for Common Refclk Rx Architecture” in the PCI

Express Base Specification Revision 2.0.



Electrical Characterization Details

Virtex-5 FPGA RocketIO GTX Transceiver Wizard, including attribute settings. GTX transceiver attribute settings that differ from the GTX Transceiver Wizard default settings are identified in the “Test Setup and Conditions” table for each test.

Table 4 shows the PLL settings used in the characterization.

Transmitter Output Eye

Test Methodology

While operating at nominal voltage and room temperature, the device under test is configured to transmit the PCI Express specification compliance pattern on each of the TX data pins. The resulting eye is captured using an Agilent Infiniium DSA91304A Digital Signal Analyzer. The add-in card setup, as shown in Figure 1, is used for measuring the output eye. This corresponds to the Add-In Card Transmitter Path Compliance Eye Diagrams at 5.0 GT/s from the PCI Express Card Electromechanical Specification (CEM) Revision 2.0 specification.

Table 4: 5.0 Gb/s Line Rate PLL Settings

Data Rate(Gb/s)

PLL Frequency(Gb/s)

REFCLKFrequency

(MHz)PLL_DIVSEL_REF

PLL_DIVSEL_FBand DIV

PLL_TXDIVSEL_OUTand PLL_RXDIVSEL_OUT

5.0 2.5 250 1 2 x 5 = 10 1




Table 5 defines the test setup and conditions for the transmitter output eye.

X-Ref Target - Figure 1SMA M/F INNER

Figure 1: Transmitter Output Jitter and Peak Differential Output Voltage Test Setup Block Diagram

Aux Out Aux Trig Channel 1 Channel 2 Channel 3 Channel 4

Agilent Infiniium DSA91304A Digital Signal Analyzer 13 GHz - Gsa/s Agilent E3631A 0-6V, 5A / 0-±25V, 1A

Agilent E3631A 0-6V, 5A / 0-±25V, 1A

ML523 Virtex-5 FX70TFPGA Board

ICS874003AG-02-EVB

PCI Express Gen-2 ComplianceBase Board R2.0

Legend

Display

Display

Virtex-5FX70TFPGA

FF1136ICS

874003BG-05

DIP

SW

ITC

H

FunctionMiscellaneous

Buttons

1 2 3 4

On/Off

On/Off 6V

Adjust

Voltage/Current

±25VCOM+ – + –

Gnd

Display

Function

On/Off

DC BlocksSMA Matched Pair Cables From PCIe Load Board TX to ScopeSMA Matched Pair Cables From PCIe SMA Board RX to GTX TXSMA Matched Pair Cables From PCIe SMA Board CLK to ICS CLK

Cable For 1.2 V PSCable For 3.3 V PS

Cable For 1.0 V PSSMA Matched Pair Cables From ICS CLK to GTX CLK

Cable For Ground PS

6V

Adjust

Voltage/Current

±25VCOM

RXN

nQA0

QA0

nCLK

TXP

RXN

LAN

E0

SMA to PCIeAdapter Card

TXN

CLKP

RXP

TXP

CLKN

LANE0

TXN

VCC 3.3V

VCCO 3.3V

GND

VEE

CLK

CLKN

RPT119_01_043009

MGTAVCC 1.0V

AVCCPLL 1.0V

AVTTTX 1.2V

AVTTRX 1.2V

GND

CLKP

RXP

TXN TXP

+ – + –

Table 5: Transmitter Output Eye Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent Infiniium DSA91304A Digital Signal Analyzer

TX Coupling AC coupled using DC blocks

Voltage Nominal

Temperature Room Temperature

Pattern Compliant with the PCI Express specification, revision 2.0




Test Results

Figure 2 shows the transmitter output eye at 5.0 Gb/s.

Transmitter Output Jitter and Peak Differential Output Voltage

Test Methodology

Transmitter output jitter and the peak differential output voltage are measured using the test setup shown in Figure 1. An Agilent Infiniium DSA91304A Digital Signal Analyzer measures the transmitter output jitter using the methodology defined in the PCI-SIG® document PCI Express 2.0 CEM Signal Quality Testing for Add-in Cards using Agilent DSO91304A, and DSA91304A 13 GHz Real-Time Oscilloscopes. The version of the SIGtest software used is 3.1.9.

Load Boards • ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136)

• SMA to PCIe® Adapter Card• PCIe Compliance Base Board, Version 2.0• ICS874003BG-05 evaluation board

TX Amplitude andPre-Emphasis

RocketIO GTX Transceiver Attributes:

• TXDIFFCTRL = 011• TXPREEMPHASIS = 0010

REFCLK 250 MHz sourced from the PCIe Compliance Base Board, Version 2.0 and the ICS874003BG-05 PCI Express Jitter Attenuator IC

Table 5: Transmitter Output Eye Test Setup and Conditions (Cont’d)

Parameter Value

X-Ref Target - Figure 2

Figure 2: Transmitter Output Eye (5.0 Gb/s with 250 MHz REFCLK)

RPT119_02_043009




An SMA to PCIe Adapter Card (Figure 3) is used in order to connect the ML523 board to the PCIe Compliance Base Board.

Table 6 defines the test setup and conditions for the transmitter output jitter and peak differential output voltage tests.


Figure 3: ML523 Board with an SMA to PCIe Adapter Card

Table 6: Transmitter Output Jitter and Peak Differential Output Voltage Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent Infiniium DSA91304A Digital Signal Analyzer

TX Coupling AC coupled using DC blocks

Voltage VMIN, VMAX

Temperature T-40, T0, T100

Pattern Compliant with the PCI Express specification, revision 2.0

BER 10-12

Load Boards • ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136)

• SMA to PCIe Adapter Card• PCIe Compliance Base Board, Version 2.0• ICS874003BG-05 evaluation board

TX Amplitude/Pre-Emphasis RocketIO GTX Transceiver Attributes:

• TXDIFFCTRL = 011

• TXBUFDIFFCTRL = 101

• TXPREEMPHASIS = 0010

REFCLK 250 MHz sourced from the PCIe Compliance Base Board, Version 2.0 and the ICS874003BG-05

RPT119_03_040709




Test Results

Figure 4, Figure 5, and Figure 6 show histograms for the output jitter test results. Table 7 summarizes the maximum and minimum test result values.X-Ref Target - Figure 4

Figure 4: Transmitter Eye Width


Figure 5: Transmitter Deterministic Jitter

16

14

12

10

8

6

4

2

0

121 125 129 133 137 141 145 149 153 157

Eye Width

161

Eye Width (ps)

Num

ber

of D

ata

poin

ts

RPT119_04_050809

0

2

4

6

8

10

12

14

16

18

7.00

9.00

11.0

013

.00

15.0

017

.00

19.0

021

.00

23.0

025

.00

27.0

029

.00

31.0

033

.00

35.0

037

.00

39.0

041

.00

43.0

045

.00

47.0

049

.00

51.0

053

.00

55.0

057

.00

59.0

0

DJ

DJ (ps)

Num

ber

of D

ata

Poi

nts

RPT119_05_050809




The revision 2.0 PCI Express Card Electromechanical Specification defines the transmitter peak differential output voltage between 380 mV to 1200 mV. Figure 7 shows the transmitter peak differential output voltage histogram. Table 8 summarizes the maximum and minimum test result values.


Figure 6: Transmitter Output Total Jitter (BER = 10-12)

Table 7: Transmitter Output Jitter Test Results

Parameter Min Max Units

Transmitter Output Eye Width 145.86 158.96 ps

Transmitter Output Deterministic Jitter 7.66 17.34 ps

Transmitter Output Total Jitter (BER = 10-12) 41.04 54.14 ps


Figure 7: Transmitter Peak Differential Output Voltage

Table 8: Transmitter Peak Voltage Output

Parameter Min Max Units

Transmitter Peak Differential Output Voltage (TXDIFFCTRL = 011, TXPREEMPHASIS = 0010)

718.3 947.2 mV

0

2

4

6

8

10

12

14

16

41.0

0

43.0

0

45.0

0

47.0

0

49.0

0

51.0

0

53.0

0

55.0

0

57.0

0

59.0

0

61.0

0

63.0

0

65.0

0

67.0

0

69.0

0

71.0

0

73.0

0

75.0

0

77.0

0

79.0

0

TJ (BER = 10-12) (ps)

Num

ber

of D

ata

Poi

nts

RPT119_06_050809

TJ (BER = 10-12)

0

5

10

15

20

25

400

450

500

550

600

650

700

750

800

850

900

950

1000

1050

1100

1150

1200

Peak DifferentialOutput Voltage

Peak Differential Output Voltage (mV)

Num

ber

of D

ata

Poi

nts

RPT119_07_050809




Figure 8 shows the non-transition eye signal diagram from the SIGtest software.

Figure 9 shows the transition eye signal diagram from the SIGtest software.


Figure 8: Transmitter Non-Transition Eye Signal Diagram from SIGTest


Figure 9: Transmitter Transition Eye Signal Diagram from SIGtest

RPT119_08_040809Unit Intervals

Diff

eren

tial S

igna

l (V

)

-0.2-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

RPT119_09_040809Unit Intervals

Diff

eren

tial S

igna

l (V

)

-0.2-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2




Figure 10 shows the SIGtest results displayed on the Agilent Infiniium DSA91304A Digital Signal Analyzer.

Transmitter Differential and Common Mode Return Loss

Test Methodology

The PCI Express Base Specification Revision 2.0 defines the differential return loss measurement as –10 dB or better from 50 MHz to 1.25 GHz, and as –8 dB or better from 1.25 GHz to 2.5 GHz. Differential return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. This output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100Ω.

The transmit common mode return loss measurement is defined as –6 dB or better from 50 MHz to 2.5 GHz.

The Vector Network Analyzer (VNA) interfaces to the host PC through a GPIB interface. After the measurement parameters are set, calibration begins. Four cables are included in the calibration process. VNA measurements are independent of voltage and are accurate up to 11 GHz. A digital multimeter (DVM) confirms the differential resistance is 100Ω before the measurement.

Table 9 defines the test setup and conditions.


Figure 10: Transmitter SIGtest Results

RPT119_10_040709




Figure 11 shows the setup for the return loss measurement.

Test Results

Figure 12 shows the transmitter differential output return loss measurement.

Table 9: Transmitter Differential and Common Mode Return Loss Test Setup and Conditions

Parameter Value

Measurement Instrument HP8720ES Vector Network Analyzer

TX Coupling/Termination Differential, DC coupled into 50Ω to GND

Voltage Typical voltage

Temperature Room temperature

Frequency Sweep 50 MHz to 11 GHz (10 MHz steps)

Test Fixture ML523 test fixture with 1-inch board trace using a low-profile ZIF socket

REFCLK Not Used

Source Power 0 dBm

Averaging Calibration 1

Intermediate Frequency (IF) 100 Hz


Figure 11: Return Loss Test Setup Block Diagram

20 GHz Vector

NetworkAnalyzer

RX - Pair

TX - Pair

8720ES

GP

IB

port 1

port 2

port 3

port 4

2 Ft. Green Cable 5Vswitch

OFF ON5VDCPlug+

+VCCINT

1V

+VCCO

+VCCAUX

2.5V

2.5V

-GND

50MHz

126

126

122

122

118118

RX0

TX0TX1 RX1116

116

114

114

RX1

TX1

RX0

112RX1

TX1112RX0

TX0

DIFFDIFF

120

120

124

124

OZTEC Socket

FF1136

126

122

118

124

120

116

112

114

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

SerialGPIBUSB

PCChipScope

Tool

34401ADVM

com

I

V+ GP

IB

TE: 1-inch 114ML523

E2

E1

RPT119_11_040809

RX0TX0

RX1TX1

RX1TX1

RX1TX1

TX0

TX0

RX0

TX0RX0

TX1RX1

TX0RX0

RX1

TX1 RX0 TX0 X0Y0

X0Y1

X0Y2

X0Y3

X0Y4

X0Y5

X0Y6

X0Y7




Figure 13 shows the transmitter common mode output return loss measurement.

Receiver Input Jitter Tolerance

Test Methodology

The receiver input jitter tolerance as defined by the PCI Express Base Specification Revision 2.0 is measured using the test setup shown in Figure 14. The BERTScope BSA75B-PCIE generates a CJTPAT pattern with different components of Random Jitter (RJ) and Deterministic Jitter (DJ) per the table called “5.0 GT/s Limits for Common Refclk Rx Architecture” from the PCI Express Base Specification Revision 2.0. Part of the DJ in the form of ISI is added using 15 inches of FR4 through the Xilinx Quad Serial Loop Board. Sinusoidal Jitter (S J) is swept from 1 MHz to 80 MHz. The CJTPAT pattern is used in this test because it is a more strenuous specification test than the compliance test pattern. The GTX transceiver under test recovers the data and transmits the pattern back to the Error Detector input of the BERTScope, where bit errors are measured. The test setup is synchronous, with no PPM offset between the BERTScope data generator and the reference clock provided to the GTX transceiver under test.


Figure 12: Transmitter Differential Return Loss Measurement


Figure 13: Transmitter Common Mode Return Loss Measurement

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0 0.5 1.0 2.01.5 2.5

Frequency (GHz)

Loss

(dB

)

RPT119_12_051109

TXSDD11PCIe 2.0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0 0.5 1.0 2.01.5 2.5

Frequency (GHz)

Loss

(dB

)

RPT119_13_051109

TXSCC11PCIe 2.0





Figure 14: Receiver Jitter Tolerance Setup Block Diagram

TriggerErrorBlankTTLLevel

Error DetectorMarkerTTLLevel

TriggerSubrateClock

HFJitter

Pattern Generator

EXTClock

USBPort

ClockOutput

+

–

ClockInput

+

–

DataOutput

+

–

DataInput

+

–

BERTScope SAgilent E3631A 0-6V, 5A / 0-±25V, 1A

Agilent E3631A 0-6V, 5A / 0-±25V, 1A

ML523 Virtex-5 FX70TFPGA Board

Legend

Display

Display

Virtex-5FX70TFPGA

FF1136Xilinx

Quad SerialLoop RevB

Function

BSA75B-PCIE7.5 Gb/s PCIe

On/Off 6V

Adjust

Voltage/Current

±25VCOM+ – + –

GndDisplay

Function

On/Off

DC BlocksSMA Matched Pair Cables For GTX ReceiverSMA Matched Pair Cables For GTX TransmitterSMA Matched Pair Cables For GTX Clocks

Cable For 1.0 V PowerCable For 1.2 V Power

Cable For BERTScope Clock Input

Cable For Ground

6V

Adjust

Voltage/Current

±25VCOM

TXP

CLKN

RPT119_14_043009

MGTAVCC 1.0V

AVCCPLL 1.0V

AVTTTX 1.2V

AVTTRX 1.2V

GND

CLKPTXN

RXP RXN

+ – + –




Figure 15 shows the jitter injected to the GTX transceiver under test. In addition to all the jitter components added and amplitude settings applied as defined in Table 10, SJ is applied during the test.

Table 10 defines the test setup and conditions for receiver jitter tolerance.


Figure 15: Receiver Jitter Tolerance Setup - Eye Diagram of Pattern with RJ and DJ Injected

RPT119_15_040709

Table 10: Receiver Jitter Tolerance Test Setup and Conditions

Parameter Value

Measurement Instrument BERTScope S BSA75B-PCIE, 7.5 Gb/s

RX Coupling AC coupled using DC blocks

Voltage VMIN, VMAX

Temperature T-40, T0, T100

Pattern CJTPAT

Injected Jitter and Amplitude Settings Sum of the following:

• High Frequency RJ (1.5-100 MHz RMS jitter) = 3.4 ps RMS• Low Frequency RJ (below 1.5 MHz RMS jitter) = 4.2 ps RMS• High Frequency DJ = 88 ps• Low Frequency DJ (33 kHz REFCLK residual) = 75 ps• Eye width = 120 ps• Minimum/maximum pulse voltage ratio = 5• Receive eye voltage opening = 120 mVPP differential• Common mode noise from RX = 300 mVPP• SJ = Tested to Failure, Frequency Sweep = 1 MHz to 80 MHz

BER 10-12 (measured at 10-9, extrapolated to 10-12)




Test Results

Figure 16 shows the receiver jitter tolerance SJ sweep. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10.

Load Board • ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136)

• Xilinx Quad Serial Loop Board

Attributes RocketIO GTX Transceiver Attributes:

• PMA_CDR_SCAN = 27’h6404037

• PMA_RX_CFG = 25’h0F44088

• RXEQMIX = 2’b10

• DFE Disabled ♦ DFECLKDLYADJ = 0♦ DFETAP1[4:0] = 0♦ DFETAP2[4:0] = 0♦ DFETAP3[4:0] = 0♦ DFETAP4[4:0] = 0♦ DFE_CAL_TIME[4:0] = 5'b00110

♦ DFE_CFG[9:0] = 10’b1001111011

REFCLK 250 MHz sourced from the BERTScope

Table 10: Receiver Jitter Tolerance Test Setup and Conditions (Cont’d)

Parameter Value


Figure 16: Receiver Jitter Tolerance SJ Sweep Test Results (CJTPAT, BER = 10-12)

0.01

0.1

1

10

100

1000

1,000 10,000 100,000 10,000,0001,000,000 100,000,000

Frequency (Hz)

Am

plitu

de (

UI)

RPT119_16_051109




Figure 17 shows the SJ at 22.8 MHz. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10.

Table 11 shows the minimum receiver SJ tolerance for 22.8 MHz. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10.

Receiver Differential and Common Mode Return Loss

Test Methodology

The receiver input differential and common mode return loss specification and setup are the same as “Transmitter Differential and Common Mode Return Loss,” page 16.

Table 12 defines the test setup and conditions.


Figure 17: Receiver Sinusoidal Jitter Tolerance at 22.8 MHz Test Results (CJTPAT, BER = 10-12)

Table 11: Receiver Jitter Tolerance Test Results

Parameter Test Condition BER Min SJ Tolerance Units

Receiver Jitter Tolerance SJ at 22.8 MHz 10-12 0.266 UI

12

10

8

6

4

2

0

0.260 0.280 0.300 0.320 0.340 0.360 0.380 0.400 0.420 0.440

SJ at 22.8 MHz

0.460

SJ at 22.8 MHz (UI)

Num

ber

of D

ata

poin

ts

RPT119_17_050909

Table 12: Receiver Differential and Common Mode Input Return Loss Test Setup and Conditions

Parameter Value

Measurement Instrument HP8720ES Vector Network Analyzer

RX Configuration/Amplitude RX configured for 100Ω differential termination (center tap to GND), AC coupled using both internal and external capacitors

Voltage Typical voltage

Temperature Room temperature

Frequency Sweep 50 MHz to 11 GHz (10 MHz steps)




Test Results

Figure 18 shows the receiver differential input return loss measurement.

Figure 19 shows the receiver common mode input return loss measurement.

Test Fixture ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136) with 1-inch board trace using a low-profile ZIF socket

REFCLK Not Used

Source Power 0 dBm

Averaging Calibration 1

Intermediate Frequency (IF) 100 Hz

Table 12: Receiver Differential and Common Mode Input Return Loss Test Setup and Conditions (Cont’d)

Parameter Value


Figure 18: Receiver Differential Input Return Loss Measurement


Figure 19: Receiver Common Mode Input Return Loss Measurement

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0 0.5 1.0 2.01.5 2.5

Frequency (GHz)

Loss

(dB

)

RPT119_18_051109

RXSDD11PCIe 2.0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0

0.0 0.5 1.0 2.01.5 2.5

Frequency (GHz)

Loss

(dB

)

RPT119_19_051109

RXSCC11PCIe 2.0


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