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Document Number DS40252 Rev 4-2
PCI Express to PCI-X Reversible Bridge
DATASHEET Revision 4
1545 Barber Lane Milpitas, CA 95035
PI7C9X130 Page 2 of 160 March 2018 Document Number DS40252 Rev 4-2 www.diodes.com Diodes Incorporated
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PI7C9X130 Page 3 of 160 March 2018 Document Number DS40252 Rev 4-2 www.diodes.com Diodes Incorporated
Date Revision Number Description
02/24/2006 0.1 First Draft of PI7C9X130 Data Sheet
03/20/2006 0.2 Correct INTA, B, C, D buffer type
Update configuration map and registers Update JTAG chain order
Add PCI/PCI-X selection information
04/07/2006 0.3 Update on configuration register bit definitions. 1) Bit [10, 7:2] of offset 40h 2) Bit [31:30] of offset 68h 3) Bit  of offset 70h 4) Bit [23:22] of offset 94h 5) Bit [7:1] of offset 164h
Correct typo of pin CLKRUN_L in pin assignment and JTAG section.
06/07/2006 0.4 Add Absolute Maximum Ratings
Correct pin description:
1. REQ_L as GPI and GNT_L as GPO 2. CLKOUT [8:0] as CLKOUT [6:0]
06/19/2006 0.5 Correct default setting for bit [31:30] of offset 68h
04/18/2007 0.7 Completed non-transparent function for address 28h 2Bh in the Configuration Register Map
Corrected pin HSEN (R3) in section 2.6 Miscellaneous Signals. Should read tie LOW if Hot
Swap is not used instead of tie HIGH
05/02/2007 0.8 Revised table 8-1 in section 8
Address bit corrected to equal 0
Address bit corrected to equal GPIO
05/15/2007 0.9 Revised PCIe Base Specification Compliancy from 1.0a to 1.1
06/08/2007 0.91 Corrected pin HSSW (T3) in section 2.6 Miscellaneous Signals. Remove
Tied high if hot swap function is not used.
07/13/2007 1.0 Corrected bit offset 110h from reserved to Advisory Non-Fatal Error Status Changed Logos and some font types
08/07/2007 1.1 Corrected Pin #s of GNT_L, GNT_L, GNT_, GNT_, GNT_ on
Table 14-1JTAG Boundary Scan Register Definition
09/28//2007 1.2 Recommendation of Pull-up Resistor for PI7C9X130 Control Signals added to section 16.3 of PI7C9X130 Datasheets; pin numbers of SMBCLK and SMBDAT are corrected under section 5.2.
Added PCIX Clock Detection to Chapter 9, Clock Scheme.
01/03/2008 1.3 Revised Ambient Temperature Maximum Ratings Compliancy
04/21/2008 1.4 Updated to revision D
04/24/2008 1.5 Added package thermal data. RREF pin description change. Removed CDM information
08/08/2008 1.6 Added Power-Up Sequencing Description
10/30/2008 1.7 Revised Product Ordering Info
07/01/2009 1.8 Added Extended Configuration Access / Data Register under section 7.1 and 7.4
01/20/2010 1.9 Added Asynchronous Clock Support to Section 19
03/29/2010 2.0 Revised configuration register definitions:
1) 7.4.31 bit[5:4] and bit[7:6] of PCI Data Buffering Control Register )Offset 40h) 2) 7.4.87 Extended Configuration Access Address Register (Offset E0h) 3) 7.4.88 Extended Configuration Access Data Register (Offset E4h) 4) 7.4.129 bit of Replay and Acknowledge Latency Timers (Offset 310h) 5) 7.5.24 bit[5:4] and bit[7:6] of PCI Data Buffering Control Register )Offset 40h) 6) 7.5.135 bit of Replay and Acknowledge Latency Timers (Offset 310h)
Revised Section 9 Clock Scheme
04/27/2011 2.1 Updated Section 2.2 PCI Express Signals
06/29/2011 2.2 Updated Section 2.3 PCI Signals (REQ_L [3:0], GNT_L [3:0]) Updated Section 7.5.9, 7.5.11, 7.5.12, 7.5.13, 7.5.34, 7.5.36, 7.5.37, 7.5.38 (bit[31:12]).
09/17/2012 2.3 Updated Section 7.4.70 Device Capability Register (bit[2:0])
Updated Section 7.5.76 Device Capability Register (bit[2:0])
04/15/2015 2.4 Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode
04/20/2016 2.5 Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode
Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode Updated Section 2.5 JTAG Boundary Scan Signals
PI7C9X130 Page 4 of 160 March 2018 Document Number DS40252 Rev 4-2 www.diodes.com Diodes Incorporated
PREFACE The datasheet of PI7C9X130 will be enhanced periodically when updated information is available. The technical information
in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X130 (PCI Express
Bridge) and provides technical information for designers to design their hardware using PI7C9X130.
06/02/2017 2.6 Updated Section 16.1 Absolute Maximum Ratings Updated Section 16.2 DC SPECIFICATIONS
Added Table 16-4 PCIe Reference Clock Timing Parameters
Added Table 16-5 PCI Express Interface - Differential Transmitter (TX) Output Characteristics Added Table 16-6 PCI Express Interface - Differential Receiver (RX) Input Characteristics
Added Section 16.5 Operating Ambient Temperature
09/27/2017 3 Added Section 16 Power Sequencing Updated Section 19 Ordering Information
Revision numbering system changed to whole number 03/16/2018 4 Updated Section 19 Ordering Information
Added Figure 18-4 PART MARKING
PI7C9X130 Page 5 of 160 March 2018 Document Number DS40252 Rev 4-2 www.diodes.com Diodes Incorporated
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PI7C9X130 Page 6 of 160 March 2018 Document Number DS40252 Rev 4-2 www.diodes.com Diodes Incorporated
TABLE OF CONTENTS
1 INTRODUCTION ............................................................................................................................................. 15
1.1 PCI EXPR