Internal Memory

INTERNAL MEMORY

Dr. Pardeep Kumar

In the last set of lectures …

• Computer Memory System Overview

• Cache Memory Principles

• Elements of Cache Design

• Pentium 4 Cache Organization

• ARM Cache Organization

In this set of lectures• Overview to semiconductor main memory

– Organization of main memory– DRAM and SRAM– Types of ROM– Chip Logic– Chip Packaging

• Error Correction– Hamming Code

• Advanced DRAM Organization

Main memory – History

• Initially, the main memory is organized as an array of doughnut-shaped ferromagnetic loops referred to as cores.

• The advent of, and advantages of, microelectronics has long since vanquished the magnetic core memory.

• We have already seen about the memory cores and microelectronics in previous lectures.

Overview to semiconductor main memory

– Organization of main memory– DRAM and SRAM– Types of ROM– Chip Logic– Chip Packaging

Organization of main memory

• The basic element of a semiconductor memory is the memory cell having the following properties:

– They exhibit two stable states, which can be used to represent binary 1 and 0.

– They are capable of being written into (at least once), to set the state.

– They are capable of being read to sense the state.

Memory Cell

• The cell has three functional terminals capable of carrying an electrical signal.– The select terminal,– The control terminal and– The data / sense terminal

Memory Cell

Overview to Random Access Memory (RAM)

• By random access we mean that the individual words of memory are directly accessed through wired-in addressing logic.

– It is possible both to read data from the memory and to write new data into the memory easily and rapidly through the use of electrical signals.

– RAM is a volatile storage medium. That is, it must be provided with a constant power supply. If the power is interrupted, then the data are lost. Thus, RAM can be used only as temporary storage

RAM technology types

• Dynamic RAM or DRAM

• Static RAM or SRAM

DRAM

• A dynamic RAM (DRAM) is made with memory cells that store data as charge on capacitors.

• The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0.

• Because capacitors have a natural tendency to discharge, DRAM require periodic charge refreshing to maintain data storage.

• The term dynamic refers to this tendency of the stored charge to leak away, even with power continuously applied.

DRAM cell

DRAM

• Although the DRAM cell is used to store a single bit (0 or 1), it is essentially an analog device.

• Why?

• Because the capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0.

SRAM

• A static RAM (SRAM) is a digital device that uses the same logic elements used in the processor.

• In a SRAM, binary values are stored using traditional flip-flop logic-gate configurations.

• A static RAM will hold its data as long as power is supplied to it.

SRAM cell

SRAM cell description

• Four transistors (T1, T2, T3, T4) are cross connected in an arrangement that produces a stable logic state.

• For logic state 1:– Point C1 is high and point C2 is low

• In this state,T1 and T4 are off and T2 and T3 are on.

• For logic state 0:– Point C2 is high and point C1 is low

• In this state,T1 and T4 are on and T2 and T3 are off.

SRAM cell description

• The address line is used to open or close a switch with the help of two transistors T5 and T6.

• For a write operation, the desired bit value is applied to line B, while its complement is applied to line B.

• For a read operation the bit value is read from line B.

Comparing DRAM and SRAM

• Both DRAM and SRAM are volatile.

• A DRAM memory cell is simpler and smaller than a SRAM memory cell.

• Thus, a DRAM is more dense (smaller cells equals more cells per unit area) and less expensive than a corresponding SRAM.

Comparing DRAM and SRAM

• As DRAM is more dense and less expensive than SRAM; DRAMs tend to be favored for large memory requirements like main memory, HDD, etc.

• Finally, SRAMs are generally somewhat faster than DRAMs. Hence, SRAM is used for cache memory (both on and off chip).

Overview to ROM

• As the name suggests, a read-only memory (ROM) contains a permanent pattern of data that cannot be changed. This means that a ROM is nonvolatile; that is, no power source is required to maintain the bit values in memory.

• Hence ROM can be used to store data / programs which need not be modified and used frequently. Some of the applications of ROM are– Microprogramming– Storing library subroutines for frequently wanted functions– System programs

Overview to ROM

• A ROM, originally has been created with the data actually wired into the chip as part of the fabrication process.

• This presents two problems:– The data insertion step includes a relatively large fixed

cost, irrespective of whether one or thousands of copies of a particular ROM are fabricated.

– There is no room for error. That is, if one bit is wrong, the whole batch of ROMs must be thrown out.

Types of ROM

• Programmable ROM (PROM)

• Erasable Programmable ROM (EPROM)

• Electrically Erasable Programmable ROM (EEPROM)

• Flash Memory

PROM

• When only a small number of ROMs with a particular memory content is needed, a less expensive alternative is the programmable ROM (PROM).

• Like the ROM, the PROM is nonvolatile and may be written into only once.

• For the PROM, the writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication.

• Special equipment is required for the writing or “programming” process. PROMs provide flexibility and convenience.

EPROM

• As with PROM, in the EPROM the writing process is performed electrically.

• Here, before performing a write operation, all the storage cells of a EPROM must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation.

• This erasure process can be performed repeatedly; each erasure can take as much as 20 minutes to perform.

• Thus as the name suggests, EPROM can be altered or modified with new data content multiple times.

EEPROM

• EEPROM is a read-mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes which needs to be modified are updated.

• EEPROM is more expensive than EPROM and also is less dense, supporting fewer bits per chip.

Flash Memory

• Flash memory were named so because of the speed with which it can be reprogrammed i.e. updated.

• An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip (as in EEPROM).

• Flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM.

Summarizing Semiconductor Memory Types

Chip Logic

• Like other integrated circuit products, semiconductor memory comes in packaged chips with each chip containing an array of memory cells.

• For semiconductor memories, one of the key design issues is the number of bits of data that may be read/written at a time.– At one end of the extreme, we may have W words of B bits each

read / written at a time.– At another end is the so-called 1-bit-per-chip organization, in

which data are read/written 1 bit at a time.

Typical 16Mb DRAM Organization

Chip Packaging

• An integrated circuit is mounted on a package that contains pins for connection to the outside world.

• We are going to consider an example EPROM package, which is an 8-Mbit chip organized as 1M * 8.

• In this case, the organization is treated as a one-word-per-chip package. The package includes 32 pins, which is one of the standard chip package sizes.

Pin description for the 8 – Mbit EPROM

• The address of the word being accessed. For 1M words, a total of 20 (220 = 1 M) pins are needed (A0–A19).

• The data to be read out, consisting of 8 lines (D0–D7).

• The power supply pin to the chip (Vcc).

• A ground pin (Vss).

• A chip enable (CE) pin which is used to indicate whether or not the address is valid for this chip.

• A program voltage (Vpp) that is supplied during programming (write operations).

8-Mbit EPROM Pin Diagram

Error Correction

• A semiconductor memory system is subject to errors which can be categorized as

– Hard failures and

– Soft errors.

• Both hard and soft errors are clearly undesirable, and most modern main memory systems include logic for both detecting and correcting errors.

Error correction general procedure


• The error correction code yields one of three results:

– No errors are detected. The fetched data bits are sent out.

– An error is detected, and it is possible to correct the error. The data bits plus error correction bits are fed into a corrector, which produces a corrected set of M bits to be sent out.

– An error is detected, but it is not possible to correct it. This condition is reported.


• Codes that operate in the above fashion are referred to as error-correcting codes.

• The error correcting code is characterized by the number of bit errors in a word that it can correct and detect.

• The error correcting code may be single bit or two bit error correcting code.

An example error correcting code – Hamming Code

• The simplest of the error-correcting codes is the Hamming code devised by Richard Hamming at Bell Laboratories.

Hamming error correcting code

Hamming code description

• M denotes the number of data bits.

• K denotes the number of check bits (known as the syndrome words / syndrome bits) and has the range between 0 to 2k – 1.

• An error could occur on any of the M data bits or K check bits, we must have

2K – 1 >= M + K

Relation between data bits and check bits

• The above inequality gives the number of bits needed to correct a single bit error in a word containing M data bits. For example, for a word of 8 data bits (M = 8), we have

– For K=1: we have 21 - 1 < 8 + 3

– For K=2: we have 22 - 1 < 8 + 3

– For K=3: we have 23 - 1 < 8 + 3

– For K=4: we have 24 - 1 > 8 + 4

• Thus, the eight data bits require four check bits.

Relation between data bits and check bits

Hamming code for 8 bit word

• We are going to consider an example with 8 data bits and 4 check bits which are arranged as shown below:


• Each check bit operates on every data bit whose position number contains a 1 in the same bit position as the position number of that check bit.

• For example, data bit positions 3, 5, 7, 9, and 11 (D1, D2, D4, D5, D7) all contain a 1 in the least significant bit of their position number and hence will be taken care by C1.

• Similarly, bit positions 3, 6, 7, 10, and 11 all contain a 1 in the second bit position and hence will be taken care by C2; and so on.


• The check bits are calculated as follows:

Hamming code example

Advanced DRAM Organization

• Some of the most widely used forms of DRAM organization are:

– Synchronous DRAM (SDRAM)– Rambus DRAM (RDRAM)– Double-data-rate SDRAM (DDR SDRAM)– Cache DRAM (CDRAM)

Synchronous DRAM (SDRAM)

• Unlike the traditional DRAM, which is asynchronous, the SDRAM exchanges data with the processor in synchronization with an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

Synchronous DRAM (SDRAM)

• During the SDRAM operation, the processor or other master issues the instruction and address information, which is latched by the SDRAM. The SDRAM then responds after a set number of clock cycles. Meanwhile, the master can safely do other tasks while the SDRAM is processing the request.

Rambus DRAM (RDRAM)

• RDRAM, developed by Rambus has been adopted by Intel for its Pentium and Itanium processors and has become the main competitor to SDRAM.

• RDRAM chips are vertical packages, with all pins on one side.

• The special RDRAM bus delivers address and control information using an asynchronous block-oriented protocol.

Rambus DRAM (RDRAM)

• The chip exchanges data with the processor over 28 wires no more than 12 centimeters long. The bus can address up to 320 RDRAM chips and is rated at 1.6 GBps.

• What makes this speed possible is the bus itself. Rather than being controlled by the explicit RAS, CAS, R/W, and CE signals used in conventional DRAMs, an RDRAM gets a memory request over the high-speed bus. This request contains the desired address, the type of operation, and the number of bytes in the operation.

RDRAM Structure

Double-data-rate SDRAM (DDR SDRAM)

• DDR DRAM was developed by the JEDEC Solid State Technology Association, the Electronic Industries Alliance’s semiconductor-engineering-standardization body.

• The drawback of traditional SDRAM is that it can only send data to the processor once per bus clock cycle. This drawback is being removed by double-data-rate SDRAM, which can send data twice per clock cycle, once on the rising edge of the clock pulse and once on the falling edge.

DDR SDRAM Timing

Cache DRAM• Cache DRAM (CDRAM), developed by Mitsubishi,

integrates a small SRAM cache (16 Kb) onto a generic DRAM chip.

• The SRAM on the CDRAM can be used in two ways:– First, it can be used as a true cache, consisting of a

number of 64-bit lines.

– The SRAM on the CDRAM can also be used as a buffer to support the serial access of a block of data.

Internal Memory

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