William Stallings Computer Organization and Architecture8th EditionChapter 5Internal Memory

Semiconductor Memory Types

Memory TypeCategoryErasureWrite MechanismVolatilityRandom-access memory (RAM)Read-write memoryElectrically, byte-levelElectricallyVolatileRead-only memory (ROM)Read-only memoryNot possibleMasksNonvolatileProgrammable ROM (PROM)ElectricallyErasable PROM (EPROM)Read-mostly memoryUV light, chip-levelElectrically Erasable PROM (EEPROM)Electrically, byte-levelFlash memoryElectrically, block-level

Semiconductor MemoryRAM Misnamed as all semiconductor memory is random accessRead/WriteVolatileTemporary storageStatic or dynamic

Memory Cell Operation

Dynamic RAMBits stored as charge in capacitorsCharges leakNeed refreshing even when poweredSimpler constructionSmaller per bitLess expensiveNeed refresh circuitsSlowerMain memoryEssentially analogueLevel of charge determines value

Dynamic RAM Structure

DRAM OperationAddress line active when bit read or writtenTransistor switch closed (current flows)WriteVoltage to bit lineHigh for 1 low for 0Then signal address lineTransfers charge to capacitorReadAddress line selectedtransistor turns onCharge from capacitor fed via bit line to sense amplifierCompares with reference value to determine 0 or 1Capacitor charge must be restored

Static RAMBits stored as on/off switchesNo charges to leakNo refreshing needed when poweredMore complex constructionLarger per bitMore expensiveDoes not need refresh circuitsFasterCacheDigitalUses flip-flops

Stating RAM Structure

Static RAM OperationTransistor arrangement gives stable logic stateState 1C1 high, C2 lowT1 T4 off, T2 T3 onState 0C2 high, C1 lowT2 T3 off, T1 T4 onAddress line transistors T5 T6 is switchWrite apply value to B & compliment to BRead value is on line B

SRAM v DRAMBoth volatilePower needed to preserve dataDynamic cell Simpler to build, smallerMore denseLess expensiveNeeds refreshLarger memory unitsStaticFasterCache

Read Only Memory (ROM)Permanent storageNonvolatileMicroprogramming (see later)Library subroutinesSystems programs (BIOS)Function tables

Types of ROMWritten during manufactureVery expensive for small runsProgrammable (once)PROMNeeds special equipment to programRead mostlyErasable Programmable (EPROM)Erased by UVElectrically Erasable (EEPROM)Takes much longer to write than readFlash memoryErase whole memory electrically

Organisation in detailA 16Mbit chip can be organised as 1M of 16 bit wordsA bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so onA 16Mbit chip can be organised as a 2048 x 2048 x 4bit arrayReduces number of address pinsMultiplex row address and column address11 pins to address (211=2048)Adding one more pin doubles range of values so x4 capacity

RefreshingRefresh circuit included on chipDisable chipCount through rowsRead & Write backTakes timeSlows down apparent performance

Typical 16 Mb DRAM (4M x 4)

Packaging

256kByte Module Organisation

1MByte Module Organisation

Interleaved MemoryCollection of DRAM chipsGrouped into memory bankBanks independently service read or write requestsK banks can service k requests simultaneously

Error CorrectionHard FailurePermanent defectSoft ErrorRandom, non-destructiveNo permanent damage to memoryDetected using Hamming error correcting code

Error Correcting Code Function

Advanced DRAM OrganizationBasic DRAM same since first RAM chipsEnhanced DRAMContains small SRAM as wellSRAM holds last line read (c.f. Cache!)Cache DRAMLarger SRAM componentUse as cache or serial buffer

Synchronous DRAM (SDRAM)Access is synchronized with an external clockAddress is presented to RAMRAM finds data (CPU waits in conventional DRAM)Since SDRAM moves data in time with system clock, CPU knows when data will be readyCPU does not have to wait, it can do something elseBurst mode allows SDRAM to set up stream of data and fire it out in blockDDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

SDRAM

SDRAM Read Timing

RAMBUSAdopted by Intel for Pentium & ItaniumMain competitor to SDRAMVertical package all pins on one sideData exchange over 28 wires < cm longBus addresses up to 320 RDRAM chips at 1.6GbpsAsynchronous block protocol480ns access timeThen 1.6 Gbps

RAMBUS Diagram

DDR SDRAMSDRAM can only send data once per clockDouble-data-rate SDRAM can send data twice per clock cycleRising edge and falling edge

DDR SDRAM Read Timing

Simplified DRAM Read Timing

Cache DRAMMitsubishiIntegrates small SRAM cache (16 kb) onto generic DRAM chipUsed as true cache64-bit linesEffective for ordinary random accessTo support serial access of block of dataE.g. refresh bit-mapped screenCDRAM can prefetch data from DRAM into SRAM bufferSubsequent accesses solely to SRAM

ReadingThe RAM GuideRDRAM